1. Microcontroller
8051

2. Contents Difference between Microprocessor and Microcontroller,
Block Diagram and Pin Description of the 8051

3. Microprocessors General-purpose microprocessor CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example：Intel’s x86, Motorola’s 680x0
Many chips on mother’s board
Data Bus
CPU
General-Purpose Micro-processor
Intel’s x86: 8086,8088,80386,80486, Pentium
Motorola’s 680x0: 68000, 68010, 68020,68030,6040
Serial COM Port
I/O Port
RAM
ROM
Timer
Address Bus
General-Purpose Microprocessor System

4. Microcontroller A smaller computer On-chip RAM, ROM, I/O ports...
Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X
CPU
RAM
ROM
A single chip
Serial COM Port
I/O Port
Timer
Microcontroller

5. Microprocessor vs. Microcontroller
Single chip computer which has everything in-built.
CPU, RAM, ROM, I/O and timer are all on a single chip.
fix amount of on-chip ROM, RAM, I/O ports.
Uses different program and data memory.
Suited to control of I/O devices requiring a minimum component count.
Extremely compact instructions.
Data bus: 8,16 bits wide.
10 to 20 MHz.
single-purpose.
Cheap.
Microprocessor
Dependent on other chips for many functions so hardware size increases.
CPU is stand-alone, RAM, ROM, I/O, timer are separate.
Designer can decide on the amount of ROM, RAM and I/O ports.
Program memory and data memory are same.
Suited to processing information in computer systems.
Powerful addressing mode.
Data bus: 32,64,128 bits wide.
Clock rate > 1GHz.
general-purpose.
Expensive.
versatility 多用途的: any number of applications for PC

6. Features of 8051 8-bit CPU 4 KB of on chip program memory.
128 bytes of on chip data memory.
64 KB program external ROM and 64 KB external RAM addressability.
32 bidirectional and individually addressable I/O lines arranged as four 8 bit ports P0-P3.
Two 16 bit timer/counters.
Full duplex serial data transmitter/receiver.
Four register banks.
8 bit program status word and stack pointer.
Interrupt structure with two priority levels.
On chip oscillator and clock circuits.
Binary or decimal arithmetic.
Power saving mode

7. 8051 Architecture

8. Functional Blocks of 8051
Eight bit register A (Accumulator) and register B.
Arithmetic and Logic Unit (ALU).
16 bit Program counter (PC).
16 bit Data Pointer (DPTR).
8 bit program Status Word (PSW).
8 bit stack pointer (SP).
128 byte Internal RAM and 4 KB Internal ROM.
Four 8 bit ports : Port 0, Port 1, Port 2, Port 3.
Two 16 bit Timer/counters, serial port and interrupt control.
Control Registers.
On chip oscillator.

9. Accumulator ( ACC ) B Register 8-bit Register.
It is a multipurpose register.
It holds operands & result of ALU operations.
Also used for data transfer between 8051 and any external memory.
Rotate, swap etc. specifically apply on the accumulator.
B Register
8-bit Register.
Used with the A register for multiplication and division operations.
For other instructions it is treated as a scratch pad register.

10. Arithmetic and Logic Unit ( ALU )
It can perform arithmetic and logic operations on eight bit data.
It can perform arithmetic operations like addition, subtraction, multiplication, division and logical operations like AND, OR, EX-OR, complement, rotate etc.
It also takes care of branching instructions.
Program Status Word ( PSW ) and Flags
8051 has
a) Four math flags
1) Carry 2) Auxiliary 3) Overflow 4) Parity
b) Three general purpose user flags
1) F0 2) GF0 3) GF1

11. Program Status Word ( PSW ) and FlagsCY AC F0
RS1 OV
RS0 P --
CY PSW.7 Carry flag
AC PSW.6 Auxiliary carry flag
-- PSW.5 Available to the user for general purpose
RS1 PSW.4 Register Bank selector bit 1
RS0 PSW.3 Register Bank selector bit 0
OV PSW.2 Overflow flag
-- PSW.1 User define bit
P PSW.0 Parity flag Set/Reset odd/even parity
RS1 RS0 Register Bank Address
RS1 RS0 Register Bank Address
H-07H
H-0FH
H-17H
H-1FH

12. Clock and Oscillator
Oscillator circuit generates the clock pulses to synchronize all internal operations.
Quartz crystal is used.
8051 requires frequencies ranging from 1 MHz to 16 MHz.

13. Program Counter ( PC ) Data Pointer ( DPTR ) It is a 16 bit register.
It is used to hold the address of a instruction in the memory
When power supply is switched on, the PC resets to 0000H.
Data Pointer ( DPTR )
It is a 16 bit register.
It is used to hold the address of data in the memory
It can be accessed separately as lower eight bits (DPL) and higher eight bits (DPH)
It serves as a base register in case of instructions handling look up tables and external data transfer.

14. Stack and Stack Pointer
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
(Stack) Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
The register used to access the stack is called SP (stack pointer) register.
The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.

15. Internal Memory Internal ROM
For proper operation of a computer system, the system should have memory for program code.
8051 has separate memory for the program and data having same address ranges.
Address space ranging from 0000 H to FFFF H.
Capacity from 0000 H to 0FFF H.
Internal RAM
805 1 has 128 byte Internal RAM organized as
1) Four register banks of 8 bytes each.
2) Bit addressable area of 16 bytes.
3) General purpose RAM area (scratch pad area).

16. Internal RAM structure
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
(Stack) Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM

17. Four register banks ( 8 bytes each)
Each bank is made up of eight registers named R0 to R7.
For selecting a register bank two bits RS0 and RS1 are provided in the PSW.
Can be used as a simple scratch pad RAM or general purpose RAM.
Upon power on or reset BANK0 is selected by default.
It reduces the latency period for a subroutine call or an interrupt. 1F 18
Bank 3 17 10
Bank 2 0F 08
Bank 1 07 06 05 04 03 02 01 00 R7 R6 R5 R4 R3 R2 R1 R0
Bank 0

18. Bit addressable area (16 bytes)2F 2E 2D 2C 2B 2A 29 28 7F 78 1A 10 0F 08 07 06 05 04 03 02 01 00
8051 has reserved 16 bytes of internal RAM (128 bits forming addressable bits).
Locations are called bit addressable locations.
Useful for binary event to remember e.g. open switch, close switch 27 26 25 24 23 22 21 20

19. General purpose RAM area
Scratch pad area.
Address range from 30 H to 7F H.
Used as a data RAM.
Programmer may declare stack in this area.

20. Special Function Registers (SFRs)
SFR memory consist of important registers like acc, B reg., interrupt control register, PSW, timer/counter, four I/O ports, serial control.
Some of these registers are bit addressable while remaining are byte addressable .
Bit addressable - P0, TCON, P1, SCON, P2, IE, P3, IP, PSW, ACC, B
Byte addressable – SP, DPL, DPH, PCON, TMOD, TL0, TL1, TH0, TH1, SBUF P1 P0

21. External Memory
Used in cases when the internal ROM and RAM memory available on chip is not sufficient.
External RAM of upto 64 KB is accessed by the DPTR.
External ROM of upto 64 KB can be added to any chip in the 8051 family.

22. Input / Output Ports 8051 has four ports named P0, P1, P2, P3.
All these ports are bi-directional.
Each of these 8 bit ports consists of a D-type output latch, an output driver and an input buffer.
Each pin of I/O ports
Internal CPU bus：communicate with CPU
A D latch store the value of this pin
D latch is controlled by “Write to latch”
Write to latch＝1：write data into the D latch
2 Tri-state buffer：
TB1: controlled by “Read pin”
Read pin＝1： read the data present at the pin
TB2: controlled by “Read latch”
Read latch＝1：read value from internal latch
A transistor M1 gate
Gate=0: open
Gate=1: close

23. D Latch:

24. Port 1 Port 2 Also called as “quasi-bidirectional” port.
Simple I/O port used as
1) Simple Input Port.
2) Simple Output Port.
Port 2
Also called as “quasi-bidirectional” port.
Multifunctioned port used as
1) Simple Input Port.
2) Simple Output Port.
3) Higher order address bus (A8-A15) for external memory.

25. A Pin of Port 1 P0.x 8051 IC Read latch Bit Vcc TB2 Load(L1) P1.X pin
D Q
Clk Q
Vcc
Load(L1)
Read latch Bit
Read pin Data
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB1
TB2
P0.x
8051 IC

26. Writing “1” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB2
2. output pin is Vcc
1. write a 1 to the pin 1
output 1
TB1
8051 IC

27. Writing “0” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB2
2. output pin is ground
1. write a 0 to the pin
output 0 1
TB1
8051 IC

28. Reading “High” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
2. MOV A,P1
external pin=High
TB2
write a 1 to the pin MOV P1,#0FFH 1 1
TB1
3. Read pin=1 Read latch=0 Write to latch=1
8051 IC

29. Reading “Low” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
2. MOV A,P1
external pin=Low
TB2
write a 1 to the pin
MOV P1,#0FFH 1
TB1
3. Read pin=1 Read latch=0 Write to latch=1
8051 IC

30. Other Pins P1, P2, and P3 have internal pull-up resisters.
P1, P2, and P3 are not open drain.
P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051.
P0 is open drain.
Compare the figures of P1.X and P0.X.
However, for a programmer, it is the same to program P0, P1, P2 and P3.
All the ports upon RESET are configured as output.

31. Port 0 Multifunctioned port of microcontroller used as
1) Simple Input Port.
2) Simple Output Port.
3) Multiplexed address / data bus (AD0 - AD7) for external memory.
D Q
Clk Q
Read latch
Read pin
Write to latch
Internal CPU bus M1
P0.X pin
P1.X
TB1
TB2

32. Port 0 with Pull-Up Resistors
DS5000
8751
8951
Vcc
10 K
Port 0

33. Port 3 Significance SBUF TCON.1 TCON.3 TL0 TL1 - P3 Bit Function SFR
Also called as “quasi-bidirectional” port.
Multifunctioned port used as
1) Simple Input Port.
2) Simple Output Port.
3) One of the alternate functions.
Significance
SBUF
Receive data pin for serial port in UART mode.
Transmit data pin for serial port in UART mode.
TCON.1
External Interrupt
TCON.3
TL0
External Timer / Counter 0 input pin.
TL1
External Timer / Counter 1 input pin. -
External memory write pulse.
External memory read pulse.
P3 Bit
Function
SFR
RxD
P3.0
P3.1
TxD
P3.2
INT0
P3.3
INT1
P3.4 T0
P3.5 T1
P3.6 WR
P3.7 RD

34. Some 8-bitt Registers of the 8051A B R0 R1 R3 R4 R2 R5 R7 R6
DPH
DPL PC
DPTR
Some bit Register
Some 8-bitt Registers of the 8051

35. RESET Value of Some 8051 Registers:PC
0000
ACC
0000 B
0000
PSW
0000 SP
0007
DPTR
0000
RAM are all zero. 

36. Pin Description of the 8051 8051 (8031)  1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL2
XTAL1
GND
(INT0)P3.2
(INT1)P3.3
(RD)P3.7
(WR)P3.6
Vcc
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051
(8031) 

37. Pins of 8051 Vcc（pin 40）： GND（pin 20）：ground
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GND（pin 20）：ground
XTAL1 and XTAL2（pins 19,18）
RST（pin 9）：reset
It is an input pin and is active high（normally low）.
The high pulse must be high at least 2 machine cycles.
It is a power-on reset.
Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. 

38. Power-On RESET Circuit
Vcc +
10 uF 31
EA/VPP X1
30 pF 19
MHz
8.2 K X2 18
30 pF
RST 9 

39. Pins of 8051 EA/VPP（pin 31）：external access
There is no on-chip ROM in 8031 and
The EA pin is connected to GND to indicate the code is stored externally.
For 8051, EA pin is connected to Vcc.
This pin also receives 12V, programming enable voltage (VPP), during flash programming.
PSEN（pin 29）：program store enable
This is an output pin and is connected to the OE pin of the external ROM.
PSEN ＆ ALE are used for external ROM.
Read strobe to external memory.

40. Pins of 8051 ALE / PROG（pin 30）：address latch enable
It is an output pin and is active high.
8051 port 0 provides both address and data.
The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
This pin is also program pulse input (PROG) during flash programming.
PROG = 0, enters into flash programmable mode.
= 1, enters into normal execution mode.

41. Pins of 8051 The 8051 has four I/O ports
Port 0 （pins 32-39）：P0（P0.0～P0.7）
Port 1（pins 1-8） ：P1（P1.0～P1.7）
Port 2（pins 21-28）：P2（P2.0～P2.7）
Port 3（pins 10-17）：P3（P3.0～P3.7）
Each port has 8 pins.
Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X
Ex：P0.0 is the bit 0（LSB）of P0
Ex：P0.7 is the bit 7（MSB）of P0
These 8 bits form a byte.
Each port can be used as input or output (bi-direction).
Program is to read data from P0 and then send data to P1 

42. Timers / Counters Two 16 bit Timer / Counter register namely Timer 0
and Timer 1.
Timer: Register is programmed to count the internal
clock pulse.
Internal clock pulses are generated from a constant clock generator, the count loaded in the register gives constant time.
Register is incremented every machine cycle (1 machine cycle = 12 oscillator periods)
Counting rate is 1/12 of the oscillator frequency.

43. Timers / Counters Counter: microcontroller is programmed to count
external pulses.
The register is incremented in response to high to low transition of the corresponding external input pin, T0 and T1.
The external input does not have a constant frequency and hence it is not used for timing reference.
T0 and T1 pins are sampled during S5P2 of every machine cycles.
When the samples show high in one cycle and low in the next, the count is incremented.
The new count value is appears in S3P1 of the following detection cycle.
Hence in order to recognize the high-low transition the microcontroller requires two machine cycle i.e. 24 oscillator periods.
Max count rate is 1/24 of oscillator frequency

44. Timers / Counters The counter / timer registers are divided into 8 bit
Timer low (TL0 and TL1)
Timer high (TH0 and TH1)
TL0 and TH0 together form the 16 bit Timer 0.
TL1 and TH1 together forms the 16 bit Timer 1.
Counter action is controlled by the bits in the
Timer mode control register (TMOD).
Timer / Counter control register (TCON).

45. TMOD register
GATE: Gating control. When set, timer only runs while INT(0,1) is high. (pulse width measurement)
C/T: Counter or Timer Selector
M1 M0:
00: 8-bit Timer/Counter with 5-bit prescaler
01: 16-bit Timer/Counter
10: 8-bit auto reload Timer/Counter
11: (Timer0) TL0 is 8-bit Timer/Counter controlled by Timer0 control bits TH0 is 8-bit timer only controlled by Timer1 control bits
11: (Timer1) Timer/Counter is stopped

46. TCON register TF: Overflow flag TR: Run control bit.
Set by hardware on timer / counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
TR: Run control bit.
Set / cleared by software to turn Timer / Counter on / off.
IE: Interrupt Edge Flag.
Set by hardware when external interrupt edge detected.
Cleared when interrupt processed.
IT: Interrupt Type control bit.
Set / cleared by software to specify falling edge / low level triggered external interrupt.

47. Mode 0
Timer operates as a 13 bit register (TL – 5 bits and TH – 8 bits)
5 bits in the TL sets the divide by 32 prescalar to the TH as an 8 bit counter.
Interrupt
If the user desires some count in the register and gives command by TR1 bit the timer / counter will start.
If Timer count exceeds 13 bit i.e. 1FFFH the next count will be 0000H.
It causes the microcontroller to generate an interrupt in order to inform the programmer whether one cycle is over.
To indicate it, Timer overflow bit TF1 will be set.
If the timer interrupt is enabled using the IE register, the controller will vector to ISR routine

48. Mode 1
Same as Mode 0.
Timer / counter operates as a 16 bit register.

49. Mode 2
Timer / Counter register is configured as an 8 bit counter (TL) with auto reload facility.
TL1 acts as the basic timer / counter.
When the Timer starts working, it keeps on incrementing and it will overflow.
This will set the timer interrupt flag TF1 and it also reloads the contents of TH1 to TL1.
The reloading operation will not alter the contents of TH1.

50. Mode 3
Timer 1 is not used, Timer 1 simply holds its count. The timer 0 register TL0 and TH0 are configured as two separate 8 bit counters.
TL0 register uses the Timer 0 control bits C / T, GATE, TR0, INT0 and TF0. TH0 counts the machine cycles. It takes over the use of TR1 and TF1 from Timer 1
When the Timer 0 is in mode 3, Timer 1 may be used in modes 0,1,2 and no interrupts will be generated because Timer 0 is using the TF1 flag.

51. Serial Data Input and Output
For communication between two computer system we can send and receive the data bits serially.
Supports full-duplex serial communication
Serial port receive and transmit registers are both accessed through Special Function Register SBUF
Writing to SBUF loads the transmit register
Reading from SBUF accesses a physically separated receive register
SCON - Serial Port Control / Status Register controls the data communication.
PCON register along with timer 1 controls the data rates.
SBUF register comprises of two registers physically via
TXD Pin
RXD Pin
Double buffered receiver is used.
Serial data communication is a relatively slow process, so in order not to tie up with valuable processor time, serial data flags are included in SCON to aid in efficient data transmission and reception.

52. SCON Register
SM2
SM0 SM1:
00: Mode 0, Shift register, fosc//12
01: Mode 1, 8-bit UART, variable
10: Mode 2, 9-bit UART, fosc//32 or fosc//64
11: Mode 3, 9-bit UART, variable
SM2: Enables multiprocessor features in Mode 2 and Mode 3
In Mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0.
In Mode 1, if SM2 is set to 1 then RI will not be activated if valid stop bit was not received.
In Mode 0, SM2 should be 0
REN: Enables serial reception
Set/Clear by software

53. SCON Register
TB8: 9th data bit that will be transmitted in Mode2 and Mode3
Set/Clear by software
RB8: 9th data bit that was received in Mode2 and Mode3 In Mode 1, if SM2=0, is the stop bit that was received
TI: Transmit interrupt flag
Set by hardware. Must be cleared by software
RI: Receive interrupt flag

54. Mode 0 Half duplex synchronous mode referred as shift register.
Mode 0 Tx
Half duplex synchronous mode referred as shift register.
Shift register has shift left, shift right operation. The shifting operation of data bits is sequentially done.
Input to the shift register is data and clock.
Serial data is transmitted and received through the RXD line.
The clock is generated by the TXD line, TXD shift clock is a square wave, low for states S3, S4 and S5 of the machine cycle, while high for S6, S1and S2.
Eight bit are transmitted at a time, the start and stop bits are not required. The LSB of data is transmitted and received first.
Shift data In at S5P2 and shift data Out at S6P2.
Baud rate = oscillator frequency / 12.
Raising-edge trigger
Mode 0 Rx

55. Mode 1 stop synchronization event
Full duplex mode. It supports 8 bit asynchronous communication. Whether there is a change in data 1 is transmitted, otherwise 0 is transmitted.
Serial data enters through RXD, exits through TXD
Although the data bits are 8 bit, the number of transmitted bits are 10 i.e. 1 start bit, 1 stop bit and 8 data bits.
Start bit is discarded, 8 bit data go to SBUF and stop bit goes into RB8 in SCON register.
Baud rate is variable, determined by timer 1 overflow rate.
Timer is used in mode 2 as an auto reload 8 bit timer.
Baud rate = (2SMOD / 32) * (oscillator frequency / 12 + (256 – (TH1)))
SMOD is a control bit in the PCON register, it can be 0 or 1.
If timer 1 is not in mode 2 then the baud rate is
Baud rate = (2SMOD / 32) * (timer 1 overflow rate)

56. Mode 2 Mode 2 Serial data enters through RXD, exits through TXD
11 bits are transmitted/received:
start bit(0), 8 data bits (LSB first), a programmable 9th bit, stop bit(1)
On transmit, the 9th bit is TB8 in SCON register
On receive, the 9th bit goes into RB8 in SCON register, both start and stop bits are discarded.
Baud rate is higher for many multiprocessor applications.
The baud rate is programmable to either
1/32 or 1/64 the oscillator frequency
Baud Rate =[(2SMOD)/64]*Oscillator frequency
Mode 2
Same as MODE 2 in all respects except baud rate
The baud rate is variable

57. Interrupts External asynchronous input applied to the microcontroller.
8051 supports five interrupts
Three interrupts that are Automatically generated by internal operations – TF0, TF1 and serial port interrupt (RI or TI).
Two interrupts that are triggered by external signals are - INT0 and INT1
All interrupt functions are under program control.
By setting or clearing the bits in IE, IP and TCON register the programmer can block any or all of the interrupt.

58. Interrupts 5 interrupt sources 2 external (INT0, INT1)
2 timers (TF0, TF1)
Serial Port (RI or TI)

59. Timer flag interrupt Serial Port interrupt Part 4
When the timer / counter overflows, the corresponding timer flag TF0 or TF1 is set to 1. The flag is cleared to 0 when the interrupt generates program call to the timer subroutine in the memory.
Interrupts are generated by TF0 and TF1 in register TCON
When a timer interrupt is generated, the flag that generated it is cleared by hardware when the service routine is vectored to
Serial Port interrupt
generated by the logical OR of bits RI and TI in register SCON, to provide a single interrupt to the processor.
The TI bit in the SCON register is set when a data byte is transmitted and the RI bit in the SCON register is set whenever a data byte is received.

60. External interrupts
Two interrupts that are generated by external circuits are INT0 and INT1.
These interrupts may be edge triggered or they may be level triggered.
Level-activated or transition-activated depending on bits IT0, IT1 in register
TCON
The inputs on the pins of these interrupts sets the interrupt IE0 and IE1 in the
TCON register.
The flags that generate these interrupts are IE0, IE1 in TCON
Cleared by hardware if the interrupt was transition-activated
if the interrupt was level-activated, external source controls request bits
If external interrupt is level-activated, the external source has to hold request
active, until the requested interrupt is actually generated.
External source has to deactivate the request before interrupt service is
completed, or else another interrupt will be generated.

61. Interrupt Enable register (IE)
EA: Enable/Disable all interrupts
If EA=0 no interrupts will be acknowledged
If EA=1 each interrupt source is individually enabled/disabled
ES: Serial Port interrupt enable bit
ET: Timer interrupt enabled bit
EX: External interrupt enable bit

62. Interrupt Priority register (IE)
Priority bit=1: High Priority; Priority bit=0: Low Priority
PS: Serial Port priority bit
PT: Timer priority bit
PX: External priority bit

63. Interrupt Priority