What is ECE200 about? The high-level hardware organization… Above logic design such as gates and state machines and the low-level assembly language software… Below high-level languages like C++ …of computer systems In other words, the answers to 3 questions What are the tradeoffs in designing the assembly/machine language for a computer? Once the assembly language has been specified, what are the tradeoffs in designing the processor and memory hierarchy? (the bulk of the course) How do I take the resulting microprocessor and build a useful system (including input/output) around it?
Administrative info Instructor: Professor Dave Albonesi Office: CSB411 Email: email@example.com@ece.rochester.edu Phone: 5-3870 Office hours: Monday/Wednesday 2-2:30 and by appointment Course web page www.ece.rochester.edu/~albonesi/ece200.html TAs: Ruke Huang, firstname.lastname@example.org@ece.rochester.edu Muhammad Rashid, email@example.com@ece.rochester.edu Rong Song, firstname.lastname@example.org@ece.rochester.edu Office hours: TBD All lab and homework grading questions should be directed to the TAs first
Course sections Lectures Monday, Wednesday, Friday 1-1:50pm, CSB209 Recitation Friday 2-3:15pm, CSB523 Run by TAs Cover homework/exam solutions, detailed problems, tools No recitation this week Labs Tuesday, Thursday, 4:50-6:20pm, Hopeman 202 Run by TAs No lab this week
Course details Textbooks Computer Organization and Design: The Hardware/Software Interface, Patterson and Hennessy, 2 nd edition (check www.mkp.com for errata), Morgan Kaufmann Publishers, 1998 Chapters 1-7, parts of 8 and 9 Maybe the Motorola HC11 reference manuals (provided later) Prerequisites ECE112 ECE114 Grading 30% homework 30% labs 20% midterm 20% final
Homeworks Designed to go a step beyond the lecture material The homework for a chapter should be turned in in class one week after we finish the chapter in lecture 20% penalty assessed for each day late Homework concepts can be discussed together, but solutions must be generated independently by each student Violations may result in failing the course Homework solutions will be posted outside my office five days after the assignment is due
Labs Design and test a processor using VHDL and Altera (using knowledge gained in ECE112) Gradually build up over the course of the semester Each lab group (maximum 2-3 students) must work independently of all others Violations may result in failing the course
How to do well in this class Come to lectures and come prepared Read book sections that we will be covering in advance Resist the temptation to skip class and download the slides We will cover some things beyond the slides that will appear on the exams Hit the homework problems related to a chapter section right after we finish it in lecture Waiting until the last minute will be disastrous for later chapters Don’t wait until the last minute to start the labs Start studying for the midterm and final a week in advance Material is not that hard, but there is a wealth of it Come to office hours if you don’t understand something from lecture