1. CSC 3210 Computer Organization and Programming Chapter 8 MACHINE INSTRUCTIONS D.M. Rasanjalee Himali

2. Outline Instruction Codes Instruction Decode Format Three Instructions Format One Instruction: The call Instruction Format Two Instruction

3. Instruction Codes Instructions on SPARC architecture occupy one word, 32 bits All information needed to execute the instruction is encoded in the instruction word These 32 bits are divided into fields -- contiguous subsets of the bits. We need to define fields to specify the instruction's opcode, and fields to specify the instruction's arguments (operands).

4. Instruction Codes The format of the instruction should be uniform and as simple as possible. A typical scheme is given below: 8 bits –  To specify the instruction (we get 256 instructions) 5 bits (each)–  For address of the three registers (32 different registers) 1 bit –  To specify if second argument is a source register or constant 8 bits –  Remaining 8 bits either combined with 5 bits used for second source register for 13 bit signed immediate constant or to provide additional 8 bits to specify floating point instructions.

5. Instruction Decode The division of the instruction into fields in done in three different ways, called formats. The format is specified in the first two bits of the instruction (op filed): The 8 bits of the instruction opcode are divided into 2 parts:  op - 2 bits (which specifies instruction formats)  op3 - 6 bits Instruction Classes Specified by op: The Format three instructions are then decoded using the least significant bit of op with the remaining six bits of the op3 field. OPINSTRUCTION CLASSFORMAT 00Branch InstructionFormat 2 01Call InstructionFormat 1 10Format three instructionFormat 3 11Format three instructionFormat 3

6. Format 3 Instructions Majority of instructions executed are Format 3 instructions There are two possibilities for Format 3 instructions: op rs1, rs2, rd or op rs1, imm, rd  where "imm" is an immediate value, that is, value is coded right into the instruction.

7. Format 3 Instructions Case1: op rs1, rs2, rd :  op: 10 or 11, indicating that this is a format 3 instruction  rd: numeric ID of destination register  op3: encoding of opcode  rs1: numeric ID of first source register rs2: numeric ID of second source register rs20rs1op3rdOp 3130292524191814131254 2565185 empty 0

8. Format 3 Instructions Case2: op rs1, imm, rd:  op: 10 or 11, indicating that this is a format 3 instruction  rd: numeric ID of destination register  op3: encoding of opcode  rs1: numeric ID of first source register Signed immediate 13 bit constant1rs1op3rdOp 313029252419181413120 2565113

9. Format 3 Instructions The way the processor tells these two cases apart is by the 1 or 0 right after the rs1 field. Note that the signed constant is only allotted 13 bits. This is a consequence of our decision to limit all instructions to exactly 32 bits in size. The immediate value is encoded in two's complement, so the range of values we can encode is -4096 to +4095. Thus, if we try to use an immediate value in a format 3 instruction that is out of this range, the assembler will complain -- it just can't fit such a value in there.

10. Format 3 Instructions There are two tables:  with op = 10 and the  with op = 11. The instructions with op = 10 are three-address register instructions, such as add and sub. The instructions with op = 11 are the load/store instructions, all of which refer to memory.

11. Format Three Instructions Unimplemented instructions are listed as unimp. Three-Address Register `(Non-load-store) (op =10) Load-store (op=11)

12. %rs1 = %l0 = %r16 Format 3 Instructions Ex:  sub %l0, 5, %o0  The instruction may be written as the hexadecimal constant 0x90242005: 00000000001011100000001000100010 Signed constant = 5i= 1op3 %rd = %o0 = %r8 op The numeric IDs of registers are as follows: %g0 - %g7 -- 0 to 7 %o0 - %o7 -- 8 to 15 %l0 - %l7 -- 16 to 23 %i0 - %i7 -- 24 to 31 2565113

13. Ex:  st %l0,[%fp+ -24] %rs1 = %fp =%i6 %r30 11111111010001111100001001000011 Signed constant = 5i= 1op3 %rd = %o0 = %r16 op 2565113 Format 3 Instructions +24 0000000011000 -24: 1’s comp1111111100111 +1 2’s comp1111111101000

14. Format 3 Instructions The program: These are all Format Three instructions and may be decoded as follows:

15. Format One Instruction: The call Instruction There is only one Format One instruction, the call instruction. The target of such a transfer must be an instruction and thus word aligned. A word-aligned address has the least significant two bits, both zero, Address is calculated by right shifting displacement 2 positions A Format One call instruction contains an op field of followed by 30 bits of address. The address to which control is transferred = (displacement<<2) +pc 0130 bit displacement 31 30 29 0

16. Example Displacement = ox4059 = (0x207dc – 0x10678)>>2 0x10660 : save %sp, -96, %sp 0x10664 : clr %l0 0x10668 : b 0x10694 0x1066c : nop 0x10670 : mov %l0, %o0 0x10674 : mov 0xa, %o1 0x10678 : call 0x207dc 0x1067c : nop (gdb) x/xw *&for+8 0x10678 : 0x40004059 (gdb) x/xwt *&for+8 0x10678 : 01000000000000000100000001011001 01000000000000000100000001011001

17. Format Two Instructions Two instructions:  branch instructions and the sethi instruction.  The op field for Format Two instructions is 00. branch: sethi: 0 0 a cond op2 22 bit displacement 31 30 29 28 25 24 22 21 0 0 0 rd 1 0 0 22 bit displacement 31 30 29 25 24 22 21 0

18. Branch Instructions the target of the branch is stored relative to the program counter right-shifted two bits. Only 22 bits are available for the displacement, so that the target of branches may be only ±2 21 instructions from the program counter. 0 0 a cond op2 22 bit displacement 31 30 29 28 25 24 22 21 0 214322

19. Branch Instructions The branch is (or is not) taken based on the “cond” (condition) field. op2 = 010 means integer condition code branch, the type of branch we have been using If the branch is to be annulled, the a bit is set.

20. Branch Instructions Four-bit field cond specifies the condition under which branching is to occur:

21. Branch Instructions

22. Example 0 0 0 1000 010 0000000000000000000011 214322 b 0x10694 Destination is three instructions away from this instruction Branch Target

23. Sethi Instruction Loading 32-Bit Constants: So far we have worked only with small constants in our programs. We were limited by the 13-bit signed- immediate field of the instruction. If we need a larger constant, we will need to use the sethi instruction, which will load the high 22 bits of a register while clearing the low 10 bits.

24. Loading 32-Bit Constants The annul bit field and the cond fields are combined to form a five-bit rd field, the register into which the constant is to be loaded. Op2 = 100 in sethi instruction The execution of this instruction results in the 22-bit immediate constant being loaded into the left-hand 22 bits of the register rd with the low 10 bits of the register cleared to zero. 0 0 rd 1 0 0 22 bit immediate 31 30 29 25 24 22 21 0 25322

25. Loading 32-Bit Constants To load a 32-bit constant, two instructions are needed:  a sethi to load the high 22 bits,  followed by an or instruction to “ or ” in the low 10 bits of the constant. For example, to load register %o0 with32 bit constant 0x30cf0034, we would write: The machine provides 2 arithmatic operators to do this shifting of 10 bits to right and get low 10 bits : %hi and %lo  %hi(x) is x>>10  %lo(x) is x & 0x3ff All 1s in last 10 bits

26. Loading 32-Bit Constants Thus to load a constant 0x30cf0034 into %o0 we could write: sethi %hi(0x30cf0034), %o0 or %o0, %lo(0x30cf0034), %o0 We could write above 2 instructions in one as below (preferred):

27. Appendix : Register Addresses