1. T. Hemperek VERIFICATION OF COMPLEX MIXED SIGNAL ASICS System-Verilog and UVM mini workshop 14 th November 2013

2. Moore's law in HEP 2 NameD-OMEGA IonLHC1FE-I3FE-I4FE-I5 Year 1991~1996~2005~2011??? Technology Node 3 µm1µ0.25 µm0.13 µm65 nm?? Chip size 8.3x6.6 mm 2 8x6.35 mm 2 10.8x7.6 mm 2 10.2x19 mm 2 ??? Pixel size 75x500 µm 2 50x500 µm 2 50x400 µm 2 50x250 µm 2 25x125 µm 2 ?? Pixel array 16x6316x12718x16080x336??? Transistor count ??? 800k3.5M80M1G?

3. Switch to big “D”, little “A” 3 Same pattern for HEP

4. Verification 4 Verification plan Simulation Assertion based verification Formal verification Mixed signal verification FE-I4

5. Verification Plan 5

6. Simulation – Unified Verification Methodology 6

7. Assertions based verification 7 A pattern describes a proven solution to a recurring design problem // A start can only occur after a grant for an active requestassert property (@(posedge clk) disable iff (~rst_n)req[*1:8] ##0 grant ##1 req |-> start);

8. Formal verification 8 // SystemVerilog Assertion property p_arb; @(posedge clk) req |=> ##[0:2] gnt; endproperty assert property (p_arb);

9. Static verification checking and simulation 9

10. Metric Driven Verification 10

11. MS Verification 11

12. Accuracy versus performance 12 Source: Cadence Design Systems

13. Modeling feature chart 13

14. FE-I4 Top View 14 ANALOG ARRAY (digital part) ANALOG ARRAY (digital part) DIGITAL ARRAY DIGITAL ARRAY END OF COLUMN END OF CHIP COMMAND DECODER REGISTER MEMORY PLL DATA OUTPUT - verilog model - Implementation (rtl/gate)

15. FE-I4 Verification environment 15 For FE-I4 we heve 4 OVC: - PIX - CMD - REVEIVE - MANUAL FE-I4 DETECTOR (PIX) OUTPUT (RECIVE) MANUAL SLOW COMAND (CMD)

16. Questions? 16

17. UVM register model 17

18. System Verilog 18

19. A UVM layer for PyHVL 19 http://www.fivecomputers.com/a-uvm-layer-for-pyhvl.html