1. Renesas Electronics America Inc. © 2012 Renesas Electronics America Inc. All rights reserved. Class ID: ADC Resolution: Myth and Reality Mitch Ferguson, Applications Engineering Manager CC19I

2. © 2012 Renesas Electronics America Inc. All rights reserved.2 2 Mr. Mitch Ferguson Applications Engineering Manager Specializes support design teams develop analog and low- noise systems using MCUs. Over 15 years of system-level design experience Over 10 years of experience as an application engineer. As a hardware engineer and engineering manager, he has been involved in design in power distribution controls, automotive and fire alarm systems. Bachelor of science in electrical engineering from Cleveland State University

3. © 2012 Renesas Electronics America Inc. All rights reserved.3 Renesas Technology & Solution Portfolio

4. © 2012 Renesas Electronics America Inc. All rights reserved.4 Microcontroller and Microprocessor Line-up Wide Format LCDs  Industrial & Automotive, 130nm  350µA/MHz, 1µA standby 44 DMIPS, True Low Power Embedded Security, ASSP 165 DMIPS, FPU, DSC 1200 DMIPS, Performance 1200 DMIPS, Superscalar 500 DMIPS, Low Power 165 DMIPS, FPU, DSC 25 DMIPS, Low Power 10 DMIPS, Capacitive Touch  Industrial & Automotive, 150nm  190µA/MHz, 0.3µA standby  Industrial, 90nm  200µA/MHz, 1.6µA deep standby  Automotive & Industrial, 90nm  600µA/MHz, 1.5µA standby  Automotive & Industrial, 65nm  600µA/MHz, 1.5µA standby  Automotive, 40nm  500µA/MHz, 35µA deep standby  Industrial, 40nm  200µA/MHz, 0.3µA deep standby  Industrial, 90nm  1mA/MHz, 100µA standby  Industrial & Automotive, 130nm  144µA/MHz, 0.2µA standby 2010 2012 32-bit 8/16-bit

5. © 2012 Renesas Electronics America Inc. All rights reserved.5 Collecting, analyzing and transmitting real-world signals is a major focus of the smart society. Real-world signals are analog, so converting these signals to digital is a key focus for the smart Understanding the specifications and hidden errors in ADC circuits will enable designs that meet the intended specifications ‘Enabling The Smart Society’

6. © 2012 Renesas Electronics America Inc. All rights reserved.6 Agenda What does the “resolution” spec really mean Some standard converters and resolution DC accuracy specifications Review offset, gain, DNL and INL errors How the ADC is tested What those errors don’t tell you AC specifications SNR ENOB System errors and resolution requirements ADC required accuracy Reference errors Source impedance errors

7. © 2012 Renesas Electronics America Inc. All rights reserved.7 Resolution What does the term resolution mean to you?

8. © 2012 Renesas Electronics America Inc. All rights reserved.8 8 Successive Approximation (SAR) ADC DAC (R2R Ladder) Comparator Vref AVss ADC Register Sample and Hold Circuit Input Analog Mux AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 DC Specs primarily define this section of ADC performance

9. © 2012 Renesas Electronics America Inc. All rights reserved.9 9 Slope Converter R GPIOTimer Vref Enable CPU Start Conversion Vcc Measure value R – Thermistor or sensor Operation – Stopped GPIO = L Timer stopped – Begin conversion GPIO = Hi-Z Timer started Comp out = H – Conversion ends Vc > Vref Comp out = L Timer stops Timer value is proportional to RC time constant Resolution? L H StoppedStarted L Clock

10. © 2012 Renesas Electronics America Inc. All rights reserved.10 Delta Sigma Converter Vin ∫ ∑ Ref Digital Filter D CK 4V H H 0V 5V +V Result Register

11. © 2012 Renesas Electronics America Inc. All rights reserved.11 Delta Sigma Converter Vin ∫ ∑ Ref Digital Filter D CK Result Register Oversampling frequency (flip flop clock rate, e.g. RX21A 3.125MHz) Minimum Conversion time – rate the result register is updated (81.92 uS or 12.2 kHz on RX21A ) – This is based on the decimation factor of the digital filter – Some converters allow reducing decimation factor Faster conversion Lower resolution

12. © 2012 Renesas Electronics America Inc. All rights reserved.12 Oversampling Oversampling can increase resolution of ADC 00 01 ADC Transition Voltages S1S2S3S4 02 03 ADC Input Voltage S1S2S3S4 Result will be 04 when samples are added Result will still be 04 when samples are added if no noise x x x x x x x x

13. © 2012 Renesas Electronics America Inc. All rights reserved.13 Oversampling How noise helps oversampling 00 01 ADC Transition Voltages S1 S2 S3 S4 02 03 ADC Input Voltage Result is now 06 x x x x ADC Input Voltage with noise

14. © 2012 Renesas Electronics America Inc. All rights reserved.14 Oversampling 00 01 ADC Transition Voltages S1 S2 S3 S4 02 03 ADC Input Voltage Result is now 04 x x x x ADC Input Voltage with noise Oversample 2X results in ½ bit increase resolution To increase resolution by n bits – Oversample 4 n and decimate 2 n

15. © 2012 Renesas Electronics America Inc. All rights reserved.15 ADC Accuracy Specifications

16. © 2012 Renesas Electronics America Inc. All rights reserved.16 An Explanation of DC Specifications DC accuracy specifications These specifications look at DC or very low frequency input errors Ideal Curve Offset Error Corrected Curve Non-Linearity Error Absolute Error Input Voltage ADC Counts Full Scale Vfull Scale 0V Real Curve

17. © 2012 Renesas Electronics America Inc. All rights reserved.17 AC Specifications DC testing does not describe dynamic characteristic Sample and hold errors AC noise errors Comparator hysteresis AC testing method Input sine wave to ADC input Perform FFT Measure SNDR, SNR and/or Spurious Free Dynamic Range SNR, SNDR – Ratio of RMS value to noise SNDR (SINAD) includes harmonics or distortion SFDR - ratio of the RMS value of input sine wave to the RMS value of the largest spur

18. © 2012 Renesas Electronics America Inc. All rights reserved.18 SNDR Results Why does SNDR go down as PGA gain goes up SNDR calculation range 17Hz1.71kHz PGA Gain SNDR x186.58dB x286.37dB x481.38dB x878.37dB x1674.71dB x3271.49dB x6464.74dB (PGA x1)

19. © 2012 Renesas Electronics America Inc. All rights reserved.19 Interpreting We can calculate the equivalent perfect ADC from equation ENOB = (SNDR -1.76)/ 6.02 The 6.02 term in the divisor converts decibels (a log 10 representation) to bits (a log 2 representation). The 1.76 term comes from quantization error in an ideal ADC 86 dB would then have the equivalent resolution of a 14 bit perfect ADC ENOB = log 2 [full-scale input voltage range/(ADC RMS noise × √12)]

20. © 2012 Renesas Electronics America Inc. All rights reserved.20 Interpreting Specification AC testing does not provide linearity data DNL and INL do affect SNDR DNL affects SNR INL affect THD Oversampling is still valid and reduces the average noise if Gaussian distribution

21. © 2012 Renesas Electronics America Inc. All rights reserved. 21 Example

22. © 2012 Renesas Electronics America Inc. All rights reserved.22 Understanding the Errors an Example Requirements Input = 0V – 2.0V +/-.25% of full scale accuracy (+/- 5 mV) Vref = 3.0V ADC range and resolution LSB must be < 10 mV – 0.25% * 2.0V = 10 mV – 10 mV / 3.0V = 1/300 – 9 bit ADC required Decreasing Vref to 2.5V – 10 mV / 2.5V = 1/250 – 8 bit ADC meets resolution requirement

23. © 2012 Renesas Electronics America Inc. All rights reserved.23 Understanding the Errors an Example Output Code Assume Vref = 2.56V, 8 Bit ADC (10 mV per step) Actual Voltage (mV) 0 5 10 20 30 40 00 01 02 03 Indicated Voltage (mV) 0 10 mV 20 mV 30 mV 04 40 mV 15 ½ LSB Offset

24. © 2012 Renesas Electronics America Inc. All rights reserved.24 Understanding the Errors an Example Can we use a 10 bit ADC with +/- 2 bits INL Each LSB error = 2.5mV (2.56V / 1024) Error for 2 LSB = 5 mV 5 mV/2.0V = 0.25% But there is still an additional ½ LSB quantization error 6.25 mV total error = 0.31% What about 1 bit of error Worst case ADC error is 2.5 mV + 1.25 mV 0.1875% error

25. © 2012 Renesas Electronics America Inc. All rights reserved.25 Understanding the Errors an Example Output Code Assume Vref = 2.56V, 10 Bit ADC (2.5 mV per step) Actual Voltage (mV) 0 1.2 5 2.5 5 7.5 10 00 01 02 03 Indicated Voltage (mV) 0 2.5 mV 5 mV 7.5 mV 04 10 mV 1.251 mV code 01 With 2 LSB error

26. © 2012 Renesas Electronics America Inc. All rights reserved.26 When is a 16 Bit ADC Not 16 Bit?

27. © 2012 Renesas Electronics America Inc. All rights reserved. 27 System Considerations

28. © 2012 Renesas Electronics America Inc. All rights reserved.28 Errors That Are Sometimes Forgotten System noise Clocks IO port toggles Sensor and reference error Accuracy vs. drift Temperature, age and voltage effects Calibration Input system effects

29. © 2012 Renesas Electronics America Inc. All rights reserved.29 Check Accuracy Conditions Specification may expect: MCU in a sleep mode No IO toggling Specified ADC clock speed

30. © 2012 Renesas Electronics America Inc. All rights reserved.30 What is the ADC Reading for the Circuit Below? 1.Depends on Vref 2.Depends on Vcc 3.Need to know resistor values 4.512 5.Ask the HW engineer 10 bit AD Input Vref Vcc +V R1 R2 R1=R2 +Vref MCU

31. © 2012 Renesas Electronics America Inc. All rights reserved.31 Ratiometric and Non-Ratiometric Conversions AD Input Vref Vcc +V AD Input Vref Vcc +V +Vref AD Input Vref Vcc +V +Vref a) ratiometricb) ratiometricd) non-ratiometric AD Input Vref Vcc +V c) non-ratiometric MCU

32. © 2012 Renesas Electronics America Inc. All rights reserved.32 AD Input Vref Vcc +V Vm RtMCU Rref Understanding Reference Errors T Zt Vref powers R2R ladder Treat as power supply pin – Typically <100 uA – Bypass properly 3 mV ripple = 1 LSB error on 10bit 3V ADC Vref is a power supply pin

33. © 2012 Renesas Electronics America Inc. All rights reserved.33 Understanding Ratiometric Reference Errors Vcc ≠ Vref Sensor biased from Vref Vref can pick up noise Bypassing ADC input can help AD Input Vref Vcc Rt MCU Rref T +V C1C2 C3 Loads

34. © 2012 Renesas Electronics America Inc. All rights reserved.34 Reference Errors – External References Consider design example Measure 0 – 2V with < 0.5% FS error 2.5V reference This measurement is non-ratiometric Assume 10 bit ADC with 1 LSB INL used Previously calculate 0.1875% error from ADC Can I use a 2.56V 0.5% accurate reference diode? AD In Vref Vcc MCU

35. © 2012 Renesas Electronics America Inc. All rights reserved.35 Reference Errors – Reference Accuracy Can use 0.5% accuracy diode? If no calibration – no If calibrate is performed? – Depends on drift and temp range LM4040 0.5% accuracy w/ 100 ppm/C 20 ppm typical If operating range is 0-50C max drift – 100 ppm/C * 25C =.25% drift – Total error still only 0.4375%

36. © 2012 Renesas Electronics America Inc. All rights reserved.36 Source Resistance Errors To AD Converter Block 10k Vref S1 Ceq Req RC time constant of source resistance and sampling cap can cause error For M16C/62P Req = 7.8k Ceq = 1.5 pF S1 closed for 3 fAD cycles ADC Input Ckt Equivalent Rs

37. © 2012 Renesas Electronics America Inc. All rights reserved.37 Source Resistance Limitation (An Intuitive Approach) Desired charge error much less than 1/1024 (0.1%) Allow 10 time constants (0.005%) Sampling occurs for 300 nSec (3 cycles of 10 MHz AD clock) 10 time constants = 300 nSec  1 TC = 30 nSec C = 1.5 pF so Rtotal (Rs + Req) must be 20Kohm or less (300 nSec/1.5 pF) Rsource can not be greater than 12.2 K ohms Equivalent resistance of the AD circuit is 7.8K (Strict analysis indicated 13.8 kOhm)

38. © 2012 Renesas Electronics America Inc. All rights reserved.38 Source Resistance Errors What can we do? Decrease Rs – Could add buffer – Buffer adds offset Increase sampling time Add capacitor To AD Converter Block 40k 30k Vref S1 Ceq Req For M16C/62P Req = 7.8k Ceq = 1.5 pF S1 closed for 3 fAD cycles C1 Rs

39. © 2012 Renesas Electronics America Inc. All rights reserved.39 Summary What does the “resolution” spec really mean Some standard converters and resolution DC accuracy specifications Review offset, gain, DNL and INL errors How the ADC is tested What those errors don’t tell you AC specifications SNR THD ENOB How does this affect my application Errors and considerations

40. © 2012 Renesas Electronics America Inc. All rights reserved.40 Questions? Questions?

41. © 2012 Renesas Electronics America Inc. All rights reserved.41 Collecting, analyzing and transmitting real-world signals is a major focus of the smart society. Real-world signals are analog, so converting these signals to digital is a key focus for the smart Understanding the specifications of an ADC and the effects of system device selections will help the information delivered by the smart society provide an accurate picture of the world ‘Enabling The Smart Society’

42. © 2012 Renesas Electronics America Inc. All rights reserved.42 Please utilize the ‘Guidebook’ application to leave feedback or Ask me for the paper feedback form for you to use… Please Provide Your Feedback…

43. Renesas Electronics America Inc. © 2012 Renesas Electronics America Inc. All rights reserved.

44. 44 Also Check the Conditions K10P100M100SF2 Data Sheet Rev 6

45. © 2012 Renesas Electronics America Inc. All rights reserved.45 Testing the DC Specifications Ramp or histogram testing – one common method Insert very slow ramp waveform Record number of each ADC output code – “Wide” bin – more codes – “Narrow or missing” bins – fewer or no codes ADC Signal Generator PC 0x0101

46. © 2012 Renesas Electronics America Inc. All rights reserved.46 Testing With Ramp (cont) Example 2 bit ADC with 4V reference Ramp rate 1V/sec Sample rate 5 hz - 5 samples per code state Ideal Transition Voltages 00 ADC Code 01 10 11 Samples by PC Ramp Voltage

47. © 2012 Renesas Electronics America Inc. All rights reserved.47 Testing With Ramp (cont) Transition voltages not ideal Transition Voltage 00 ADC Code 01 10 11 DNL >1 DNL < 1 DNL = 1

48. © 2012 Renesas Electronics America Inc. All rights reserved.48 ADC Testing Other methods exist Servo method ramps up and down small amount Slides ramp until codes split 50:50 Average voltage is a code transition Testing involves averaging Averaging masks noise

49. © 2012 Renesas Electronics America Inc. All rights reserved.49 49 Delta Sigma Converter

50. © 2012 Renesas Electronics America Inc. All rights reserved.50 50 Effect of Adding Capacitor to Input Pin Adding capacitor creates a low pass filter To AD Converter Block S1 Ceq Req Rs C1 Freq Gain fc fc = 1/2πRC 20k Rs and.0015 uF = 5.3 kHz corner

51. © 2012 Renesas Electronics America Inc. All rights reserved.51 Notes Below a certain frequency, THD is only dependent on the overall INL of the converter For an example, if the converter depicted in Figure 2 is being used to digitize a signal which can slew at an equivalent rate to that of a 10kHz signal, then the "THD" performance of the converter will be roughly -86dB. This figure means that the harmonic distortion is 86dB below the converter's full-scale range. Since the full-scale range of this 16-bit converter is ±32,768, then the harmonic distortion represents roughly ±1.6 LSB of error.