1. Useful Design Guide To Make the PLD

2. Xilinx FPGA Gate Count  Standardized on Logic Cell as unit of measure  Maximum capacity = number of logic cells  Usable capacity = logic cells x utilization  ASIC "gate" estimate = 8-12 gates / cell  Example: XC4062XL = 4992 logic cells = 62,000 gates o Result: Simplicity, easy Xilinx FPGA capacity comparisons 4-input LUTFF 4 8

3. First Order Size Estimate  Count I/Os required Select FPGA with next higher number of bonded IOBs  Count flip-flops required Select FPGA with next smaller number of CLBs Capability of using two flip-flops in one CLB, or flip-flops in IOBs, may balance with combinatorial CLBs XC4000 allows higher utilization than XC3000  Device may be determined by special resources Decoder width Busses Structured logic fitting in one column (especially carry)

4. Consider Architecture  Use dedicated logic functions  Limit clocks  Abundant flip-flops Also RAM  AND gate options (e.g., comparator) Lookup tables Edge decoders Wired-AND of three-state buffers Carry logic Writable RAM

5. CLB Lookup Table Functions of 4 inputs are best  Xilinx FPGAs are built from lookup tables  A lookup table can implement any function of its 4 inputs Similar to addressing ROM  Limit is on inputs, not complexity Reducing inputs/function (fan-in) to fit CLBs improves density and speed  Inverters are free

6. Why Use to Hierarchy  Adds structure to design  Eases debug  Users can build libraries of common functions  Allows each design portion to be entered by most efficient method  Improves incremental design  Allows for floorplanning  Provides for team design

7. Hierarchy Guidelines  No limit to number of levels Recommend placing all I/O pads on top level  Create macros for common functions Do not save user-defined macros in vendor-supplied library Future software updates may overwrite the library  Do not leave macro inputs floating Run logic simulation before place and route to check overall functionality

8. Locking I/O Pins  Avoid it until the last possible iteration Or until design is 75-80% complete & timing requirements met More flexibility on board than inside FPGA Then re-align I/Os in logical pattern with minimal movement  Specify edge locations only to guide layout If schematic is entered, let place & route choose I/O locations Useful for partial designs or incremental design

9. Use Legal and Readable Names  Allowable characters Alphanumerics A - Z, a - z, 0 - 9 Underline _ Dollar sign $ Dash - Angle brackets (reserved for buses) <> Slash / (reserved for hierarchy )  Names must contain at least one non-digit  Avoid using names that correspond to device resources CLB row/column locations in XC3000: AA, AB, etc. IOB pin locations: P1, P2, etc.

10. Synchronous Design  Be careful not to glitch a clock signal  Be careful not to glitch an asynchronous set or reset  The FF in fast FPGAs can respond to very narrow “glitch” pulses An easy rule to follow is “Never source a clock, asynchronous set or asynchronous reset signal from combinatorial logic”

11. Glitches  Delays through CLB are balanced for all inputs  Lookup table is a multiplexer built from transfer gates Logic inputs are select lines Non-overlapping decoder cannot glitch  If multiple inputs change, make sure possible intermediate codes do not cause problems  Synchronous designs are fundamentally immune to glitches except on clocks and reset direct nets 0-->1---1 1----1->0 0-->1-->0 CLR D Q

12. Avoid Gated Clock and Reset  Move gating to non-clock pin to prevent glitch from affecting logic  Or separate input signal changes by at least a CLB delay to minimize the likelihood of a glitch DQ Carry Q0 Q1 Q2 3-Bit Counter DQ Carry-1 Q0 Q1 Q2 3-Bit Counter CLB Delay

13. Use Clock Enables  Use clock enable when using most of or all logic inputs Not recommended to gate clock signal directly  Use muxed data to allow multiple clock enables in a CLB Required even for opposite edges of same signal  Some macros use logic for clock enable while others use the CE pin Make sure CE, if unused, is always connected to VCC DQ CE DQ FDxE

14. DQ R P INPUT CLOCK DQ R P DQ R P 12.13.63.33.63.13.0 This shift register will not work because of clock skew! Clock Skew  Use global buffers for clocks and there are no clock skew concerns (guaranteed to meet FF hold times)

15. Asynchronous Logic  Analyze carefully  Check for potential problems with faster parts  Try fastest speed grade available  Try low temperature and high VCC to speed up chip If failure is at hi temp and/or lo VCC, improve delays If failure is at lo temp and/or hi VCC, check for asynchronous logic and clock skew issues

16. Safely Synchronising Design for Asynchronous Inputs DQ R Async input System clock Sync input Device periphery DQ DQ Ensures no metastability DQ

17. t CO t NET t PD t NET t PD t NET t SU CLB Performance Estimation  Use block delays as estimate of net delays  Use desired clock frequency to determine allowed CLB depth Compare to functional requirements and modify design to meet performance needs  Example for 50 MHz clock frequency in XC4000XL-3: Clock period20 ns One level- 8 ns (tCO + tNET + tSU) Delay allowance12 ns Each added level div 6 ns (tPD + tNET) Added levels of logic allowed2 CLBs

18. Pipeline Logic  Registers are “FREE” in FPGAs  Increases system through put D CE Q R P D Q R P D Q R P D Q R P 25MHz 50MHz D CE Q R P

19. State Machines Three Types  Binary: The States have a counter like progression S1 = 001, S2=010, S3=011, S4=100, etc…  Enumerated: The States have assigned values S1=100, S2=110, S3=101, S4 = 111, etc…  One Hot: Only 1 register is active for each state S1=00000001, S2=00000010, S3=00000100, etc…  Binary and Enumerated have lots of feedback to make the present state to next state jump. This is good for CPLDs like the XC9500.

20. State Machines  Use One Hot Encoding for larger machines  Binary or Enumerated Encoding okay for smaller state machines  Remember the 4 input LUT! State Machines can have wide fan-in and lots of feed back  For One Hot limit number of input states to 4 for highest speed. Input 1 Input 3 State 4 State 6 State 19 1 LUT

21. State A State A1 State A2 State B cond1 State B cond1 State Machine Design Tips  Split complex states  Need to minimize number of inputs, not number of flip- flops, in FPGAs  Complex states may be improved by breaking up into additional simpler states

22. DQ fn1 DQ DQ Duplicate Registers  High fanout nets (>16 loads) are hard to route and slow  Consider duplicating source in schematic/HDL to improve routing or speed  The M1 tools don’t do this automatically  Name duplicate registers _a, _b, _c, NOT 1,2,3. M1 Mapping will be more effective.

23. O1 I1 O1 I1 N1 N1 must go to two places, so O1 may require a second level of logic Duplicating first gate allows N1A to always be collapsed inside a single lookup table N1A N1B Duplicate Combinatorial Logic  The M1 tools will duplicate combinatorial logic automatically if Logic Replication is selected  Collapsing logic into CLBs lowers the number of levels  The gates you use will determine mapping Nets with a fanout >1 may be outside a CLB Pay attention to mapping of speed-critical paths

24. LAYOUT: Pin Selection I Data Flow

25. LAYOUT: Pin Selection II Control Pins

26. LAYOUT: Pin Selection III Remember the Carry Chain Flow Direction if your design uses arithmetic functions For EX/XL/XVSpartan LSB I/O  MSB I/O   MSB or LSB I/O  LSB or MSB I/O

27. LAYOUT: Pin Selection IV  Stay off the FPGA Control Pins DOUT, M0, M1, M2, JTAG  Wire-and DONE signals to determine when all FPGAs are finished programming.  Don’t join the INIT signal for all FPGAs in the same Daisy Chain Monitor INIT for each FPGA for CRC check failure

28. LAYOUT: CCLK  CCLK is the download clock.  Many boards contain two or more FPGAs in a daisy chain configuration. The Cclk is taken from one FPGA to the other.  CCLK has a very fast slew rate driver and that is can cause a lot of reflections on the clock line.  Inside the FPGA the CCLK is first routed to the CCLK pin and then taken back inside to the configuration circuit. Treat the Cclk line as a transmission line. Terminate it properly.  Ideas : active termination via two Shottky diodes, or a slow slew rate driver mounted immediately after the first device.

29. Use Tick marks To help with pin identification on your board LAYOUT: Debug Tips

30. XC4K FPGA XC17XX PROM VCC GND CCLK DIN PROG DONE INIT RD RT M0 M1 M2 VCC LAYOUT: Debug Tips  Use the Xilinx Download Cable for debug  Use the FPGA Readback, RD & RT

31. CPLD  <5K gates  Simple tools  Low cost (SW + IC)  Equations  Schematics  Tpd, ISP High Volume FPGAs  Higher integration  5K–20K gates  3rd party tools  Equations  Schematics  Verilog/VHDL High End FPGAs  >20K gates  ASIC-like flow  System level tools  Verilog/VHDL  Schematics Xilinx Product Strategy Serve the ASIC Designer Serve the PAL Designer PAL ASIC XC9500 XC4000E XC5200 XC4000EX/XL/XV Integrated Software Migration

33. FPGA Technology Roadmap 1995199719981999 Year XC4000E Largest Device XC4025 45,000 sys. gates 0.5  m 5 Volt XC4000EX Largest Device XC4036EX 65,000 sys. gates 0.5  m 5 Volt 30% faster than E XC4000XL Largest Device 180,000 sys. gates XC4085XL 0.35  m 3.3 Volt 30% faster than EX XC4000XV Largest Device 500,000 sys. gates XC40250XV 0.25  m 2.5 Volt 30% Faster than XL 1996 Virtex 1 Million+ sys. gates System Solution 0.25/0.18  2.5/1.8 Volt Density/Peformance 2.0M gates in the year 2001 2.0M gates in the year 2001

34. 4000 Series X = EX/XL/XV  How to keep naming straight  Markets the X architecture  e X tra routinge X tra density  e X tra performance EX XL XV 5 Volts 3.3 Volts 2.5 Volts X Architecture

35. XC4000X Family Features Select-RAM ( Synchronous Single and Dual-Port RAM) Pin Locking Flexibility with VersaRing 100% PCI Compliance LogiCore Modules (PCI, DSP and USB) Strong Footprint compatibility High density, up to 125,000 Gate (250,000 System Gate) Internal Three-state Buffers JTAG Boundary Scan System performance to 100 MHz (-0.9) – 1/ (T setup + Tclk-out)

36. XC4000X Series High Density XC4000EX XC4000XL XC4000XV Family Family Family Logic Cells 2,432 - 3,078 152 - 7,448 10,982 - 20060 Max Logic Gates 28,000 - 36,000 2,000 - 85,000 125,000 - 250,000 Typ Gate Range 50,000 - 65,000 5,000 - 180,000 250,000 - 500,000 (Logic + Select-RAM) I/O 256 - 288 112 - 448 288 - 544 Number of Devices 2 11 5 Power Supply 5 V 3.3 V 3.3 V + 2.5 V I/O Interface 5 V 5 V / 3.3 V 5 V / 3.3 V

37. Xilinx FPGA Comparison XC5200XC4000EXC4000XSPARTAN Function Generators/CLB4333 Flip-flops/CLB4222 Global Nets48208 Extended Routing No No Yes No Global Three-State ControlYesYesYesYes Wide Decode CapabilityCascadeDedicatedYesNo Carry LogicYesYesYesYes On-Chip MemoryNoYesYesYes Wired-AND Function No Yes Yes No Internal Three-State BuffersYesYesYesYes Output Slew Rate ControlYesYesYesYes Boundary Scan LogicYesYesYesYes Output Drive (Sink)8 mA12 mA12 mA12 mA Power-Down OptionNoNoNoNo

38. 4002XL 4005XL 4010XL 4013XL 4020XL 4028XL 4036XL 4044XL 4052XL 4062XL 4085XL 40125XV PC84 PC84 PC84 PQ100 PQ100 PQ100 VQ100 TQ144 TQ144 HT144 HT144 PQ160 PQ160 PQ160 PQ160 HQ160 HQ160 HQ160 TQ176 TQ176 HT176 HT176 PQ208 PQ208 PQ208 PQ208 HQ208 HQ208 HQ208 PQ240 PQ240 HQ240 HQ240 HQ240 HQ240 HQ240 HQ304 HQ304 HQ304 HQ304 HQ304 BG256 BG256 BG256 BG256 BG352 BG352 BG352 BG432 BG432 BG432 BG432 PG411 PG411 PG411 BG560 BG560 BG560 PG559 PG559 XC4000XL Footprint and Packaging Future extensions

39. Density: The Facts

41. XC4000 Series FPGA Architecture

42. XC4000X Interconnect Hierarchy  Abundant high-speed, segmented interconnect  Optimized resources for high-density designs  Delivers fast compilation times and ensures high first-pass completion rates Routing Resource XC4000EX XC4000E V/H Quad Line 12/120/0 V/H Long Line 10/66/6 V/H Direct Connects 2/20/0 V/H Single Line 8/68/6 V/H Double Line 4/44/4 Vertical Global Lines 8 4

43. XC4000EX Clocking Options Global Low-Skew Buffers FastCLK Buffers Global Early Buffers Ideal for “system clocks” or critical control signals High speed clock for localized macros or cells Optimized for high-speed I/O 6ns setup 6ns pin to pin 6ns clock to out

44. XC4000X VersaRing TM

45. 0.35  FPGA, 5 Volt Compatible  accepts 5 volt inputs  drives standard TTL levels  totally compatible in 5 volt environment Any 5 V device XC4000XL FPGA 0.35  3.3V Core 3.3V I/O 5V5V 3.3v 5V5V 3.3V Meets TTL Levels

46.  30% faster than 0.5   70% power reduction over 0.5  at same speed and density  3.3 volt power supply, I/Os 5 volt compatible XC4000XL Density (Logic Cells) XC4000E XC4000EX Price ($) 7,500 Price reduction from 5 volt devices 400 XC4085XL High Performance 0.35u FPGAs 3.3 volts in 1997 5,000 85,000 Density (Gates)

47. XC4000XL Delivers High Performance at 3.3 V  80 MHz internal speed (3-4 LUT levels)  66 MHz internal speed (4-5 LUT levels)  I/O performance XC4013XL XC4036XL Tco (output register) 6.4 ns 6.4 ns Tsu (input register) 4.5 ns 5.4 ns Th (input register) 0 ns 0 ns Max I/O frequency92 MHz 85 MHz

48. Gate Array Densities FPGA Capability FPGAs Overlap Gate Array Design Starts Source: Dataquest 1996 Design Starts Asic Line Widths FPGA Performance Level

49. XC4000XL Performance Overlaps with Gate Arrays * Design Dependent, source:Major GA supplier Gate Array performance advantage shrinking annually XC4000XL Equivalent XC4000XL-2 XC4000XL-1 XC4000XL-09

50. * 25-30% of CLBs as RAM * 20-25% of CLBs as RAM 4002XL4005XL4010XL4013XL4020XL4028XL 4036XL Logic Cells1524669501,3681,8622,432 3,078 Typ Gate Range*2-5K3 - 9K7-20K10-30K13-40K18-50K 22-65K (Logic + Select-RAM) Max. RAM bits2K6K13K18K25K33K 42K I/O64112160192224256 288 Initial PackagesPQ160PQ160PQ160PQ160PQ160 PQ160 TQ176TQ176HT176HT176 PQ208PQ208PQ208HQ208HQ208 HQ208 HQ240HQ240HQ240 HQ240 BG256BG256BG256 BG256 BG352 BG432 4044XL4052XL4062XL4085XL Logic Cells 3,8004,5985,4727,448 Typ Gate Range* 27-80K33-100K40-130K55-180K (Logic + Select-RAM) Max. RAM bits 51K62K74K100K (no Logic) I/O320352384448 HQ160 HQ208 Initial packages HQ240HQ240HQ240 BG352 BG432BG432BG432 BG560BG560BG560 XC4000XL Family

51. XC4000XL Success Story  Big Datacom company  ATM Switch Application  Division was 100% Altera for PLDs  Board with 10K50 failed to meet 25MHZ after one month of effort (including Altera Engineers). XC4028XL-1 ran at 30MHZ with no problem.  This socket allowed us to win ALL FPGAs on the board. New ATM platform is 95% Xilinx.

52. XC4000XL Success Story  Subsidiary of major networking company  Design included 12x14 multiplier and high- speed pipelined RAM, target speed 100MHZ  Began with Altera 10K100 - Simulation said design would work at 74MHz  Altera part began “melting the printed circuit board” at 60MHz  XC4000XL-1 works at 91MHZ - will hit 100MHZ target with -09 speed

53. World’s... First 0.25 micron FPGA, First 250,000+ Gate FPGA, First 2.5 Volt FPGA, First 25 million transistor logic device

54. Technology Leadership: XC4000XV Family  Advanced process technology 5 layer metal 0.25u CMOS stacked vias CMP (chemical mechanical polishing)  XC4000XV+ includes extra routing 100XV, 150XV, 200XV, 250XV eight tracks of octal lines added per CLB minimizes routing congestion

55. World’s Most Advanced Logic Devices Transistor count (millions) 7.5 25 50  4Q971Q982Q98 Intel Pentium II XC40125XV XC40150XV XC40200XV XC40250XV XC40100XV

56. Xilinx FPGA Density Leadership XC4000XV Production Roadmap Jan ‘98 Q2 ‘98 Q1 ‘98 Q3 ‘98 NOW Q1 ‘98 Altera

57. 0.25  FPGA, 5 Volt Compatible  accepts 5 volt inputs  drives standard TTL levels  totally compatible in 5 volt environment  Separate I/O & Core Supplies Any 5V device XC4000XV FPGA 0.25  2.5V Core 3.3V I/O Any 3.3V device 5V5V 3.3V 2.5V 5V5V 3.3V I/O Supply Core Supply Meets TTL Levels

58.  30% faster than 0.35   70% power reduction over 0.35  at same speed and density  2.5 volt power supply, I/Os 5 volt compatible High Performance 0.25  FPGAs 1997/1998 XC4000XV Logic Cells Price ($) 32,000 11,000 XC40125XV Generation 3 Architecture Up to 400k logic gates 400K 125K Gates

59. The XC4000XV - 0.25 µm Fast  Performance summary XC40125XV Internal operation (3-4 LUT levels)100 MHz Tco (output register)7.5 ns Tsu (input register)5.0 ns Max I/O frequency80 MHz  XC40125XV: 10,982 logic cells (265,000 system gates) Combining VERY high density AND VERY high performance

60. 4KXV Addresses 90% ASIC Starts by Speed Source: Dataquest and Xilinx 1997 0% 5% 10% 15% 20% 25% 30% 0-2040-6080-100120-140160-180 Average Clock Speed (MHz) % of 1997 Gate Array Starts Adressed by FPGAs

61. Xilinx: The Density Leader Logic cells 40% bigger ]

62. XC4000XV Family

63. Foundation FPGA Express

64. Foundation Express Features  Express Technology Optimizes the design for Xilinx Architectures Optimized arithmetic functions Automatic Global Signal Mapping Automatic I/O Pad Mapping Resource Sharing Hierarchy Control Source Code Compatible With Synopsys Design Compiler and FPGA Compiler Verilog (IEEE 1364) and VHDL (IEEE 1076-1987) Support Easy, graphical constraint entry

65. Xilinx-Express Design Flow.VEI.VHI.UCF Reports DSP COREGen & LogiBLOX Module Generator XNF.NGO HDL Editor State Diagram Editor VHDL Verilog.V.VHD Foundation Design Entry Tools Gate Level Simulator Schematic Capture EDIF XNF Timing Requirements VHDL Verilog Express EDIF/XNF.XNF BIT JDEC SDF VHDL Verilog Reports EDIF Xilinx Implementation Tools HDLSIMULATIONHDLSIMULATION VHDL Verilog Behavioral Simulation Models

66. Express Input and Output  Input files may be VHDL or Verilog format Mixed Verilog/VHDL modules are accepted Schematics may also be used, but should not be input into Express Schematic files in XNF or EDIF format will be merged into the design in Xilinx Design Manager  Output netlists are in XNF format  Timing Specifications may be specified in Express Timing Specifications are not used during Synthesis Timing Specifications can be included in the output netlist Reports Timing Requirements VHDL Verilog Express.XNF

67. Express Design Process (1) 2. Implement - Create generic logic design (Elaborate) 1. Analyze - Syntax check 2. Enter constraints and options Foundation Express Layout with Xilinx Design Manager 5. Evaluate Results 4. Synthesize - Optimize the design for specific device

68. Create a Project  Invoke Express with Start -> Programs -> Xilinx Foundation Series -> Foundation Express The Main Window Appears

69. Analyze the Design (1)  “Analyze” checks the HDL code for syntax errors Also creates internal files  Files are automatically analyzed when selected for a project  Do not select XNF or EDIF files Will be merged into the design by Design Manager Synthesis -> Identify Sources

70. Analyze the Design (2)  As the design blocks are analyzed, status is displayed: No Errors or Warnings Out of Date Warnings Errors In this example, all blocks were analyzed successfully Main Window

71. Implement the Design  Express Implementation maps the HDL code to standard logic, creating a generic netlist.  At this stage, the design has not been optimized To implement a design, select only the top level block, and then select the Implement icon Main Window

72. Check for Errors and Warnings  After implementation is complete, the chip symbol plus status is displayed  View errors, warnings and messages  Right click inside window to save information to a text file

73. Define Clock Period  Enter Period, Rise, and Fall Time Select Clock entry -> Define Synthesis -> Edit Constraints -> Clocks -> Define Synthesis -> Edit Constraints -> Clocks

74. Define Global Synchronous Delays (1)  The clock period creates 3 types of global constraints:  All input ports to sequential Elements (1) Setup of flip-flop or latch is included  Sequential Element to all output ports (2) Flip-Flop Clock to Q delay is included  Sequential Element to Sequential Element (3)  All constraints have the same value by default 3 Clock period logic DQ 1 DQ 2

75. Define Global Synchronous Delays (2)  Use the Paths form to edit delays assigned by the clock period Default delays from the clock period are shown here Synthesis -> Edit Constraints -> Paths form 3 Clock period logic DQ 1 DQ 2

76. Define Individual Synchronous Delays  Default delay from Clock specification is used in the Paths form  Individual, or path specific delays can be defined on the Ports form Port delays over-write the global delays from the Paths form  Input delay, shown here, arrives 20 ns before the rising edge of the clock. Synthesis -> Edit Constraints -> Ports

77. Define Key Port Features (1)  Global Buffer defines the type of Clock Distribution network - Use BUFG for most applications(default)  Resistance specifies use of pullup or pulldown resistor on unused pads Reduces power consumption and noise  Use IO Reg allows use of sequential elements within IO Blocks to minimize Input or Output delay (default) Dependent on device type Synthesis -> Edit Constraints -> Ports

78. Define Key Port Features (2)  Slew Rate can be fast or slow Fast slew rate can cut IO delay up to 50%, but causes more noise Default is slow  Pad Location is used to specify pin number of the IO pad Synthesis -> Edit Constraints -> Ports

79. Control the Hierarchy (1)  Eliminate (default) or save hierarchical boundaries  Flat designs yield best results because more merging and sharing of boolean logic occurs  However, small blocks are easier to debug Easier to match source HDL code to synthesized design  Synthesis goals (Speed or Area) and Effort level can be defined for each module Synthesis -> Edit Constraints -> Modules (implemented design)

80. Control the Hierarchy (2)  Hierarchical blocks may be eliminated or saved  By default, hierarchical boundaries are eliminated  Flat designs yield best results because more merging and sharing of boolean logic occurs  Synthesis goals (speed or Area) and Effort level are defined for each module Synthesis -> Edit Constraints -> Modules (implemented design)

81. Optimize the Design  Optimization minimizes the design for speed or area  Select the implementation, and then select the Optimize icon  After Optimization, check for errors and warnings again Main Window

82. View Results  Select File -> Project Report to generate a report Report file contains : – Files and libraries used – Settings for Synthesis – Chip type and speed grade – Estimated Timing – Warning: Circuit timing estimates tend to be optimistic. Run timing analysis after routing for most accurate timing analysis. Report.txt file

83. Verify Results (1)  After Optimization, open Synthesis -> Edit Constraints to verify that correct constraints were specified  Results are based on estimated routing delays Synthesis -> Edit Constraints -> Paths (for an optimized design)

84. Verify Results (2)  Review size of the design  Resource use is displayed for each hierarchical block Resources used per hierarchical block Black Box instantiations cannot be analyzed by Express Synthesis -> Edit Constraints -> Modules (Optimized Design)

85. Verify Results (3)  View Details for each block Left click within Area slot --> Arrow -> Details  Type and number of each Xilinx component are used. BUFG - Primary or Secondary Buffer BUFGS - Secondary Buffer CY4* - Carry Logic Function DFF - CLB flip-flop FMAP, HMAP - F and H LUTS IBUF - IOB input buffer INFF - IOB flip-flop OBUF - IOB output buffer OSC4 - Internal Oscillator Synthesis -> Edit Constraints -> Modules

86. Export Netlist  Create the output netlist for use with the Xilinx Design Manager (Xilinx Implementation Tools) Output File format is XNF  Select the optimized design, then select Synthesis -> Export Netlist to create the file XNF file format is used Enable Export Timing Specifications to include constraints in the output netlist Synthesis -> Export Netlist