1. SystemVerilog basics
Jean-Michel Chabloz

2. How we study SystemVerilog
Huge language:
last LRM has >1300 pages
Not possible to cover everything, we cover maybe 5% of the constructs
You can succeed in the course using only the subset of the language that is treated in these slides
If you want you are free to use other constructs, research them by yourself

3. SystemVerilog Hello World
module M();
initial
$display(“Hello world”);
endmodule

4. SystemVerilog simple program
module M();
logic a,b;
logic [7:0] c;
assign b = ~a;
initial begin
a <= 0;
#20ns;
repeat(40)
#5ns a <= ~a;
#20ns $display(c);
$finish();
end
initial
c <= 0; a)
c <= c + 1;
endmodule

5. SystemVerilog syntax Case sensitive
C-style comments: // or /*comment*/
Similar to C, but code blocks are delimited by “begin” “end”. If a single-line, can be omitted

6. Modules
Let’s start to consider systems without hierarchy (no submodules)
A module contains objects declarations and concurrent processes that operate in parallel.
Initial blocks
Always blocks
Continuous assignments
(instantiations of submodules)

7. SystemVerilog basic data types
logic – 4 valued data type:
0, 1, X, Z
initialized to X
can also be called reg // deprecated verilog legacy name
bit – 2 valued data type:
0, 1
initialized to 0
Defining an object of a certain type:
bit a;
logic b;
bit c, d;

8. Packed arrays of logic and bits
bit [5:0] a;
logic [2:0] b;
logic [0:2047] [7:0] c; //array of 2048 bytes
integer: equivalent to logic [31:0]
int, byte: equivalents to bit [31:0] and bit [7:0]
Signed/unsigned affects operations such as “>”
arrays of logics default to unsigned, can be overriden with the keyword signed
ex: logic signed [7:0] a;
arrays of bits default to signed, can be overriden with the keyword unsigned
ex: bit unsigned [7:0] a;

9. Literals Decimal literal: Unspecified length: binary literal
a <= 54; // automatically extended to the length of a with 0 padding
a <= ‘d54;
a <= 12’d54; // specifies that a is 12-bits wide
Unspecified length:
‘1, ‘0, ‘x, ‘z // fills with all 1s, 0s, xs, zs
binary literal
12’b1000_1100_1110 // underscores can be put anywhere except the beginning of a literal
‘b11011 // automatically resized with zeroes if fed to something bigger
hexadecimal literal:
12’hc; // “ ”
‘hcd: // ”… ”

10. Packed array access Single element access:
bit [7:0] a
a[5] <= a[6];
bit [9:0][7:0] b:
b[5] <= 15;
Packed arrays can be sliced:
bit [7:0] a;
a[3:2] <= 2’b10;
a[3:0] <= a[7:4];
bit [2047:0][7:0] a; bit [1:0][7:0] b;
a[2047:2046] <= b

11. packed structures
equivalent to a packed array subdivided into named fields:
example: 48 bit packed array
can be accessed as pack1[15:0] <= ‘b0;
can access pack1[9:4] <= 15;
can be accessed as pack1.d <= ‘b0;
the whole struct can be resetted with pack1 <= ‘b0;
unpacked struct (no “packed” keyword) allow only acces through the named fields (pack1.d <=‘b0);
struct packed {
int a;
bit [7:0] c;
bit [7:0] d;
} pack1;

12. Other data types Enumerated data type:
enum bit [1:0] {idle, writing, reading} state
If skipping the type an int type is assumed
Can be typedeffed (like all other data types):
typedef enum {red, green, blue, yellow, white, black} Colors;
Colors [2:0] setOfColors; // array of 3 elements of type colors

13. Types in SV SystemVerilog is a weakly-typed language
advantages: simpler and shorter code
disadvantages: easy to do mistakes
Many assignment-compatible types
a bit and a logic are assignment-compatible, we can assign one to the other
a longer array can be assigned to a shorter one or viceversa (truncation or extension will happen automatically)
arrays can be indexed by logic arrays, bit arrays
a packed struct has the same properties as an array
struct packed {bit[3:0] a, b;} can be assigned a bit array, a logic array, etc.
ifs, whiles, etc. can take as condition bits, logic, arrays, etc.
non-zero values count as TRUE, all-zero values count as false
if a is a bit or logic, then we can write if (a==1) or if (a), they do the same thing

14. Processes
Modules contain processes (initial, always) – code inside processes is called “procedural code”
Initial: executed only once, at the beginning of the simulation
initial begin
#10ns;
a <= 1’b1;
#20ns;
a <= 1’b0;
end

15. Processes
Always with no sensitivity list: triggers as soon as it finishes executing
always begin
#10ns;
a <= 1’b1;
#20ns;
a <= 1’b0;
end

16. Processes
Always with sensitivity list: triggers when it has finished executing and one of the events in the sensitivity list happens
b, negedge c) begin
#10ns;
a <= 1’b1;
#20ns;
a <= 1’b0;
end
posedge: positive edge
negedge: negative edge
signal name: any toggle

17. Always block, combinational process
To make combinational processes, the sensitivity list must contain all elements in the right-hand side of statements (also in conditions, loop headers, …) – in general, anything that influences the output
begin
c <= a+b;
end
SystemVerilog allows using always_comb instead
the sensitivity list is automatically compiled to make a combinational block
always_comb begin
the compiler also checks for latches, as in the following example
always_comb begin // latch will be detected
if (c)
d <= a+b;

18. Always block, flip-flop
D flip-flop with async reset:
Possible to specify always_ff to declare intent
we declare to the compiler we want to do a FF (in the sense of edge-triggered logic, can also be an FSM), if it is not an FF we get an error
clk, negedge rst) begin
if (rst==0)
q <= 0;
else // posedge clk, rst==1
q <= d;
end
clk, negedge rst) begin
if (rst==0)
q <= 0;
else // posedge clk, rst==1
q <= d;
end

19. Procedural code if (a==1) begin //code end
if (a) begin // 1 counts as true
//code
end
while (a==1) begin
//code
end
repeat (3) begin
//code
end
forever begin // loops forever
//code
end
for (i=0; i<3; i++) begin // loops three times
//code
end

20. if trees
if (condition) begin …
end
else begin

21. if trees No elsif construct, but this is equivalent
if (condition1) begin …
end
else if (condition2) begin
else if (condition3) begin
else begin
No elsif construct, but this is equivalent

22. Bitwise logic operators
Bitwise logic operators – return a number of bits equal to the length of the inputs:
&: and
| : or
^ : xor
~ : not
Negate one bit/logic array:
a <= ~a
Do a bit-wise OR between two bit/logic arrays:
c <= a | b

23. logic operators
logic operators – return one bit only, treat as one everything that is non-zero:
&&: and
| |: or
! : not
for one-bit elements “if (!a)” is equal to “if (~a)”
for a 4-bit elements, if a=1100
if(!a) will not execute (!a returns 0)
if(~a) will execute (~a returns 0011 which is not all-zeros)

24. comparisons equality: == diseguality: != greather than: >
lower than: <
greater or equal than: >=
lower or equal than: <=

25. arithmetic
+ and – can be used with logic arrays, bit arrays, automatically wrap around:
up counter:
……….
11101
11110
11111
00000
00001
00010

26. Timing Control in Processes
#10ns: waits for 10 ns
#10: wait for 10 time units – time unit specified during elaboration or with a `timescale directive in the code
#(a): wait for a number of time units equal to the value of variable a
#(a*1ps): wait for a number of picoseconds equal to the value of a
@(posedge a): waits for the positive edge of a
@(b): wait until b toggles
wait(expr): waits until expr is true
wait(b): wait until b is one
Timing checks can be bundled with the next instr: #10ns a<=!a

27. fork… join
Spawn concurrent processes from a single process: A is printed at 30ns; B at 20ns; join waits until both subprocesses have finished, “both finished” is displayed at 40ns
initial begin
#10ns;
fork
begin
#20ns;
$display( “A\n" );
end
$display( “B\n" );
join
$display(“both finished”);

28. fork… join_any
Spawn concurrent processes from a single process: A is printed at 30ns; B at 20ns; join_any waits until any subprocess has finished, “at least one finished” is displayed at 30ns
initial begin
#10ns;
fork
begin
#20ns;
$display( “A\n" );
end
$display( “B\n" );
join_any
$display(“at least one finished”);

29. fork… join_none
Spawn concurrent processes from a single process: A is printed at 30ns; B at 20ns; join_none executes as soon as the fork is encountered, “fork entered” is displayed at 10ns.
initial begin
#10ns;
fork
begin
#20ns;
$display( “A\n" );
end
$display( “B\n" );
join_none
$display(“fork entered”);
The number of forked processes (begin...end blocks) in any fork can be any (minimum one).
Note 1: having one forked process only makes sense with join_none
Note 2: if processes have a single line, no begin...end is necessary

30. Procedural assignments
Non-blocking assignment
“<=“
Write-back takes place after a delta delay
Blocking assignment
“=“
takes place immediately
The two can be mixed – but probably not a good idea

31. Procedural assignments
blocking assignments behaves like the VHDL variable assignment “:=“
non-blocking assignments behaves like the VHDL signal assignment “<=“
BUT:
In VHDL := is reserved for variables, <= for signals
In Verilog, both can be used for variables
Possible to mix them - but probably not a good idea
A better idea is to use some objects as VHDL variables and only assign them with “=“, others as VHDL signals and only assign them with “<=“

32. Procedural assignments
clk) begin
a <= b;
b <= a;
end
clk) begin
a = b;
b = a;
end

33. Procedural assignments
clk) begin
a <= b;
b <= a;
end
Swaps A and B
clk) begin
a = b;
b = a;
end
copies B to A
(B is unchanged)

34. Procedural assignments
initial begin
a = 1;
$display(a);
end
initial begin
a <= 1;
$display(a);
end
initial begin
a <= 1;
#10ns;
$display(a);
end

35. Procedural assignments
initial begin
a = 1;
$display(a);
end
1 is displayed
initial begin
a <= 1;
$display(a);
end
The old value of A is displayed
initial begin
a <= 1;
#10ns;
$display(a);
end
1 is displayed

36. Default assignments
default values to avoid latches and to avoid writing long if else trees
works like in VHDL (the last write is kept)
always_comb begin
a <= 0; // default value of a …
if (c)
if (b==100)
a <= 1;
end

37. Console/control commands
introduced with the $ keyword
$display – used to display information to the console
ex:
$display(“hello”); // displays “hello”
$display(a); // displays the value of a, depending on its data type
$stop(), $finish(): stop (break) and finish (terminate) the simulation

38. Direct generation of random numbers
$urandom returns a 32-bit random unsigned number every time it is called
Can be automatically assigned to shorter values, automatic clipping will take place:
bit a; a <= $urandom;
To generate a random number between 0 and 59 we can use: $urandom%60 (modulus)
Note: if not seeded, every time the testbench is run we get the same values
this behavior is required for being able to repeat tests

39. Direct generation of random numbers
$urandom_range(10,0) returns a random number between 10 and 0
Note: if not seeded, every time the testbench is run we get the same values
this behavior is required for being able to repeat tests
Seed can be given during elaboration

40. Event-driven simulation
The simulator executes in a random order any of the operations scheduled for a given timestep.
It continues until the event queue for the timestep is empty, then advances time to the next non-empty timestamp
This might create race conditions:
What happens is not defined by the rules of SystemVerilog
No error is signaled
The behavior of the system might be simulator-dependent or even change from run to run

41. Race condition initial begin #10ns; a = 1; end #10 ns; a = 0; #20 ns;
$display(a);

42. Race condition initial begin #10ns; a = 1; end
$display(a);
Value displayed is random, because two assignments to A with different values take place in different processes at timestep 10ns

43. Race condition initial begin #10ns; a <= 1; end #10 ns; a <= 0;
$display(a);

44. Race condition initial begin #10ns; a <= 1; end
$display(a);
Value displayed is random, because two assignments to A with different values take place in different processes at timestep 10ns+delta

45. Race condition initial begin #10ns; a <= 1; end #10 ns; a = 0;
$display(a);

46. Race condition initial begin #10ns; a <= 1; end
$display(a);
Value displayed is 1, because A is assigned 0 at timestep 10ns and 1 at timestep 10ns+delta

47. Race condition initial begin #10ns; a = 1; a = 0; end #20 ns;
$display(a);

48. Race condition initial begin #10ns; a = 1; a = 0; end
$display(a);
Value displayed is 0, because, although there are two assignments to A with different values taking place at timestep 10ns, the assignments are in the same process and are therefore executed in order

49. Race condition initial begin #10ns; a <= 1; a <= 0; end #20 ns;
$display(a);

50. Race condition initial begin #10ns; a <= 1; a <= 0; end
$display(a);
Value displayed is 0, because, although there are two assignments to A with different values taking place at timestep 10ns+delta, the assignments are in the same process and are therefore executed in order

51. Race conditions
Happen when two different processes try to write the same signal during the same time step
Ways to avoid:
don’t write the same signal in different processes, unless you really know what you do (you know that the two processes will never write the signal in the same time step)

52. Continuous assignments
continuously performs an assignment
outside procedural code
ex: assign a = b+c;
Note: module input/output ports “count” as continuous assignments
can be done on variables or nets
nets can be driven by multiple continuous assignments, variables no

53. Variables vs Nets Variables: Are defined as: var type name
Example: var logic a (logic is default, can be omitted)
The keyword “var” is the default, it can be omitted
So when we define something like
logic a;
bit [7:0] b;
we are actually defining variables

54. Variables vs Nets Variables can be assigned:
in a procedural assignment (blocking or non-blocking assignment inside an initial or always process)
By a single continuous assignment

55. How variables work
initial
#10ns a <= 1;
#20ns a <= 0;
a variable keeps the newest value that is written to it. Variable A will have value 1 between time 10 and 20, then will have value 0.
VARIABLES HAVE NOTHING TO DO WITH VHDL VARIABLES

56. Variables vs Nets Nets:
Different types: wire, wand, wor, etc. We consider only wire
Are defined as: wire type name
Examples: wire logic a, wire logic [2:0] c
logic is the default and can be omitted
A wire cannot be a 2-valued data type (like bit)
A net can be assigned only by one or more continuous assignments, cannot be assigned into procedural code

57. Variables vs Nets
So there is only one thing in SV that nets can do and that variables cannot: be driven by multiple continuous assignments
Nets should be used when modeling tri-state buffers and buses
The value is determined by a resolution function 1 X Z

58. Objects scope objects declared inside modules/programs:
local to that module/program
objects declared inside blocks (ifs, loops, etc.) between a begin and an end:
local to that block of code

59. Subroutines Functions: return a value, cannot consume time
Tasks: no return, can consume time

60. Functions
input/ouput/inout ports (inouts are read at the beginning and written at the end)
the keyword input is the default, no need to specify it.
cannot consume time
a function can return void (no return value)
It is allowed to have non-blocking assignments, writes to clocking drivers and other constructs that schedule assignments for the future but don’t delay the function execution
function logic myfunc3(input int a, output int b, c);
b = a + 1;
c <= a + 2; // this schedules a write-back to C for a
// delta delay later, but does not consume time
// (the function returns in the same timestep it
// was called)
return (a==1000);
endfunction

61. Tasks Tasks can consume time, they do not return values
task light (output color, input [31:0] tics);
repeat (tics)
@ (posedge clock);
color = off; // turn light off.
endtask: light
Tasks can consume time, they do not return values

62. Packages type definitions, functions, etc. can be defined in packages
package ComplexPkg;
typedef struct {
shortreal i, r;
} Complex;
function Complex add(Complex a, b);
add.r = a.r + b.r;
add.i = a.i + b.i;
endfunction
function Complex mul(Complex a, b);
mul.r = (a.r * b.r) - (a.i * b.i);
mul.i = (a.r * b.i) + (a.i * b.r);
endpackage

63. Packages Stuff that is in package can be called as: or
c <= PackageName::FunctionName(a,b) or
the package can be imported, then we can just write:
c <= FunctionName(a,b);
Importing a package is done through:
import PackageName::*;

64. Unpacked arrays bit a [5:0];
Arrays can have multiple unpacked dimensions or can even mix packed and unpacked dimensions:
logic [7:0] c [0:2047]; // array of 2048 bytes
Unpacked dimensions cannot be sliced, only single elements can be accessed
They do not reside in memory in contiguous locations – they can be bigger than a packed array because of this reason

65. dynamic arrays
arrays with an unpacked dimension that is not specified in the code. Defined as:
logic [7:0] b [];
Can only be used after having been initialized with the keyword “new”
b = new[100];
Can be resized with: b = new[200](b);
After having been initialized, it can be used like any other array with unpacked dimension

66. associative arrays associative array of bytes:
declared as logic [7:0] a [*];
Acts exactly as a vector of 2^32 bytes:
a[ ] <= 8’b is legal
Memory space is allocated only when used
Accessing the elements is slow in terms of simulation time
If we would try to write to all locations, we would crash everything or generate an error
Ideal to model big memories used only sparsely

67. queues
logic [7:0] q[$];
Supports all operations that can be done on unpacked arrays, plus other functions:
q.push_front(a); // pushes element to the front
q.push_back(a); // pushes element to the back
b=q.pop_back(); // pops element from back
b=q.pop_front(); // pops element from front
q.insert(3,a) // inserts element at position 3
q.delete(3) // deletes the third element
q.delete() // delete all the queue
q.size() // returns size of queue

68. queues Can also be accessed using slicing and $:
q = { q, 6 }; // q.push_back(6)
q = { e, q }; // q.push_front(e)
q = q[1:$]; // q.pop_front() or q.delete(0)
q = q[0:$-1]; // q.pop_back() or q.delete(q.size-1)
q = { q[0:pos-1], e, q[pos:$] }; // q.insert(pos, e)
q = { q[0:pos], e, q[pos+1:$] }; // q.insert(pos+1, e)
q = {}; // q.delete()

69. Structure Hierarchy is encapsulated and hidden in modules
module dut (
output bit c,
input bit [7:0] a,
input bit [7:0] b);
// module code (processes, continuous assignments, instantiations of submodules)
endmodule
There exists also legacy Verilog port declaration methods

70. Structure Verilog legacy port declarations, not recommended.
module test(a,b,c);
input logic [7:0] a;
input b; //unspecified type: logic
output bit [7:0] c; …
endmodule

71. Structure Module declaration with ports module simple_fifo (
input bit clk,
input bit rst,
input bit [7:0] a,
output bit [7:0] b);
// module code (processes, continuous assignments, instantiations of submodules)
endmodule

72. Structure Module instantiation in a top-level testbench
module tb (); // top-level testbench has no inputs/outputs
bit clk, reset;
bit [7:0] av, bv;
simple_fifo dut(.clk(clk), // module instantiation
.rst(reset),
.b(bv),
.a(av));
always
#5ns clk <= !clk;
initial
#30ns reset <= 1;
initial begin
forever
#10ns av <= $random();
end
endmodule

73. Module instantiation Module instantiation in a top-level testbench
Ports can be named out of order
module tb ();
bit clk, reset;
bit [7:0] av, bv;
simple_fifo dut(.clk(clk), // module instantiation
.rst(reset),
.a(av),
.b(bv));
always
#5ns clk <= !clk;
initial
#30ns reset <= 1;
initial begin
forever
#10ns av <= $random();
end
endmodule

74. Module Instantiation
If signals have the same names in the including and the included modules we can use the syntax (.*) for port connection.
module tb ();
bit clk, rst;
bit [7:0] a, b;
simple_fifo dut(.*); // a->a; b->b; clk->clk; rst-> rst
always
#5ns clk <= !clk;
initial
#30ns rst <= 1;
initial begin
forever
#10ns a <= $random();
end
endmodule

75. Module Instantiation
positional connection, each signal is connected to the port in the same position – easy to make errors
module tb (); // top-level testbench has no inputs/outputs
bit clk, reset;
bit [7:0] av, bv;
simple_fifo dut(clk,reset,av,bv);
always
#5ns clk <= !clk;
initial
#30ns rst <= 1;
initial begin
forever
#10ns a <= $random();
end
endmodule

76. Module instantiation module tb (); bit clk, reset; bit [7:0] av, bv;
simple_fifo dut(.*, // ports are connected to signals with the same name
.a(av), // except the ones named later
.b()); // b is left open - unconnected
always
#5ns clk <= !clk;
initial
#30ns reset <= 1;
initial begin
forever
#10ns av <= $random();
end
endmodule

77. Parameters used to express configurability module #(
parameter DEPTH=64,
parameter WIDTH=8 )
simple_fifo (
input logic clk,
input logic rst,
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] b );
localparam internal_param_name;
endmodule
module tb (); // top-level testbench has no inputs/outputs
bit clk, rst;
bit [7:0] a, b;
simple_fifo #(
.DEPTH(64),
.WIDTH(8))
dut (
.clk(clk),
.rst(rst),
.a(a),
.b(b)); …
endmodule

78. Parameters used to express configurability module #(
parameter DEPTH=64,
parameter WIDTH=8 )
simple_fifo (
input logic clk,
input logic rst,
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] b );
localparam internal_param_name;
endmodule
module tb (); // top-level testbench has no inputs/outputs
bit clk, rst;
bit [7:0] a, b;
simple_fifo #(
.DEPTH(64),
.WIDTH(8))
dut (
.clk(clk),
.rst(rst),
.a(a),
.b(b)); …
endmodule

79. Parameters Positional instantiation module #( parameter DEPTH=64,
parameter WIDTH=8 )
simple_fifo (
input logic clk,
input logic rst,
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] b );
localparam internal_param_name;
endmodule
module tb (); // top-level testbench has no inputs/outputs
bit clk, rst;
bit [7:0] a, b;
simple_fifo #(64,8)
dut (
.clk(clk),
.rst(rst),
.a(a),
.b(b)); …
endmodule

80. Parameters Other notation module simple_fifo ( input logic clk,
input logic rst,
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] b );
parameter DEPTH=64
parameter WIDTH=8
localparam internal_param_name; …
endmodule
module tb (); // top-level testbench has no inputs/outputs
bit clk, rst;
bit [7:0] a, b;
simple_fifo #(
.DEPTH(64),
.WIDTH(8))
dut (
.clk(clk),
.rst(rst),
.a(a),
.b(b)); …
endmodule

81. Parameters If not overwritten, they keep their default value
Can have a type:
parameter logic [7:0] DEPTH = 64;
localparam: like parameters, but cannot be modified hierarchically during the instantiation
Used to indicate a parameter that there is not any sense for it to be modified by some higher block in the hierarchy

82. Hierarchical access
From anywhere, it is possible to access any object in the hierarchy by accessing through its full path starting from the top module name:
a <= top.dut.subDutUnit.intObjectName;
Using this, the testbench can monitor any internal DUT signal (white/grey box verification) without having the signal forwarded through ports

83. SystemVerilog Programs
Programs behave and look like modules, but:
They cannot contain always blocks
They cannot include modules
Simulation finishes automatically when all initial have been completed
Always blocks are the basic building block of RTL code, but testbenches don’t need them. Using always blocks in tyestbenches leads to bad coding style
So, programs can do everything that is needed for verification

84. Clocking block default clocking ck1 @(posedge clk);
default input #1ns output #1ns; // reading and writing skew
input a; // a, b, … objects visible from this scope
output b; // input: can read; output: can write
output negedge rst; // overwrite the default skew to the negedge
// of the clock
inout c; // inout: can both read and write
input d = top.dut.internal_dut_signal_name;
endclocking
Inside a module/program, we access signals for read/write inside processes in this way:
ck1.a <= 1’b1;
c = ck1.b; // or c <= ck1.b;
ck1.d <= e;
A write will take place 1ns after the clock edge, a read will read the value that the signal had 1ns before the clock edge

85. Clocking block
The clocking block makes the timing relation (positive-edge of the clock or other) explicit
Since we only verify synchronous systems with a single clock, we need a single clocking block
We add only one clocking block and specify it as “default”
It specifies input and output skews to read/write to the signals
The input/output skew can also be omitted

86. Clocking blocks and programs
The rules of SV say that if we access signals from a program through a clocking block, there will be no race condition between testbench and DUT
Even if no timing skew is specified
When there is a default clocking block in a program/module, we can use the ##n timing construct: wait n cycles as specified by the default clocking block
examples:
##3; // wait 3 cycles
##(2*a); //wait a number of cycles equal to the double of the value of variable a
initial begin
##3 reset <= 0;
forever begin
##1 a <= ~a;
end
##1 executed at a time instant in which there is no clock edge will delay by a fraction of the clock cycle (wait until the first clock edge only)

87. generate Used to generate processes and continuous assignments
No need of generate… endgenerate statements
Define a variable of type genvar
We can then do a generate using a loop or if with with the genvar
Example:
genvar i;
initial ##20 b <= 0;
for(i=0;i<3;i++) begin
initial begin ##(i) a <= $urandom; end
if (i==1) begin
clk) begin …
end

88. named blocks after every begin there can be an optional name
Allows hierarchical access to local variables and to find the variables in the simulator window
ex:
initial begin : inputController …
if (a==10) begin : terminationHandler
end

89. Good Testbench Structure – required for the labs
Write all your testbenches in this way
The testbench program must access all DUT signals for read and write through the default clocking block
Only timing construct allowed in the testbench program: ##
top module
generation of clock
clk
testbench
program
drive
DUT inputs,
check
DUT outputs
DUT

90. Good Testbench Structure
Alternative, also good for the labs: several programs are allowed
all use clocking block in links to the DUT
top module
generation of clock
clk
testbench
program
drive inputs
DUT
testbench
program
check outputs

91. Good testbench structure
You are free to divide programs as you like
The one below is more UVM-like
top module
generation of clock
clk
testbench
program
drive some inputs
DUT
testbench
program
collect outputs
translate them into
a higher level
model
testbench
program
drive other inputs
program
check outputs

92. Good testbench structure – required for the labs - summary
You can use multiple programs, but given the size of the testbenches used in this course, one program that does everything is a good choice
All inputs/outputs to the DUT through the default clocking block
Only timing construct allowed: ## (no need for other levels of timing granularity)
Try to keep separated the different functions (input generation, output checking) using several initial blocks