1. Copyright © 2004 Texas Instruments. All rights reserved. 1.Introduction 2.Real-Time System Design Considerations 3.Hardware Interrupts (HWI) 4.Software Interrupts (SWI) 5.Task Authoring (TSK) 6.Data Streaming (SIO) 7.Multi-Threading (CLK, PRD) 8.BIOS Instrumentation (LOG, STS, SYS, TRC) 9.Static Systems (GCONF, TCONF) 10.Cache (BCACHE) 11.Dynamic Systems (MEM, BUF) 12.Flash Programming (HexAIS, Flashburn) 13.Inter-Thread Communication (MSGQ,...) 14.DSP Algorithm Standard (XDAIS) – Wizard Tool 15.Input Output Mini-Drivers (IOM) 16.Direct Memory Access (DMA) 17.Review DSP/BIOS System Integration Workshop 1 T TO Technical Training Organization

2. How Do I Create XDAIS Algorithms ?  Create an algorithm  Develop I/O vectors to test/validate the algorithm  Decide which invocation/runtime parameters will be offered  Determine what memory requirements the algo will have  Optional – note what DMA resources the algo requires  Invoke the xDAIS Wizard and answer the questions asked  The wizard will create the interface code based on the interview  Add your algorithm to the interface code created by the wizard  Build the object library housing the algo – wizard created  Add your test vectors to the wizard created algo test project  Build and verify the library and test projects  Optional – run the QualiTI validation program  Optional – run the RTSC packager wizard 2 T TO Technical Training Organization

3. The Nextxen xDAIS Wizard  Wizard Tour  Code Review  CCS Projects  Optional Tools  To Order… 3 T TO Technical Training Organization

4. Creating alg Interfaces: xDAIS Wizard Preferences Define the locations of all the related TI software Open Open an existing interface to reuse or modify New Create a new xDAIS compliant interface 4 T TO Technical Training Organization

5. Information About the Component Templates Auto populate most wizard fields with VISA defined values MOD VEN Module and vendor prefixes are required on all exposed variables in xDAIS algorithms 5 T TO Technical Training Organization

6. Define the Target Environment Topology Define whether target is DSP or ARM plus DSP DSP Type Select which DSP core type and endianess to build to 6 T TO Technical Training Organization

7. Define DSP Algorithm Function DSP Method(s) xDAIS defines the create and delete methods for algorithms, but leaves it to the author to determine the signature of the call of the algorithm itself Function Prototype Window Build up prototype of DSP method(s) in steps and see prototype results along the way – here: define function name and return value 7 T TO Technical Training Organization

8. Define DSP Algorithm Function Function Prototype Window Build up prototype of DSP method(s) in steps and see prototype results along the way – here: define argument types 8 T TO Technical Training Organization

9. Defining Parameters IMOD_Params Author can provide as many creation parameters as desired. Wizard aids in typedef creation IMOD_Status Similar to above, but used to modify algo behavior of existing instance Add New Parameter Window Build up parameter structures incrementally. Each param is instance and/or status. Status is read or read/write. Default values also defined here. 9 T TO Technical Training Organization

10. Define Memory Blocks – Instance Object memTab[0] Automatically set up by wizard. Defines the instance object required by all algos Add Allows author to add as many extra blocks of memory as required for algorithm 10 T TO Technical Training Organization

11. Define Additional Memory Blocks memTab[n] Defines size, type, alignment, preferred location and persistence of each required memory block Size Parameter Can be an integer value or an equation based on parameters, as desired by author 11 T TO Technical Training Organization

12. Define DMA Requirements DMA Chans Each channel defines the number of transfers to link, the number of TCCs needed, the priority of the channel, and whether the resources are owned or shared Algos may need no DMA hardware, or can request as many channels as the DSP chip supports 12 T TO Technical Training Organization

13. Ready to “Generate Code” Directory view Shows directory where code will be created and sub-directories therein Append options Name and/or version number subdirectories can be added to root directory specification to manage path for results Root dir User can select root directory for algo interface code to be written to Generate Code Pressing ‘Next” button will generate interface code based on interview responses 13 T TO Technical Training Organization

14. View Code Written by Component Wizard Config Button Allows user to define paths for TI tools, eg: CCS, xDAIS libraries, etc. Only needs to be done once per installation Directory view Files now created, can be opened to view/edit here or via explorer Invoke CCS Launches CCS with proper simulator to create library and test projects Invoke QualiTI Launches TI xDAIS compliance test tool 14 T TO Technical Training Organization

15. The Nextxen xDAIS Wizard  Wizard Tour  Code Review  CCS Projects  Optional Tools  To Order… 15 T TO Technical Training Organization

16. Component Wizard Made Instance Object /* //========================================================== // FIR_TI_Obj */ typedef struct FIR_TI_Obj { IALG_Obj alg; /* MUST be first field of all FIR objs */ XDAS_Int16 firLen; XDAS_Int16 blockSize; XDAS_Int16 * coeffPtr; XDAS_Int16 *workBuffer; XDAS_Int16 *historyBuffer; /* TODO: add custom fields here */ } FIR_TI_Obj; /* //========================================================== // FIR_TI_Obj */ typedef struct FIR_TI_Obj { IALG_Obj alg; /* MUST be first field of all FIR objs */ XDAS_Int16 firLen; XDAS_Int16 blockSize; XDAS_Int16 * coeffPtr; XDAS_Int16 *workBuffer; XDAS_Int16 *historyBuffer; /* TODO: add custom fields here */ } FIR_TI_Obj; 16 T TO Technical Training Organization

17. Component Wizard Made algAlloc() Int FIR_TI_alloc(const IALG_Params *FIRParams, IALG_Fxns **fxns, IALG_MemRec memTab[]) { const IFIR_Params *params = (Void *)FIRParams; if (params == NULL) { params = &IFIR_PARAMS; /* set default parameters */ } memTab[0].size = sizeof(FIR_TI_Obj); memTab[0].alignment = (4 * 8) / CHAR_BIT; memTab[0].space = IALG_SARAM0; memTab[0].attrs = IALG_PERSIST; memTab[WORKBUFFER].size = (params->firLen+params->blockSize-1) * sizeof(XDAS_Int16); memTab[WORKBUFFER].alignment = (2 * 8) / CHAR_BIT; memTab[WORKBUFFER].space = IALG_SARAM0; memTab[WORKBUFFER].attrs = IALG_SCRATCH; memTab[HISTORYBUFFER].size = (params->firLen-1) * sizeof(XDAS_Int16); memTab[HISTORYBUFFER].alignment = (2 * 8) / CHAR_BIT; memTab[HISTORYBUFFER].space = IALG_EXTERNAL; memTab[HISTORYBUFFER].attrs = IALG_PERSIST; return (MTAB_NRECS); } Int FIR_TI_alloc(const IALG_Params *FIRParams, IALG_Fxns **fxns, IALG_MemRec memTab[]) { const IFIR_Params *params = (Void *)FIRParams; if (params == NULL) { params = &IFIR_PARAMS; /* set default parameters */ } memTab[0].size = sizeof(FIR_TI_Obj); memTab[0].alignment = (4 * 8) / CHAR_BIT; memTab[0].space = IALG_SARAM0; memTab[0].attrs = IALG_PERSIST; memTab[WORKBUFFER].size = (params->firLen+params->blockSize-1) * sizeof(XDAS_Int16); memTab[WORKBUFFER].alignment = (2 * 8) / CHAR_BIT; memTab[WORKBUFFER].space = IALG_SARAM0; memTab[WORKBUFFER].attrs = IALG_SCRATCH; memTab[HISTORYBUFFER].size = (params->firLen-1) * sizeof(XDAS_Int16); memTab[HISTORYBUFFER].alignment = (2 * 8) / CHAR_BIT; memTab[HISTORYBUFFER].space = IALG_EXTERNAL; memTab[HISTORYBUFFER].attrs = IALG_PERSIST; return (MTAB_NRECS); } 17 T TO Technical Training Organization

18. Component Wizard Made algFree() Int FIR_TI_free(IALG_Handle handle, IALG_MemRec memTab[ ]) { Int n; FIR_TI_Obj *FIR = (Void *)handle; n = FIR_TI_alloc(NULL, NULL, memTab); memTab[WORKBUFFER].base = FIR->workBuffer; memTab[WORKBUFFER].size = (FIR->firLen+FIR->blockSize-1) * sizeof(XDAS_Int16); memTab[HISTORYBUFFER].base = FIR->historyBuffer; memTab[HISTORYBUFFER].size = (FIR->firLen-1) * sizeof(XDAS_Int16); return (n); } Int FIR_TI_free(IALG_Handle handle, IALG_MemRec memTab[ ]) { Int n; FIR_TI_Obj *FIR = (Void *)handle; n = FIR_TI_alloc(NULL, NULL, memTab); memTab[WORKBUFFER].base = FIR->workBuffer; memTab[WORKBUFFER].size = (FIR->firLen+FIR->blockSize-1) * sizeof(XDAS_Int16); memTab[HISTORYBUFFER].base = FIR->historyBuffer; memTab[HISTORYBUFFER].size = (FIR->firLen-1) * sizeof(XDAS_Int16); return (n); } 18 T TO Technical Training Organization

19. Component Wizard Made algInit() Int FIR_TI_initObj(IALG_Handle handle, const IALG_MemRec memTab[ ], IALG_Handle p, const IALG_Params *FIRParams) { FIR_TI_Obj *FIR = (Void *)handle; const IFIR_Params *params = (Void *)FIRParams; if(params == NULL){ params = &IFIR_PARAMS; /* set default parameters */ } FIR->firLen = params->firLen; FIR->blockSize = params->blockSize; FIR->coeffPtr = params->coeffPtr; FIR->workBuffer = memTab[WORKBUFFER].base; FIR->historyBuffer = memTab[HISTORYBUFFER].base; /* TODO: Implement any additional algInit desired */ return (IALG_EOK); } Int FIR_TI_initObj(IALG_Handle handle, const IALG_MemRec memTab[ ], IALG_Handle p, const IALG_Params *FIRParams) { FIR_TI_Obj *FIR = (Void *)handle; const IFIR_Params *params = (Void *)FIRParams; if(params == NULL){ params = &IFIR_PARAMS; /* set default parameters */ } FIR->firLen = params->firLen; FIR->blockSize = params->blockSize; FIR->coeffPtr = params->coeffPtr; FIR->workBuffer = memTab[WORKBUFFER].base; FIR->historyBuffer = memTab[HISTORYBUFFER].base; /* TODO: Implement any additional algInit desired */ return (IALG_EOK); } 19 T TO Technical Training Organization

20. algActivate & algDeactivate Incomplete… Void FIR_TI_deactivate(IALG_Handle handle) { FIR_TI_Obj *FIR = (Void *)handle; // TODO: implement algDeactivate // TODO: Save any important scratch memory values from FIR->workBuffer // to persistant memory. } Void FIR_TI_deactivate(IALG_Handle handle) { FIR_TI_Obj *FIR = (Void *)handle; // TODO: implement algDeactivate // TODO: Save any important scratch memory values from FIR->workBuffer // to persistant memory. } Void FIR_TI_activate(IALG_Handle handle) { FIR_TI_Obj *FIR = (Void *)handle; // TODO: implement algActivate // TODO: Initialize any important scratch memory values to FIR->workBuffer } Void FIR_TI_activate(IALG_Handle handle) { FIR_TI_Obj *FIR = (Void *)handle; // TODO: implement algActivate // TODO: Initialize any important scratch memory values to FIR->workBuffer } 20 T TO Technical Training Organization

21. Void FIR_TI_activate(IALG_Handle handle) { FIR_TI_Obj *FIR = (Void *)handle; memcpy((Void *)FIR->workBuffer, (Void *)FIR->historyBuffer, (FIR->firLen-1) * sizeof(Short)); } Void FIR_TI_activate(IALG_Handle handle) { FIR_TI_Obj *FIR = (Void *)handle; memcpy((Void *)FIR->workBuffer, (Void *)FIR->historyBuffer, (FIR->firLen-1) * sizeof(Short)); } algActivate and algDeactivate Completed Void FIR_TI_deactivate(IALG_Handle handle) { FIR_TI_Obj *FIR = (Void *)handle; memcpy((Void *)FIR->historyBuffer,(Void *)FIR->workBuffer + FIR->blockSize, (FIR->firLen-1) * sizeof(Short)); } Void FIR_TI_deactivate(IALG_Handle handle) { FIR_TI_Obj *FIR = (Void *)handle; memcpy((Void *)FIR->historyBuffer,(Void *)FIR->workBuffer + FIR->blockSize, (FIR->firLen-1) * sizeof(Short)); } 21 T TO Technical Training Organization

22. Add FIR Code Below Declaration XDAS_Void FIR_TI_filter(IFIR_Handle handle, XDAS_Int16 * pIn, XDAS_Int16 * pOut) { FIR_SW_Obj *FIR = (Void *)handle; shorti, j; // loop counters intsum;// FIR filter accumulator - 32 bits for (j = 0; j buffer_size; j++) // for each sample received { sum = 0;// clear accumulator before each SoP for (i = 0; i filter_size; i++)// for size of filter (# of coeffs) sum += pIn[(i+j)] * FIR->coeffs[i]; // perform sum of products (SoP) pOut[j] = (short)(sum >> 15); // scale final result back to 16bits } XDAS_Void FIR_TI_filter(IFIR_Handle handle, XDAS_Int16 * pIn, XDAS_Int16 * pOut) { FIR_SW_Obj *FIR = (Void *)handle; shorti, j; // loop counters intsum;// FIR filter accumulator - 32 bits for (j = 0; j buffer_size; j++) // for each sample received { sum = 0;// clear accumulator before each SoP for (i = 0; i filter_size; i++)// for size of filter (# of coeffs) sum += pIn[(i+j)] * FIR->coeffs[i]; // perform sum of products (SoP) pOut[j] = (short)(sum >> 15); // scale final result back to 16bits } 22 T TO Technical Training Organization

23. The Nextxen xDAIS Wizard  Wizard Tour  Code Review  CCS Projects  Optional Tools  To Order… 23 T TO Technical Training Organization

24. Invoke CCS – LIB and Test PJTs Invoke CCS Launches CCS with proper simulator to create library and test projects Two projects are created by the xDAIS Wizard: 1. a Library project 2. a Test project Each are nearly complete and ready to use. Author just adds the algo to the library source and test vectors to the main test file. LIB is provided to algo consumer, test project is optional, but a good demo of how to use the algo 24 T TO Technical Training Organization

25. Add DSP Algo to Function Declaration Most algos will be larger, but this example suffices … 25 T TO Technical Training Organization

26. Add Test Vectors to Main Declare in/out buffers Fill with zero, eg Add ‘impulse’ 26 T TO Technical Training Organization

27. Built Projects, Test Result 27 T TO Technical Training Organization

28.  FIR_TTO_IALG.C  Define Instance Object  Implementation of Interface Functions  FIR_TTO_IALGVT.C  Implementation of Vector Table  IFIR.C  Create Parameter Initialization Table  IFIR.H  Define Parameter Structure  Define Vector Table Structure Required XDAIS Delivery Files FIR_TTO.L55L Vendor must group source files into an object library 28 T TO Technical Training Organization

29. Required XDAIS Delivery Files 29 T TO Technical Training Organization

30. The Nextxen xDAIS Wizard  Wizard Tour  Code Review  CCS Projects  Optional Tools  To Order… 30 T TO Technical Training Organization

31. Invoke QualiTI, RTSC Pkgr, XDC Builder RTSC Packager (optional) TI tool that prepares xDAIS algo for RTSC packaging. xDAIS wizard pre- populates most fields for you Invoke XDC (optional) TI tool that completes the RTSC package process Invoke XDC (optional) TI tool that verifies an algo meets xDAIS spec Invoke XDC To set up paths to all TI tools 31

32. Algorithm Documentation 32 T TO Technical Training Organization

33. The Nextxen xDAIS Wizard  Wizard Tour  Code Review  CCS Projects  Optional Tools  To Order… 33 T TO Technical Training Organization

34. ti www.xdaiswiz.com 34 T TO Technical Training Organization

35. The Nextxen xDAIS Wizard  Current Milestone  Other Milestones 35 T TO Technical Training Organization