1. Compiler & Microarchitecture Lab Support of Cross Calls between Microprocessor and FPGA in CPU-FPGA Coupling Architecture G. NguyenThiHuong and Seon Wook Kim Microarchitecture and Compiler Laboratory School of Electrical Engineering Korea University

2. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 2 Motivation void process (struct data* head) { struct data* p; int ret = 0; for( p = head; p; p = p->next){ p->content = (struct elem*) calloc (p->size); if( !p->content ){ ret = 1; break; } else{ ….. } return ret; } struct data* head; int main (void) { ….. error = process (head); ….. } MicroprocessorFPGA process() calloc() … … main() process() main() call return call return Many code sections are executed more efficiently in microprocessor: floating intensive codes, system calls, memory management functions, etc. To support codes containing these functions in FPGA, the FPGA should be able to call back to microprocessor as a master component.

3. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 3 Previous work  Away from code coordination between CPU and FPGA  Handel-C, Impulse C  OCPIP, AMBA  Support nested and recursive only in hardware side  ASH (M. Budiu – ASPLOS ‘04), HybridThreads (E. Anderson-ERSA ‘07)  Do not allow hardware to call software  Allows hardware to return back to software for software code execution  Comrade (H. Lange-FPL ‘07)  Do not support communication among compute units in FPGA No work to support the cross calls between SW and HW without any limitation!

4. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 4 GCC2Verilog approach  GCC2Verilog: A C-to-Verilog translator based on GCC compiler  Including a Verilog backend to generate Verilog code from GCC’s RTL  Making hardware follows software calling convention  Software and hardware share one stack space.  Arguments passing through argument registers and stack.  Preserve software stack layout when performing calls in hardware side.  Supporting:  Unlimited nesting calls in hardware including recursive calls.  Unlimited nesting cross calls between software and hardware. Any hardware function in FPGA can be a master in the system!

5. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 5 Contents  Compilation and Execution Model  Address Resolution  Additional Components  Cross Calling Convention  Experiment Results  Conclusion

6. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 6 GCC2Verilog: Compilation & Execution Model  Code partitioning process:  Divides codes into hardware and software sections  Prepares the address resolution  Compilation process:  Compiles software code section into executable objects  Translates hardware code section into Verilog code and synthesizes them to HW bitstreams (HWIPs).  Execution process:  Running SW executable code in a microprocessor & HWIPs in FPGA  The FPGA communicates with the host processor through a communication channel and memory. Processor Memory C code GCC2Verilog translator GCC compiler Executable code Hardware bitstream HW codes SW codes Verilog code FPGA

7. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 7 Address Resolution  Hardware address resolution:  Assigning an hardware identification number hwid to each HWIP  Software address resolution:  Static link: use the symbol table obtained an executable file to resolve software addresses at HLL-to-HDL translation.  Dynamic link:  Assign an identification number swid to each SW callee called from HW  Use an address_resolver() to obtain SW callee address at run time from swid SW address resolution in dynamic linking

8. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 8 Additional Components Processor Argument Reg SP LR HW controller SW/HW interface … Control unit Datapath HWIP 1 Argument … Local variables Control unit Datapath HWIP N  HW controller:  Controls and schedules the execution between a processor and HWIPs  SW/HW interface:  Provides a uniform interface to communicate with the host processor  HW register set: set of registers for calls:  Argument registers  HW stack pointer  Link register Stack space

9. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 9 Software Calls Hardware Control unit Datapath HWIP1 Argument 0 Argument 2 Argument 3 Argument 1 SP HW controller Control unit Datapath HWIP N SW/HW interface … hwid = 1 enable Argument 4 Pushed registers 1. The wrapper function passes arguments, and calls the HW callee … SW return addr call + hwid 2. HW controller enables the HW callee 3. HW callee reads its arguments, and starts to execute Processor Wrapper Stack space Caller ID (return addr)

10. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 10 Hardware Callee Returns to Software Caller HW controller Control unit Datapath HWIP N SW/HW interface … Argument 4 Pushed registers Control unit Datapath HWIP1 finish interrupt … 4. HW controller interrupts the host processor when the HW callee finishes Processor Interrupt handler Wrapper HW_finish =1 5. The interrupt handler notifies the HW finishing to the wrapper SW return addr Stack space Caller ID (return addr)

11. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 11 Hardware Calls Software Control unit Datapath HWIP1 Argument 0 Argument 2 Argument 3 Argument 1 SP HW return addr HW controller Control unit Datapath HWIP N SW/HW interface … HWIP’s Argument 4 Pushed registers … SW callee argument 4 call + swid interrupt + swid 1. HW caller passes arguments and notifies to the controller about the call 2. HW controller interrupts the processor with SW callee ID Processor Interrupt handler Wrapper func_ptr =0xaef0 3. The interrupt handler resolves the SW callee’s actual address from swid & the wrapper calls the function. pc=func_ptr Stack space Caller ID (return addr)

12. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 12 Hardware Calls Software Argument 0 Argument 2 Argument 3 Argument 1 SP HW return addr HW controller Control unit Datapath HWIP N SW/HW interface … HWIP’s Argument 4 Pushed registers … SW callee argument 4 Processor SW callee 4. SW callee executes its code & returns to the wrapper when finish Control unit Datapath HWIP 1 Wrapper Pushed registers Stack space Caller ID (return addr) return addr

13. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 13 Software Callee Returns to Hardware caller return value HW return addr HW controller Control unit Datapath HWIP N SW/HW interface … HWIP’s Argument 4 Pushed registers … Caller ID (return addr) SW finish enable Processor Wrapper 5. The wrapper notifies to HW controller about SW finish Control unit Datapath HWIP1 6. The HW caller is enabled again to continue its execution Stack space SW callee argument 4

14. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 14 Hardware Calls Hardware Processor Interrupt handler Argument 0 Argument 2 Argument 3 Argument 1 SP Return addr HW controller SW/HW interface HWIP1’s argument 4 Pushed registers … call + hwid = 2 enable Control unit Datapath HWIP2 HWIP2’s argument 4 … Control unit Datapath HWIP1 Pushed registers Stack space Return addr

15. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 15 Hardware Calls Hardware Interrupt handler return value return addr HW controller Control unit Datapath HWIP2 SW/HW interface HWIP1’s argument 4 Pushed registers … HWIP2’s argument 4 finish enable Control unit Datapath HWIP1 Processor … Pushed registers Stack space Return addr

16. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 16 Experiment Result  Experiment setup  Host processor: ARM922T  Benchmarks: EEMBC + factorial (recursion)  Calling overhead:  Cross calls between SW and HW (exclude interrupting time)  Static link: 99 cycles  Dynamic link: 125 cycles  Calls among HWIPs:  Less than 5 cycles

17. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 17 Experiment Result Call overhead including interrupt time BenchmarksNumber of callsCall overhead (%) aifftr3003.52 aiifft3004.00 fft1002.71 bezier200.11 idctrn6004.62 rgbyiq100.02 viterb2008.37 autcor1000.05 factorial1019.91

18. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 18 Conclusion  Novel method to fully support cross calls among microprocessor and FPGA  Allowing FPGA to perform calls back to a microprocessor  Supporting unlimited nested and recursive calls in FPGA  Reasonable cross calling overhead  An importance step toward the full automatic translation of HLL to HDL  Implemented a C-to-Verilog translator based on GCC compiler

19. http://compiler.korea.ac.kr Compiler and Microarchitecture Lab 19 Questions & Answers