1. ECE 260B – CSE 241A Static Timing Analysis 1http://vlsicad.ucsd.edu ECE260B – CSE241A Winter 2005 Logic Synthesis Website: http://vlsicad.ucsd.edu/courses/ece260b-w05 Slides courtesy of Dr. Cho Moon

2. ECE 260B – CSE 241A Static Timing Analysis 2http://vlsicad.ucsd.edu Introduction  Why logic synthesis? l Ubiquitous – used almost everywhere VLSI is done l Body of useful and general techniques – same solutions can be used for different problems l Foundation for many applications such as -Formal verification -ATPG -Timing analysis -Sequential optimization

3. ECE 260B – CSE 241A Static Timing Analysis 3http://vlsicad.ucsd.edu RTL Design Flow RTL Synthesis HDL netlist Logic Synthesis netlist Library Physical Synthesis layout a b s q 0 1 d clk a b s q 0 1 d Module Generators Manual Design Slide courtesy of Devadas, et. al

4. ECE 260B – CSE 241A Static Timing Analysis 4http://vlsicad.ucsd.edu Logic Synthesis Problem  Given l Initial gate-level netlist l Design constraints -Input arrival times, output required times, power consumption, noise immunity, etc… l Target technology libraries  Produce l Smaller, faster or cooler gate-level netlist that meets constraints Very hard optimization problem!

5. ECE 260B – CSE 241A Static Timing Analysis 5http://vlsicad.ucsd.edu Combinational Logic Synthesis Logic Synthesis netlist Library tech independent tech dependent 2-level Logic opt multilevel Logic opt Library Slide courtesy of Devadas, et. al

6. ECE 260B – CSE 241A Static Timing Analysis 6http://vlsicad.ucsd.edu Outline  Introduction  Two-level Logic Synthesis  Multi-level Logic Synthesis  Timing Optimization in Synthesis

7. ECE 260B – CSE 241A Static Timing Analysis 7http://vlsicad.ucsd.edu Two-level Logic Synthesis Problem  Given an arbitrary logic function in two-level form, produce a smaller representation.  For sum-of-products (SOP) implementation on PLAs, fewer product terms and fewer inputs to each product term mean smaller area. F = A B + A B C F = A B I1 I2 O1 O2

8. ECE 260B – CSE 241A Static Timing Analysis 8http://vlsicad.ucsd.edu Boolean Functions f(x) : B n B B = {0, 1}, x = (x 1, x 2, …, x n )  x 1, x 2, … are variables  x 1, x 1, x 2, x 2, … are literals  each vertex of B n is mapped to 0 or 1  the onset of f is a set of input values for which f(x) = 1  the offset of f is a set of input values for which f(x) = 0

9. ECE 260B – CSE 241A Static Timing Analysis 9http://vlsicad.ucsd.edu Logic Functions: Slide courtesy of Devadas, et. al

10. ECE 260B – CSE 241A Static Timing Analysis 10http://vlsicad.ucsd.edu Cube Representation Slide courtesy of Devadas, et. al

11. ECE 260B – CSE 241A Static Timing Analysis 11http://vlsicad.ucsd.edu  A function can be represented by a sum of cubes (products): f = ab + ac + bc Since each cube is a product of literals, this is a “sum of products” representation  A SOP can be thought of as a set of cubes F F = {ab, ac, bc} = C  A set of cubes that represents f is called a cover of f. F={ab, ac, bc} is a cover of f = ab + ac + bc. Sum-of-products (SOP)

12. ECE 260B – CSE 241A Static Timing Analysis 12http://vlsicad.ucsd.edu Prime Cover  A cube is prime if there is no other cube that contains it (for example, b c is not a prime but b is)  A cover is prime iff all of its cubes are prime c a b

13. ECE 260B – CSE 241A Static Timing Analysis 13http://vlsicad.ucsd.edu Irredundant Cube  A cube of a cover C is irredundant if C fails to be a cover if c is dropped from C  A cover is irredundant iff all its cubes are irredudant (for exmaple, F = a b + a c + b c) c b a Not covered

14. ECE 260B – CSE 241A Static Timing Analysis 14http://vlsicad.ucsd.edu Quine-McCluskey Method  We want to find a minimum prime and irredundant cover for a given function. l Prime cover leads to min number of inputs to each product term. l Min irredundant cover leads to min number of product terms.  Quine-McCluskey (QM) method (1960’s) finds a minimum prime and irredundant cover. l Step 1: List all minterms of on-set: O(2^n) n = #inputs l Step 2: Find all primes: O(3^n) n = #inputs l Step 3: Construct minterms vs primes table l Step 4: Find a min set of primes that covers all the minterms: O(2^m) m = #primes

15. ECE 260B – CSE 241A Static Timing Analysis 15http://vlsicad.ucsd.edu QM Example (Step 1)  F = a’ b’ c’ + a b’ c’ + a b’ c + a b c + a’ b c  List all on-set minterms Minterms a’ b’ c’ a b’ c’ a b’ c a b c a’ b c

16. ECE 260B – CSE 241A Static Timing Analysis 16http://vlsicad.ucsd.edu QM Example (Step 2)  F = a’ b’ c’ + a b’ c’ + a b’ c + a b c + a’ b c  Find all primes. primesb’ c’a b’a cb c

17. ECE 260B – CSE 241A Static Timing Analysis 17http://vlsicad.ucsd.edu QM Example (Step 3)  F = a’ b’ c’ + a b’ c’ + a b’ c + a b c + a’ b c  Construct minterms vs primes table (prime implicant table) by determining which cube is contained in which prime. X at row i, colum j means that cube in row i is contained by prime in column j. b’ c’a b’a cb c a’ b’ c’X a b’ c’XX a b’ cXX a b cXX a’ b cX

18. ECE 260B – CSE 241A Static Timing Analysis 18http://vlsicad.ucsd.edu QM Example (Step 4)  F = a’ b’ c’ + a b’ c’ + a b’ c + a b c + a’ b c  Find a minimum set of primes that covers all the minterms “Minimum column covering problem” b’ c’a b’a cb c a’ b’ c’X a b’ c’XX a b’ cXX a b cXX a’ b cX Essential primes

19. ECE 260B – CSE 241A Static Timing Analysis 19http://vlsicad.ucsd.edu ESPRESSO – Heuristic Minimizer  Quine-McCluskey gives a minimum solution but is only good for functions with small number of inputs (< 10)  ESPRESSO is a heuristic two-level minimizer that finds a “minimal” solution ESPRESSO(F) { do { reduce(F); expand(F); irredundant(F); } while (fewer terms in F); verfiy(F); }

20. ECE 260B – CSE 241A Static Timing Analysis 20http://vlsicad.ucsd.edu ESPRESSO ILLUSTRATED Reduce Irredundant Expand

21. ECE 260B – CSE 241A Static Timing Analysis 21http://vlsicad.ucsd.edu Outline  Introduction  Two-level Logic Synthesis  Multi-level Logic Synthesis  Timing optimization in Synthesis

22. ECE 260B – CSE 241A Static Timing Analysis 22http://vlsicad.ucsd.edu Multi-level Logic Synthesis  Two-level logic synthesis is effective and mature  Two-level logic synthesis is directly applicable to PLAs and PLDs But…  There are many functions that are too expensive to implement in two-level forms (too many product terms!)  Two-level implementation constrains layout (AND-plane, OR-plane)  Rule of thumb: l Two-level logic is good for control logic l Multi-level logic is good for datapath or random logic

23. ECE 260B – CSE 241A Static Timing Analysis 23http://vlsicad.ucsd.edu Two-Level (PLA) vs. Multi-Level PLA control logic constrained layout highly automatic technology independent multi-valued logic slower? input, output, state encoding Multi-level all logic general automatic partially technology independent coming can be high speed some results

24. ECE 260B – CSE 241A Static Timing Analysis 24http://vlsicad.ucsd.edu Multi-level Logic Synthesis Problem  Given l Initial Boolean network l Design constraints -Arrival times, required times, power consumption, noise immunity, etc… l Target technology libraries  Produce l a minimum area netlist consisting of the gates from the target libraries such that design constraints are satisfied

25. ECE 260B – CSE 241A Static Timing Analysis 25http://vlsicad.ucsd.edu Modern Approach to Logic Optimization  Divide logic optimization into two subproblems: l Technology-independent optimization -determine overall logic structure -estimate costs (mostly) independent of technology -simplified cost modeling l Technology-dependent optimization (technology mapping) -binding onto the gates in the library -detailed technology-specific cost model  Orchestration of various optimization/transformation techniques for each subproblem Slide courtesy of Keutzer

26. ECE 260B – CSE 241A Static Timing Analysis 26http://vlsicad.ucsd.edu Optimization Cost Criteria The accepted optimization criteria for multi-level logic are to minimize some function of: 1. Area occupied by the logic gates and interconnect (approximated by literals = transistors in technology independent optimization) 2. Critical path delay of the longest path through the logic 3. Degree of testability of the circuit, measured in terms of the percentage of faults covered by a specified set of test vectors for an approximate fault model (e.g. single or multiple stuck- at faults) 4. Power consumed by the logic gates 5. Noise Immunity 6. Wireability while simultaneously satisfying upper or lower bound constraints placed on these physical quantities

27. ECE 260B – CSE 241A Static Timing Analysis 27http://vlsicad.ucsd.edu Representation: Boolean Network Boolean network: directed acyclic graph (DAG) node logic function representation f j (x,y) node variable y j : y j = f j (x,y) edge (i,j) if f j depends explicitly on y i Inputs x = (x 1, x 2,…,x n ) Outputs z = (z 1, z 2,…,z p ) Slide courtesy of Brayton

28. ECE 260B – CSE 241A Static Timing Analysis 28http://vlsicad.ucsd.edu Network Representation Boolean network:

29. ECE 260B – CSE 241A Static Timing Analysis 29http://vlsicad.ucsd.edu Node Representation: Sum of Products (SOP) Example: abc’+a’bd+b’d’+b’e’f (sum of cubes) Advantages: easy to manipulate and minimize many algorithms available (e.g. AND, OR, TAUTOLOGY) two-level theory applies Disadvantages: Not representative of logic complexity. For example f=ad+ae+bd+be+cd+cef’=a’b’c’+d’e’ These differ in their implementation by an inverter. hence not easy to estimate logic; difficult to estimate progress during logic manipulation

30. ECE 260B – CSE 241A Static Timing Analysis 30http://vlsicad.ucsd.edu Factored Forms Example: (ad+b’c)(c+d’(e+ac’))+(d+e)fg Advantages good representative of logic complexity f=ad+ae+bd+be+cd+cef’=a’b’c’+d’e’  f=(a+b+c)(d+e) in many designs (e.g. complex gate CMOS) the implementation of a function corresponds directly to its factored form good estimator of logic implementation complexity doesn’t blow up easily Disadvantages not as many algorithms available for manipulation hence usually just convert into SOP before manipulation

31. ECE 260B – CSE 241A Static Timing Analysis 31http://vlsicad.ucsd.edu Factored Forms Note: literal count  transistor count  area (however, area also depends on wiring)

32. ECE 260B – CSE 241A Static Timing Analysis 32http://vlsicad.ucsd.edu Factored Forms Definition : a factored form can be defined recursively by the following rules. A factored form is either a product or sum where: a product is either a single literal or product of factored forms a sum is either a single literal or sum of factored forms A factored form is a parenthesized algebraic expression. In effect a factored form is a product of sums of products … or a sum of products of sums … Any logic function can be represented by a factored form, and any factored form is a representation of some logic function.

33. ECE 260B – CSE 241A Static Timing Analysis 33http://vlsicad.ucsd.edu Factored Forms When measured in terms of number of inputs, there are functions whose size is exponential in sum of products representation, but polynomial in factored form. Example: Achilles’ heel function There are n literals in the factored form and (n/2)  2 n/2 literals in the SOP form. Factored forms are useful in estimating area and delay in a multi-level synthesis and optimization system. In many design styles (e.g. complex gate CMOS design) the implementation of a function corresponds directly to its factored form.

34. ECE 260B – CSE 241A Static Timing Analysis 34http://vlsicad.ucsd.edu Factored Forms Factored forms cam be graphically represented as labeled trees, called factoring trees, in which each internal node including the root is labeled with either + or , and each leaf has a label of either a variable or its complement. Example: factoring tree of ((a’+b)cd+e)(a+b’)+e’

35. ECE 260B – CSE 241A Static Timing Analysis 35http://vlsicad.ucsd.edu Reduced Ordered BDDs like factored form, represents both function and complement like network of muxes, but restricted since controlled by primary input variables -not really a good estimator for implementation complexity given an ordering, reduced BDD is canonical, hence a good replacement for truth tables for a good ordering, BDDs remain reasonably small for complicated functions (e.g. not multipliers) manipulations are well defined and efficient true support (dependency) is displayed

36. ECE 260B – CSE 241A Static Timing Analysis 36http://vlsicad.ucsd.edu Technology-Independent Optimization  Technology-independent optimization is a bag of tricks: l Two-level minimization (also called simplify) l Constant propagation (also called sweep) f = a b + c; b = 1 => f = a + c l Decomposition (single function) f = abc+abd+a’c’d’+b’c’d’ => f = xy + x’y’; x = ab ; y = c+d l Extraction (multiple functions) f = (az+bz’)cd+e g = (az+bz’)e’ h = cde  f = xy+e g = xe’ h = ye x = az+bz’ y = cd

37. ECE 260B – CSE 241A Static Timing Analysis 37http://vlsicad.ucsd.edu More Technology-Independent Optimization  More technology-independent optimization tricks: l Substitution g = a+bf = a+bc  f = g(a+c) l Collapsing (also called elimination) f = ga+g’bg = c+d  f = ac+ad+bc’d’g = c+d l Factoring (series-parallel decomposition) f = ac+ad+bc+bd+e => f = (a+b)(c+d)+e

38. ECE 260B – CSE 241A Static Timing Analysis 38http://vlsicad.ucsd.edu Summary of Typical Recipe for TI Optimization  Propagate constants  Simplify: two-level minimization at Boolean network node  Decomposition  Local “Boolean” optimizations l Boolean techniques exploit Boolean identities (e.g., a a’ = 0) Consider f = a b’ + a c’ + b a’ + b c’ + c a’ + c b’ l Algebraic factorization procedures f = a (b’ + c’) + a’ (b + c) + b c’ + c b’ l Boolean factorization procedures f = (a + b + c) (a’ + b’ + c’) Slide courtesy of Keutzer

39. ECE 260B – CSE 241A Static Timing Analysis 39http://vlsicad.ucsd.edu Technology-Dependent Optimization Technology-dependent optimization consists of  Technology mapping: maps Boolean network to a set of gates from technology libraries  Local transformations l Discrete resizing l Cloning l Fanout optimization (buffering) l Logic restructuring Slide courtesy of Keutzer

40. ECE 260B – CSE 241A Static Timing Analysis 40http://vlsicad.ucsd.edu Technology Mapping Input l Technology independent, optimized logic network l Description of the gates in the library with their cost Output l Netlist of gates (from library) which minimizes total cost General Approach l Construct a subject DAG for the network l Represent each gate in the target library by pattern DAG’s l Find an optimal-cost covering of subject DAG using the collection of pattern DAG’s l Canonical form: 2-input NAND gates and inverters

41. ECE 260B – CSE 241A Static Timing Analysis 41http://vlsicad.ucsd.edu DAG Covering  DAG covering is an NP-hard problem  Solve the sub-problem optimally l Partition DAG into a forest of trees l Solve each tree optimally using tree covering l Stitch trees back together Slide courtesy of Keutzer

42. ECE 260B – CSE 241A Static Timing Analysis 42http://vlsicad.ucsd.edu Tree Covering Algorithm  Transform netlist and libraries into canonical forms l 2-input NANDs and inverters  Visit each node in BFS from inputs to outputs l Find all candidate matches at each node N -Match is found by comparing topology only (no need to compare functions) l Find the optimal match at N by computing the new cost -New cost = cost of match at node N + sum of costs for matches at children of N l Store the optimal match at node N with cost  Optimal solution is guaranteed if cost is area  Complexity = O(n) where n is the number of nodes in netlist

43. ECE 260B – CSE 241A Static Timing Analysis 43http://vlsicad.ucsd.edu Tree Covering Example into the technology library (simple example below) Find an ``optimal’’ (in area, delay, power) mapping of this circuit Slide courtesy of Keutzer

44. ECE 260B – CSE 241A Static Timing Analysis 44http://vlsicad.ucsd.edu Elements of a library - 1 INVERTER2 NAND23 NAND34 NAND45 Element/Area CostTree Representation (normal form) Slide courtesy of Keutzer

45. ECE 260B – CSE 241A Static Timing Analysis 45http://vlsicad.ucsd.edu Trivial Covering subject DAG 7NAND2 (3) = 21 5INV (2) = 10 Area cost 31 Slide courtesy of Keutzer Can we do better with tree covering?

46. ECE 260B – CSE 241A Static Timing Analysis 46http://vlsicad.ucsd.edu Optimal tree covering - 1 ``subject tree’’ 3 2 2 3 Slide courtesy of Keutzer

47. ECE 260B – CSE 241A Static Timing Analysis 47http://vlsicad.ucsd.edu Optimal tree covering - 2 ``subject tree’’ 5 8 3 2 2 3 Slide courtesy of Keutzer

48. ECE 260B – CSE 241A Static Timing Analysis 48http://vlsicad.ucsd.edu Optimal tree covering - 3 ``subject tree’’ Cover with ND2 or ND3 ? 3 2 2 3 8 13 5 1 NAND23 + subtree 5 1 NAND3= 4 Area cost 8 Slide courtesy of Keutzer

49. ECE 260B – CSE 241A Static Timing Analysis 49http://vlsicad.ucsd.edu Optimal tree covering – 3b ``subject tree’’ 3 2 2 3 8 13 5 4 Label the root of the sub-tree with optimal match and cost Slide courtesy of Keutzer

50. ECE 260B – CSE 241A Static Timing Analysis 50http://vlsicad.ucsd.edu Optimal tree covering - 4 ``subject tree’’ Cover with INV or AO21 ? 5 4 3 8 2 2 13 2 1 Inverter 2 + subtree 13 Area cost 15 1 AO21 4 + subtree 1 3 + subtree 22 Area cost 9 Slide courtesy of Keutzer

51. ECE 260B – CSE 241A Static Timing Analysis 51http://vlsicad.ucsd.edu Optimal tree covering – 4b ``subject tree’’ 5 4 3 8 2 2 13 2 9 Label the root of the sub-tree with optimal match and cost Slide courtesy of Keutzer

52. ECE 260B – CSE 241A Static Timing Analysis 52http://vlsicad.ucsd.edu Optimal tree covering - 5 ``subject tree’’ Cover with ND2 or ND3 ? subtree 19 subtree 24 1 NAND23 Area cost 16 NAND2 NAND3 8 4 9 subtree 18 subtree 22 subtree 34 1 NAND34 Area cost 18 2 Slide courtesy of Keutzer

53. ECE 260B – CSE 241A Static Timing Analysis 53http://vlsicad.ucsd.edu Optimal tree covering – 5b ``subject tree’’ 16 8 4 9 2 Label the root of the sub-tree with optimal match and cost Slide courtesy of Keutzer

54. ECE 260B – CSE 241A Static Timing Analysis 54http://vlsicad.ucsd.edu Optimal tree covering - 6 ``subject tree’’ Cover with INV or AOI21 ? INV AOI21 Area cost 22 5 16 Area cost 18 subtree 116 1 INV 2 subtree 113 subtree 2 5 1 AOI21 4 13 Slide courtesy of Keutzer

55. ECE 260B – CSE 241A Static Timing Analysis 55http://vlsicad.ucsd.edu Optimal tree covering – 6b ``subject tree’’ 5 16 18 13 Label the root of the sub-tree with optimal match and cost Slide courtesy of Keutzer

56. ECE 260B – CSE 241A Static Timing Analysis 56http://vlsicad.ucsd.edu Optimal tree covering - 7 ``subject tree’’ Cover with ND2 or ND3 or ND4 ? Slide courtesy of Keutzer

57. ECE 260B – CSE 241A Static Timing Analysis 57http://vlsicad.ucsd.edu Cover 1 - NAND2 ``subject tree’’ Cover with ND2 ? 16 18 subtree 118 subtree 2 0 1 NAND2 3 Area cost 21 4 9 Slide courtesy of Keutzer

58. ECE 260B – CSE 241A Static Timing Analysis 58http://vlsicad.ucsd.edu Cover 2 - NAND3 ``subject tree’’ Cover with ND3? subtree 1 9 subtree 2 4 subtree 3 0 1 NAND3 4 Area cost 17 9 4 Slide courtesy of Keutzer

59. ECE 260B – CSE 241A Static Timing Analysis 59http://vlsicad.ucsd.edu Cover - 3 ``subject tree’’ Cover with ND4 ? Area cost 19 subtree 1 8 subtree 2 2 subtree 3 4 subtree 4 0 1 NAND4 5 8 4 2 Slide courtesy of Keutzer

60. ECE 260B – CSE 241A Static Timing Analysis 60http://vlsicad.ucsd.edu Optimal Cover was Cover 2 ``subject tree’’ INV 2 ND2 3 2 ND3 8 AOI21 4 Area cost 17 AOI21 ND2 INV ND3 Slide courtesy of Keutzer

61. ECE 260B – CSE 241A Static Timing Analysis 61http://vlsicad.ucsd.edu Summary of Technology Mapping  DAG covering formulation l Separated library issues from mapping algorithm (can’t do this with rule-based systems)  Tree covering approximation l Very efficient (linear time) l Applicable to wide range of libraries (std cells, gate arrays) and technologies (FPGAs, CPLDs)  Weaknesses l Problems with DAG patterns (Multiplexors, full adders, …) l Large input gates lead to a large number of patterns

62. ECE 260B – CSE 241A Static Timing Analysis 62http://vlsicad.ucsd.edu Outline  Introduction  Two-level Logic Synthesis  Multi-level Logic Synthesis  Timing optimization in Synthesis

63. ECE 260B – CSE 241A Static Timing Analysis 63http://vlsicad.ucsd.edu Timing Optimization in Synthesis Factors determining delay of circuit:  Underlying circuit technology l Circuit type (e.g. domino, static CMOS, etc.) l Gate type l Gate size  Logical structure of circuit l Length of computation paths l False paths l Buffering  Parasitics l Wire loads l Layout

64. ECE 260B – CSE 241A Static Timing Analysis 64http://vlsicad.ucsd.edu Problem Statement Given:  Initial circuit function description  Library of primitive functions  Performance constraints (arrival/required times) Generate: an implementation of the circuit using the primitive functions, such that: 1. performance constraints are met 2. circuit area is minimized

65. ECE 260B – CSE 241A Static Timing Analysis 65http://vlsicad.ucsd.edu Current Design Process BehaviorOptiization(scheduling) Partitioning(retiming) Logic synthesis Technology independentTechnology independent Technology mappingTechnology mapping Timing driven place and route Behavioral description Logic and latches Logic equations Gate netlist Layout Gate libraryGate library Perf. ConstraintsPerf. Constraints Delay modelsDelay models

66. ECE 260B – CSE 241A Static Timing Analysis 66http://vlsicad.ucsd.edu Synthesis delay models Why are technology independent delay reductions hard? Lack of fast and accurate delay models 1. # levels, fast but crude 2. # levels + correction term (fanout, wires,… ): a little better, but still crude (what coefficients to use?) 3. Technology mapped: reasonable, but very slow 4. Place and route: better but extremely slow 5. Silicon: best, but infeasibly slow (except for FPGAs) better slower

67. ECE 260B – CSE 241A Static Timing Analysis 67http://vlsicad.ucsd.edu Clustering/partial-collapse Traditional critical-path based methods require l Well defined critical path l Good delay/slack information Problems: l Good delay information comes from mapper and layout l Delay estimates and models are weak Possible solutions: l Better delay modeling at technology independent level l Make speedup, insensitive to actual critical paths and mapped delays

68. ECE 260B – CSE 241A Static Timing Analysis 68http://vlsicad.ucsd.edu Overview of Solutions for delay 1. Circuit re-structuring l Rescheduling operations to reduce time of computation 2. Implementation of function trees (technology mapping) l Selection of gates from library -Minimum delay (load independent model) -Minimize delay and area l Implementation of buffer trees 3. Resizing Focus here on circuit re-structuring

69. ECE 260B – CSE 241A Static Timing Analysis 69http://vlsicad.ucsd.edu Circuit re-structuring Approaches: Local:  Mimic optimization techniques in adders l Carry lookahead (tree height reduction) l Conditional sum (generalized select transformation) l Carry bypass (generalized bypass transformation) Global:  Reduce depth of entire circuit l Partial collapsing l Boolean simplification

70. ECE 260B – CSE 241A Static Timing Analysis 70http://vlsicad.ucsd.edu Re-structuring methods Performance measured by 1. levels, 2. sensitizable paths, 3. technology dependent delays  Level based optimizations: l Tree height reduction (Singh ‘88) l Partial collapsing and simplification (Touati ‘91) l Generalized select transform (Berman ‘90)  Sensitizable paths l Generalized bypass transform (Mcgeer ‘91)

71. ECE 260B – CSE 241A Static Timing Analysis 71http://vlsicad.ucsd.edu Re-structuring for delay: tree-height reduction n lm ij h k 3 6 55 1 4 1 0 0 002 0 0 a bcdefg i 1 0 0 a b m j h k 3 4 1 002 0 0 cdefg n’ Duplicatedlogic 1 2 0 0 5 Criticalregion Collapsed Critical region

72. ECE 260B – CSE 241A Static Timing Analysis 72http://vlsicad.ucsd.edu Restructuring for delay: path reduction i 1 0 0 a b m j h k 3 4 1 002 0 0 cdefg n’ Duplicatedlogic 1 2 0 0 5 i 1 0 0 a b m j h k 3 4 1 002 0 0 cdefg 1 2 0 3 5 n’ 2 1 0 4 Collapsed Critical region New delay = 5

73. ECE 260B – CSE 241A Static Timing Analysis 73http://vlsicad.ucsd.edu Generalized select transform (GST) Late signal feeds multiplexor cdefg a b out cdefg b cdefg b a=0 a=1 out 0 1 a

74. ECE 260B – CSE 241A Static Timing Analysis 74http://vlsicad.ucsd.edu Generalized bypass transform (GBX)  Make critical path false l Speed up the circuit  Bypass logic of critical path(s) f m =f f m+1 f n =g … f m =f f m+1 f n =g … 0 1 g’ dg__df Booleandifference s-a-0 redundant

75. ECE 260B – CSE 241A Static Timing Analysis 75http://vlsicad.ucsd.edu cdefg b cdefg b a=0 a=1 out 0 1 a GST GST vs GBX … 0 1 g’ dh__da a 0/1 b c g h cdefg b cdefg b a=0 a=1 … 0 1 g’ 0/1 c g b GBX a h GBX

76. ECE 260B – CSE 241A Static Timing Analysis 76http://vlsicad.ucsd.edu Thank you!