1. 1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock skew compensation) 5.3. Automated discovery – Invention by Genetic Programming (Creative Design) 5.4. EDA Tools, analog circuit design 5.5. Adaptation to extreme temperature electronics (Survivability by EHW) 5.6. Fault-tolerance and fault-recovery 5.7. Evolvable antennas (In-field adaptation to changing environment) 5.8. Adaptive filters (Function change as result of mission change) 5.9 Evolution of controllers

2. 2 LSI Tester GA-based Adjustment Software + LSI Design + Programmable Delay Circuits 1.Design2.Fabrication3.Adjustment4.Shipping Low operating yield Considerable power dissipation Design clock speed Higher operating yield Less power dissipation Faster clock speed than designed Post-Fabrication Clock Timing Adjustment EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST

3. 3 Clock Input Programmable Delay Element Programmable delay elements are inserted into clock inputs of FFs and circuit blocks. Delay values are determined optimally with GA Adaptive Clock Skew Compensation with GA EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST Clock Lines Problem: Tiny differences in propagation delay, when compounded across all the clock nets in a complex digital product, often lead to unacceptable degradations in overall system-timing margins. This generic problem is often referred to as the "clock skew" problem. Clock skew due to faster clock signals leads to degradation of operational yield rate of LSIs. Beyond 90nm, clock skew cannot be avoided only by design due to process variation

4. 4 Clock Domain or Circuit Block LSI Programmable Delay Circuit Clock Driver Clock Domain or Circuit Block LSI Clock Driver Clock not required Clock Tree Circuit Sub-Block or Flip-Flop Clock adjustment not required Clock adjustment required Clock Domain, Circuit Block, or Flip-Flop Delay Circuit Register N (N bits) Clock Input Clock adjustment for INTER-DOMAIN skew Clock adjustment for INTRA-DOMAIN skew Hierarchical Application of Clock Timing Adjustment EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST

5. 5 Delay Generator Register DAC Delay [ns] Delay Step [ns] Controlling Voltage [V] 30ps Delay Delay Steps Controlling Voltage (V adj ) vs Delay and Delay Steps Delay Generator Clock InClock Out V adj (Controlling Voltage) DAC (Digital-Analog Converter) P·A A A P·B B B P·C C C V ref V out (to V adj ) 0.18um, CMOS process 18Tr: Delay Generator + DAC Some Delay Steps are less than 30ps “Delay Steps” are calculated as differences between adjacent delay plots. Programmable Delay Circuit

6. 6 0.13um, CMOS process, Design for 1GHz(typ), Using the “Programmable Delay Circuits” Test Chip : Multiplier and Memory Test Pattern Generator EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST

7. 7 LSI : Designed at 1000ps(=1GHz) period Register Circuit Register Data Input Data Output Clock Input 1000ps(=1.0GHz) period 800ps1000ps600ps LSI : Clock period is enhanced to 800ps(=1.25GHz) 25% Enhancement of Clock Frequency （ 1000/800=1.25) Register Circuit Register 0 Register Data Input Clock Input 800ps(=1.25GHz) period 800ps1000ps600ps 200ps-delay inserted Advantage No.1: Clock Frequency Speed-up EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST

8. 8 Experiment Result:Clock Frequency Speed-up Each X point represents a unique chip GHz Each X point represents a unique chip Operational clock frequency Operational clock frequency Memory Test Pattern Generators Multipliers GA Details: Population: 50 Termination: 20th Generation Selection: Tournament Selection Crossover: One-Point Crossover Crossover Rate: 1.0 Mutation: Gaussian Mutation (σ=1.0) Mutation Rate: 1.0 GA Details: Population: 50 Termination: 20th Generation Selection: Tournament Selection Crossover: One-Point Crossover Crossover Rate: 1.0 Mutation: Gaussian Mutation (σ=1.0) Mutation Rate: 1.0 Operational clock frequency BEFORE adjustment Operational clock frequency AFTER adjustment 25% increase over all the chips EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST

9. 9 Register Circuit Register Data Input Data Output Clock Input LSI which operates at standard power supply voltage 1.2V LSI which operates at lower power supply voltage 0.8V Lowering power supply voltage, from 1.2V to 0.8V Advantage No. ２ : Power Supply Voltage Reduction EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST Register Circuit Register Data Input Data Output Clock Input Programmable Delay Circuit Circuits which violate timing constraints

10. 10 0.8V0.9V1.0V1.1V1.2V 1.58GHz0% 1.4GHz0% 20%30%40% 1.25GHz 0%40%100% 1.0GHz100% 0.8V0.9V1.0V1.1V1.2V 1.58GHz0% 10%20%10% 1.4GHz30%60%80%100%90% 1.25GHz 100% 1.0GHz100% Operational yield at each voltage and clock frequency, BEFORE adjustment Operational yield at each voltage and clock frequency, AFTER adjustment Clock Adjustment 1 2 3 Measured with the Memory- test-pattern Generators. Experiment Result: Power Supply Voltage Reduction Voltage: 1.2V 0.8V Frequency: 1.0GHz 1.25GHz & EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST

11. 11 Reduction of 2/3 in Vdd Possible power reduction: 4/9 Power Supply Voltage (Vdd) Operational yield 100% 0% 0.8V1.2V 1 2 3 Sakurai’s Formula for CMOS power dissipation [4]: where : Power supply voltage, : Almost constant : Clock frequency 123 correspond to the same marks in Fig. 3 Experiment Result: Power Dissipation Reduction Reduction of 2/3 in Vdd: 1.2V 0.8V Power Reduction: 4/9 (-54%) EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST

12. 12 Time for Clock Timing Adjustment EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST OperationsTime (s) Generation of Delay Setting and Test Data for Function Test 0.55 Write Data to Chip0.02 Execution of Test0.01 Read Results of Test from Chip0.03 Calculation of Fitness0.33 Total Time0.94

13. 13 Memory Test Pattern Generators Multipliers Operational yield [%] Clock frequency [GHz] 41.6% 93.3% 15.0% 90.0% Operating yield after adjustment Operating yield before adjustment Yield improvement from 15% to 90% Yield improvement from 42% to 93% While no chips were operational before adjustment, some chips were operational after post- fabrication adjustment. Experiment Result: Operational Yield Improvement EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST

14. 14 Design Stage TraditionalGA-based Function Design12.01.5 Logic Design30.0 Floor Planning7.02.0 Verification (1)5.0 Layout Design7.01.5 Verification (2)6.04.0 Library Design42.0 Total109.086.0 * 1 day * person *1 Advantage No.3: Design Time Reduction Target Design: DDR-SDRAM controller circuit -21% EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST

15. 15 Summary of GA-based Post-Fabrication Adjustment Higher Clock Frequency (+25% max) Smaller Area (saving circuits trying to avoid clock skew) Reduced Design Time (-21% max) Higher Yield Lower Power Dissipation by lowering Power Supply Voltage (-54% max) EH-2003 talk: Power Dissipation Reductions with Genetic Algorithms Eiichi Takahashi Masahiro Murakawa, Yuji Kasai Tetsuya Higuchi. MIRAI Project /Advanced Semiconductor Research Center, AIST Two 1GHz LSIs and a design experiment demonstrate advantages