ID 620C: Complete Motor Control Integration with Rx62T

ID 620C: Complete Motor Control Integration with Rx62T
This two part presentation is to share the Rx62T peripheral integration to support motor control area. Peripherals are specifically designed to support multitude of algorithms and techniques ranging from sensor based simple trapezoidal to sensorless vector formulation. MTU3, ADC0/1, CMT and DTC are designed to reduce firmware overhead while FPU allows designers to easily implement complex mathematical methods in understandable fashion. Yashvant Jani Ph. D. Director, Applications Engineering 13 October 2010 Version 2.0 © 2010 Renesas Electronics America Inc. All rights reserved.

Yashvant Jani, Ph. D. Director, MPU Applications Engineering
MPU Solutions, SH2A and SH4A architecture, managing hardware design and software development, New Product Specifications OTHER RELEVANT DETAILS 15+ years in semiconductor industry in solution development, performance evaluation, technical training, hardware design to support software and firmware and 15 years in space industry supporting shuttle operations and advance space vehicles Technical courses at UC-Berkeley, University of Tennessee, Duke University, Technical workshops and papers in Motor Control, Fuzzy Logic, Neural Networks, VoIP/Networking and AI learning (at ESC, SPIE, IEEE, IATC and AIAA Control conferences) Experience in Data Compression, Networking & Communication, systems engineering, verification and validation of space system software and performance evaluation of hardware, hardware modeling, simulation Ph.D. in Physics – University of Texas at Dallas, M.S. in Physics and Mathematics, M.Sc. In Nuclear physics 60+ published papers and presentations Interests in Photography & Traveling I can spend rest of the time on this slide but that would not help at all. © 2010 Renesas Electronics America Inc. All rights reserved.

Renesas Technology and Solution Portfolio
Microcontrollers & Microprocessors #1 Market share worldwide * Solutions for Innovation Analog and Power Devices #1 Market share in low-voltage MOSFET** ASIC, ASSP & Memory Advanced and proven technologies In the session 110C, Renesas Next Generation Microcontroller and Microprocessor Technology Roadmap, Ritesh Tyagi introduces this high level image of where the Renesas Products fit. The big picture. <Click> NOTE For Reviewer, the below notes are from the 110C presentation so you can better understand this slide ___________________________________________________________________________________________________________________________________ The wealth of technology you see here is a direct result of the fact that Renesas Electronics Corporation was formed on April 1, 2010 as a joint venture between Renesas Technology and NEC Electronics — Renesas Technology having been launched seven years ago by Hitachi, Ltd. and Mitsubishi Electric Corporation. There are four major areas where Renesas offers distinct technology advantage. --The Microcontrollers and Microprocessors are the back bone of the new company. Renesas is the undisputed leader in this area with 31% of W/W market share. --We do have a rich portfolio of Analog and power devices. Renesas has the #1 market share in low voltage MOSFET solutions. --We have a rich portfolio of ASIC solution with an advanced 90nm, 65nm, 40nm and 28nm processes. The key solutions are for the Smart Grid, Integrated Power Management and Networking --ASSP: Industry leader for USB 2.0 and USB 3.0. Solutions for the cell phone market -- Memory: #1 in the Networking Memory market * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). © 2010 Renesas Electronics America Inc. All rights reserved.

Renesas Technology and Solution Portfolio
Microcontrollers & Microprocessors #1 Market share worldwide * Solutions for Innovation ASIC, ASSP & Memory Advanced and proven technologies Analog and Power Devices #1 Market share in low-voltage MOSFET** This is where our session, 620C, is focused within the ‘Big picture of Renesas Products’, Microcontroller and Microprocessors. NOTE For Reviewer, the below notes are from the 110C presentation so you can better understand this slide” ________________________________________________________________________________________________________________________________ Let me first introduce our rich portfolio of microcontrollers and microprocessors solution which includes 8,16 and 32 bit CPU cores. * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 4 © 2010 Renesas Electronics America Inc. All rights reserved.

Microcontroller and Microprocessor Line-up
Up to 1200 DMIPS, 45, 65 & 90nm process Video and audio processing on Linux Server, Industrial & Automotive Superscalar, MMU, Multimedia Up to 500 DMIPS, 150 & 90nm process 600uA/MHz, 1.5 uA standby Medical, Automotive & Industrial High Performance CPU, Low Power Up to 165 DMIPS, 90nm process 500uA/MHz, 2.5 uA standby Ethernet, CAN, USB, Motor Control, TFT Display High Performance CPU, FPU, DSC Legacy Cores Next-generation migration to RX H8S H8SX M16C R32C Here are the MCU and MPU Product Lines, I am not going to cover any specific information on these families, but rather I want to show you where this session is focused <CLICK> NOTE For Reviewer, the below notes are from the 110C presentation so you can better understand this slide ___________________________________________________________________________________________________________________________________ Notes for Devcon Positioning Slide: There’s a lot of vital information on this slide, which spotlights the Renesas MCU/MPU product lines recommended for new designs. Perhaps the best way to discuss this material is to cover it from a very high level. Since the merger, we have scrutinized the needs of our global markets, reassessed our strengths, and implemented a business strategy focusing on supporting the ‘ubiquitous computing’ paradigm. This insightful concept — often abbreviated as ‘ubicomp’, and sometimes termed ‘pervasive computing’ or ‘ambient intelligence’ — was introduced by Mark Weiser of Xerox in 1988. Ubiquitous computing refers to a new genre of computing, a worldwide electronic environment in which computer-controlled products completely permeate the life of end users around the globe. Obviously, many types of products and an enormous range of applications are encompassed by this paradigm, all driven by human ingenuity, engineering creativity and marketing expertise. To one extent or another, people everywhere are already beginning to enjoy the first wave of benefits of the concept’s reality. General Purpose Ultra Low Power Embedded Security Up to 10 DMIPS, 130nm process 350 uA/MHz, 1uA standby Capacitive touch Up to 25 DMIPS, 150nm process 190 uA/MHz, 0.3uA standby Application-specific integration Up to 25 DMIPS, 180, 90nm process 1mA/MHz, 100uA standby Crypto engine, Hardware security 5 © 2010 Renesas Electronics America Inc. All rights reserved.

Notes continued from previous page
(continued from notes section of previous page) Renesas knows that to best facilitate the further growth and success of ubiquitous computing, we cannot offer just one CPU core or a single family of microcomputers. Thus, taking advantage of the broad span of leading technologies we have built up, we have decided to concentrate our future R&D efforts on five major CPU cores capable of excelling at major elements of the huge task. Each is optimized for addressing the requirements of diverse sets of key applications. With that business plan in mind, allow me to explain the relative positioning of these five architectures within our strong portfolio of MCUs and MPUs. An important design trend in recent years has seen system engineers taking full advantage of all the computing power that IC makers have made available — often right up to the limits of project constraints. As a result, there have been more and more design-ins of chips with 32-bit architectures. Renesas now has three complementary 32-bit microcontroller and microprocessor families aiding that trend. At the top end of the features-and-capability spectrum we offer the devices in the SuperH family, a superscalar RISC architecture that executes two instructions per clock cycle. Devices in the SuperH family deliver up to 1200 DMIPS performance, so they’re ideal for and popular in multimedia, Real-time industrial-control, server, and automotive engine-control applications. We also recommend them for performing video and audio processing on Linux-based systems Our second series of 32-bit system design solutions is the V850 family, which today is the top-selling line of 32-bit microcontrollers, worldwide. The V850 architecture provides high performance (up to 500 DMIPS), yet consumes low power while doing so. System designers have found these devices to be particularly well suited for automotive applications. The lower-frequency V850 chips are optimized for low power. Thus, they are excellent choices for portable medical equipment, for example. (notes continued from this page) Our third line of 32-bit products is one of the newest in the industry: the devices based on the RX architecture, which today is being volume manufactured with an in-house 90nm process. This architecture implements an upward migration path for customers using the legacy H8 and M16C architectures that have dominated the 16-bit embedded control system market for the past many years. RX MCUs are destined to be the devices chosen for advanced products for ubiquitous computing, especially those in the connectivity, motor-control, consumer and industrial areas. Two 8/16-bit architectures give Renesas the ability to meet the system design needs of millions of lower-end embedded system products — now and in the future. The MCUs in the R8C family achieve up to 10DMIPS performance and are superb choices for general-purpose applications. For instance, devices with the R8C architecture offer capacitive touch and the lowest-cost motor-control solutions. Our 78K architecture — the last of Renesas’ five major CPU cores — aims at situations requiring extremely low power dissipation. These MCUs, produced in a 150µm process, deliver up to 18 DMIPS performance; yet they consume only 190µA/MHz in full active mode and hold leakage current down to as low as 0.3µA. Among the devices in the 78K family are popular application-specific chips tailored for metering, medical and lighting applications. Quite obviously, this line-up slide highlights six product families, not five. The fifth one — our very successful R-Secure line — is a tremendous asset for us and our customers because it directly addresses a vital issue inherent to sensitive applications of ubiquitous computing: Security. These chips allow system engineers to obtain the data and operational integrity mandatory for financial-transaction and access-control applications, among many others. For instance, the R-Secure product line provides proven and trusted complete solutions for machine-to-machine authentications and smart card applications. Our R-Secure chips have a powerful crypto engine, true random number generator, voltage monitor circuit, and numerous other embedded security features. Moreover, they’re produced and distributed in carefully controlled ways to ensure the delivery and reliability of the strong protection they provide. Now let’s sum up this top-level view of the microcontroller and microprocessor line-up. The aim of the entire global Renesas Electronics organization is to make it easy for you to select the MCU/MPU architecture best suited to your application requirements. We will support your choice through the development and production process today and in the long term. In that regard, I must emphasize here that we will continue to support all existing architectures as long as customers want to use them. Nevertheless, for new designs, we urge you to choose the best fit from the five main CPU cores and product lines previously mentioned. The SuperH, V850, RX, R8C and 78K architectures will be the focus of our future R&D efforts as Renesas works to help accelerate the worldwide spread of ubiquitous computing. As a result, they will offer you the most system design advantages in the years to come. © 2010 Renesas Electronics America Inc. All rights reserved.

Microcontroller and Microprocessor Line-up
Up to 1200 DMIPS, 45, 65 & 90nm process Video and audio processing on Linux Server, Industrial & Automotive Superscalar, MMU, Multimedia Up to 500 DMIPS, 150 & 90nm process 600uA/MHz, 1.5 uA standby Medical, Automotive & Industrial High Performance CPU, Low Power Up to 165 DMIPS, 90nm process 500uA/MHz, 2.5 uA standby Ethernet, CAN, USB, Motor Control, TFT Display High Performance CPU, FPU, DSC Legacy Cores Next-generation migration to RX H8S H8SX M16C RX Motor Control R32C RX600 (100 MHz, Low Power) RX200 (50 MHz, Ultra Low Power) This presentation applies to Rx family <Click> NOTE For Reviewer, the below notes are from the 110C presentation so you can better understand this slide _____________________________________________________________________________________________________________________ Notes for Devcon Positioning Slide: There’s a lot of vital information on this slide, which spotlights the Renesas MCU/MPU product lines recommended for new designs. Perhaps the best way to discuss this material is to cover it from a very high level. Since the merger, we have scrutinized the needs of our global markets, reassessed our strengths, and implemented a business strategy focusing on supporting the ‘ubiquitous computing’ paradigm. This insightful concept — often abbreviated as ‘ubicomp’, and sometimes termed ‘pervasive computing’ or ‘ambient intelligence’ — was introduced by Mark Weiser of Xerox in 1988. Ubiquitous computing refers to a new genre of computing, a worldwide electronic environment in which computer-controlled products completely permeate the life of end users around the globe. Obviously, many types of products and an enormous range of applications are encompassed by this paradigm, all driven by human ingenuity, engineering creativity and marketing expertise. To one extent or another, people everywhere are already beginning to enjoy the first wave of benefits of the concept’s reality. General Purpose Ultra Low Power Embedded Security Up to 10 DMIPS, 130nm process 350 uA/MHz, 1uA standby Capacitive touch Up to 25 DMIPS, 150nm process 190 uA/MHz, 0.3uA standby Application-specific integration Up to 25 DMIPS, 180, 90nm process 1mA/MHz, 100uA standby Crypto engine, Hardware security 7 © 2010 Renesas Electronics America Inc. All rights reserved.

Innovation – Silicon for Motor Control
■ Issues commonly heard from designers and developers Need more CPU bandwidth How are we going to meet standards? Wish the firmware code can be smaller ‘……’ ‘……’ ‘……’ Too many tasks to do in software Must have simultaneous automatic ADC triggering ‘……’ © 2010 Renesas Electronics America Inc. All rights reserved. 8

The RX62T – Motor Control Viewpoint
■ Overcome problems and meet market demand Higher MHz for performance Better code efficiency Support for Standards Rx62T Higher level of peripheral integration Internal interfaces to support firmware © 2010 Renesas Electronics America Inc. All rights reserved. 9

Agenda RX62T Overview 7 min CPU enhancements and FPU 10 min
Peripheral integration MTU min Break time min ADC min GPT min Standards support min Examples – peripherals usage 15 min Q&A min © 2010 Renesas Electronics America Inc. All rights reserved.

Key Takeaways By the end of this session you will be able to:
Identify the strengths of the Rx devices Understand the peripheral integration available Effectively use hardware constructs for firmware efficiency © 2010 Renesas Electronics America Inc. All rights reserved.

Overview of RX62T DEBUG DTC ICU 100 MHz 165 DMIPS Harvard CPU FPU MAC
MUL & DIV CRC FLASH 256KB/ 128KB SRAM 16KB/ 8KB DATA FLASH 8KB POR/LVD OSC 125Khz PLL ADC 12b 4ch, 3S/H 3OP Amp 3Comp ADC 10b 10ch, 2S/H EXT OSC CMT 16bit X 4chn WDT I-WDT MTU3 16bit x 8chn GPT SCI x3 I2C x1 RSPI GPIO w/MUX RCAN (optional) © 2010 Renesas Electronics America Inc. All rights reserved.

Overview of RX62T RX600 CPU Core – 100MHz Flash Memory Analog Timers
CISC CPU with Harvard Architecture 165 DMIPS at 100MHz Floating Point Unit (FPU) Multiply Accumulate (MAC) Flash Memory 100 MHz, zero wait-state access Analog 4 ch x 2 units 12-bit ADC 4 sample & hold, 1usec conversion 12 ch x10-bit ADC, 2 sample-hold, 1usec 6 Op. Amp and 6 Comparator Timers MTU3 16bit x 8chn General purpose PWM timer 16bit x 4ch Compare Much Timer 16bit x 4 channels Communication UART/Clock synchronous serial x 3Unit RSPI x 1 Unit , LIN I/F x 1Unit, I2C bus I/F 1 Unit RCAN 1unit(Option) Others Data Transfer Controller (DTC) POR, LVD On chip oscillator 125KHz for independent WDT Package LQFP-100 (14x 14mm, 0.5mm pitch) 100 MHz 165 DMIPS Harvard CPU FLASH 256KB/ 128KB SRAM 16KB/ 8KB DATA FLASH 8KB ICU DEBUG DTC FPU CRC MAC MUL & DIV ADC 10b 10ch, 2S/H OSC 125Khz I-WDT MTU3 16bit x 8chn CMT 16bit X 4chn ADC 12b 4ch, 3S/H PLL ADC 12b 4ch, 3S/H POR/LVD WDT GPT 16bit X 4chn GPIO w/MUX 3OP Amp 3Comp EXT OSC 3OP Amp 3Comp RSPI x1 SCI x3 I2C x1 RCAN (optional) © 2010 Renesas Electronics America Inc. All rights reserved.

RX62T Group RX CPU Core – 100MHz (2.7 to 5.5V) Low Power Consumption
Enhanced Harvard Architecture 165 DMIPS at 100MHz Floating Point Unit (FPU) Multiply Accumulate (MAC) Low Power Consumption 500 mA per MHz, all peripherals active True 5V Operation Choose devices 2.7V-3.6V, or 4.0V-5.5V Flash Memory 100 MHz, zero wait-state access Analog 8 channels 12-bit ADC, 1 ms conversion time 12 channels 10-bit ADC, dual sample-hold, 1 ms 6 Op. Amp w/PGA and 6 Comparators Advanced Timers to Drive 2 Motors MTU3 16-bit x 8 channels General purpose PWM timer 16-bit x 4 channels Compare Match Timer 16-bit x 4 channels Communication UART/Clock synchronous serial x 3 Unit RSPI x 1 Unit, LIN I/F x 1Unit, I2C bus I/F 1 Unit RCAN 1unit (Option) Others DMA capability with Data Transfer Controller (DTC) POR, LVD On chip oscillator 125KHz±10% for independent WDT Small Packages, 64, 80, 100, and 112 pin RX62T True 5V Memory SRAM up to 16KB Zero-Wait Flash up to 256KB Data Flash 8KB Advanced Timers System Interrupt Cont. 16 levels 9 pins Data Management DTC Clock Generation OSC PLL IRC POR/ LVD Timers MTU3 16-bit 8 ch GPT 16-bit 4 ch 2 x CMT 16-bit 2 ch WDT 8-bit 1 ch I-WDT 14-bit 1 ch Communication CAN 2.0B LIN I2C 3 x SCI GPIO SPI The block diagram for the RX62T group is shown here on the right. The RX62T includes the 165 DMIPS RX CPU core which comes with integrated floating point unit and digital signal processing capabilities. Operating from 2.7V to 5.5V, the RX62T comes with Flash sizes up to 256KB. There are several communication interfaces including CAN, LIN, I2C, three SCI, and an SPI. The RX62T has an advanced timer set including an 8 channel 16-bit MTU3, a 4-channel 16-bit GPT, and a 4-channel 16-bit CMT. The RX62T has a 12-bit ADC with 16 channels with integrated programmable operational amplifiers and integrated window comparators. It also has a 10-bit ADC with 12 channels and power on reset and low voltage detection circuitry. The programmable DMA helps to optimize data throughput. Advanced Analog Analog ADC 10-bit 12 ch 2 x ADC 12-bit 4 ch with PGA, S/H, & Comparators Low pin count © 2010 Renesas Electronics America Inc. All rights reserved.

RX62T Product Selection FLASH / SRAM R5F562TABDFM 2.7V to 5.5V Version R5F562TABDFF 2.7V to 5.5V Version R5F562TABDFP 2.7V to 5.5V Version R5F562TABDFH 2.7V to 5.5V Version 80 MHz CAN R5F562TAADFM RX62TA CAN, 4.0V TO 5.5V R5F562TAADFF RX62TA CAN, 4.0V TO 5.5V R5F562TAADFP RX62TA CAN, 4.0V TO 5.5V R5F562TAADFH RX62TA CAN, 4.0V TO 5.5V 256 KB / 16 KB R5F562TAEDFM 2.7V to 5.5V Version R5F562TAEDFF 2.7V to 5.5V Version R5F562TAEDFP 2.7V to 5.5V Version R5F562TAEDFH 2.7V to 5.5V Version 80 MHz R5F562TADDFM RX62TA 4.0V TO 5.5V R5F562TADDFF RX62TA 4.0V TO 5.5V R5F562TADDFP RX62TA 4.0V TO 5.5V R5F562TADDFH RX62TA 4.0V TO 5.5V No CAN R5F562T7BDFM 2.7V to 5.5V Version R5F562T7BDFF 2.7V to 5.5V Version R5F562T7BDFP 2.7V to 5.5V Version R5F562T7BDFH 2.7V to 5.5V Version 80 MHz CAN R5F562T7ADFM RX62T7 CAN, 4.0V TO 5.5V R5F562T7ADFF RX62T7 CAN, 4.0V TO 5.5V R5F562T7ADFP RX62T7 CAN, 4.0V TO 5.5V R5F562T7ADFH RX62T7 CAN, 4.0V TO 5.5V 128 KB / 8 KB R5F562T7EDFM 2.7V to 5.5V Version R5F562T7EDFF 2.7V to 5.5V Version R5F562T7EDFP 2.7V to 5.5V Version R5F562T7EDFH 2.7V to 5.5V Version 80 MHz R5F562T7DDFM RX62T7 4.0V TO 5.5V R5F562T7DDFF RX62T7 4.0V TO 5.5V R5F562T7DDFP RX62T7 4.0V TO 5.5V R5F562T7DDFH RX62T7 4.0V TO 5.5V No CAN The RX62T group comes in three Flash sizes of 64KB, 128KB, and 256KB. There are four package options ranging from 64 pins up to 112 pins. Devices are available with and without CAN. All devices come with the industrial temperature range of -40C to +85C. Specific part ordering numbers are shown in each box. R5F562T6BDFM 2.7V to 5.5V Version R5F562T6BDFF 2.7V to 5.5V Version 80 MHz R5F562T6ADFM RX62T6 CAN, 4.0V TO 5.5V R5F562T6ADFF RX62T6 CAN, 4.0V TO 5.5V CAN All Devices : 40oC to +85oC 64 KB / 8 KB R5F562T6EDFM 2.7V to 5.5V Version R5F562T6EDFF 2.7V to 5.5V Version 80 MHz R5F562T6DDFM RX62T6 4.0V TO 5.5V R5F562T6DDFF RX62T6 4.0V TO 5.5V No CAN 64 pins LQFP 10x pitch 80 pins LQFP 14x pitch 100 pins LQFP 14x pitch 112 pins LQFP 20x pitch © 2010 Renesas Electronics America Inc. All rights reserved.

RX CPU Features 32-bit RX CPU 32-bit FPU DSP Multiple busses
Dhrystone DMIPS per MHz RX 1.0 1.5 ARM7 ARM9 Cortex-M3 Cortex-M4 1.65 DMIPS/MHz Note: Dhrystone numbers for ARM processors taken from 32-bit RX CPU Mostly single clock instructions 5-stage execution pipeline Ultra fast 5-cycle interrupts 32-bit FPU Single precision IEEE-754 compliant Direct access to General Registers DSP Repeated Multiply & Accumulate 64-bits Multiply & Accumulate 48-bits Barrel shifter 32-bits The RX CPU core uses mostly single clock instructions such as the single cycle 32-bit by 32-bit multiplication instruction. Processing is accomplished by a 5-stage pipeline using an Enhanced Harvard architecture. It is also possible to configure four general purpose registers to be used for dedicated interrupt control thereby creating an ultra fast interrupt handler which can service interrupts with only a five-cycle latency. Compared to ARM architectures such as ARM7, Cortex-M3, and Cortex-M4 the RX has significantly higher performance as indicated by it’s Dhrystone 2.0 rating of 1.65 DMIPS per MHz. The floating point unit complies with the IEEE-754 standard format for single precision 32-bit data. In order to boost performance, the FPU is able to use the general purpose registers eliminating the need for lengthy load and store operations. The RX CPU core also includes a 64-bit Repeated Multiply & Accumulate unit, a 48-bit Multiply & Accumulate unit, and a 32-bit Barrel Shifter which together give the RX excellent DSP handling capabilities. And since data processing can often put significant loading on the CPU, the RX is implemented with five internal busses and multiple data controllers and there is also a dedicated data controller for the external bus all of which relieve the CPU of loading during traditionally heavy data processing operations such as fast analog-to-digital sampling, fast digital-to-analog output, and TFT-LCD control. Multiple busses Enhanced Harvard bus Internal DTC and DMA controllers External bus with DMA controller © 2010 Renesas Electronics America Inc. All rights reserved.

RX CPU Features for Performance
■　 CPU Architecture Hardware divider and FPU in addition to multiplier and MAC 64-bit instruction bus with memory protection unit ■　 Enhanced Harvard architecture Parallel execution of instruction fetches and memory accesses boosts pipeline performance ■　 Five-stage pipeline The five-stage pipeline configuration speeds up instruction execution. ■　 Zero Wait state flash access (up to 100MHz) ■　 Single-precision floating-point unit The single-precision floating-point unit uses general registers for operations. © 2010 Renesas Electronics America Inc. All rights reserved. 19

Register Set : Sixteen 32-Bit General Registers
Facilitating register-register operations reduces memory accesses. The use of general registers simplifies compiler optimization. High-speed interrupt registers speed up interrupt handling. Augmented general registers can be allocated for dedicated use by interrupts, enabling a further speed increase. General registers Control registers 32 bits 32 bits ISP Interrupt stack pointer R0 (SP＊) USP User stack pointer R1 R2 INTB Interrupt table register R3 PC Program counter R4 PSW Processor status word register R5 High-speed interrupt registers Backup PSW BPSW R6 BPC Backup PC R7 FINTV Fast interrupt vector register facilitate 【他動】〔物・事が仕事などを〕楽［容易｛ようい｝］にする、手助けする、促進｛そくしん｝する augment 【自動】増える、増加｛ぞうか｝［増大｛ぞうだい｝・拡大｛かくだい｝］する R8 FPSW Floating-point status word register R9 CPEN Coprocessor enable register R10 R11 R12 R13 R14 R15 * Stack pointer © 2010 Renesas Electronics America Inc. All rights reserved. 20

RX Architecture RX600 CISC CPU 100MHz CPU Core
16 x 32bit General Purpose Registers 32bit Floating Point Unit 9 x 32bit Control Registers Memory Protection Unit 32 x 32 MAC to 48bit or 80bit Result 32 x 32 DIV or MULT to 32bit or 64bit Result Interrupt Control On-Chip Debug © 2010 Renesas Electronics America Inc. All rights reserved.

Enhanced Harvard Architecture
Simultaneous instruction fetches and memory accesses boosts performance RX CPU core Flash Instruction Fetch Instruction Interface 64-bit IF RAM ALU Divider Multiplier Shifter ALU Divider Multiplier Shifter Peripheral Functions A Harvard architecture has two independent buses, one for Instruction fetches and one for memory accesses. The two separate buses allow for parallel execution. The IF bus is 64-bit allowing for single cycle fetches of multi-byte instructions. The Memory bus is 32-bit. Memory Access Data Interface 32-bit registers x16 Separate buses allow parallel execution © 2010 Renesas Electronics America Inc. All rights reserved. 22

RX600 internal bus configuration
One bus for CPU and second for the other bus-master modules RX CPU ROM RAM MTU3 GPT SCI Instruction Bus Operand Bus DTC Internal main bus 1 Internal main bus 2 Internal peripheral bus External bus control External bus EXDMAC Operates in synchronization with ICLK Operates in synchronization with PCLK Operates in synchronization with BCLK AD USB Data Flash …. Bus Name Bus master Connected module or bus Instruction / Operand bus CPU Internal Flash ROM / RAM Internal main bus 1 Internal peripheral bus and external bus Internal main bus 2 DMAC, DTC and E-DMAC Internal Flash ROM / RAM, Internal peripheral bus and external bus Internal peripheral bus CPU, DMAC, DTC and E-DMAC Internal peripheral module External bus CPU, DMAC, DTC, E-DMAC and EXDMAC External devices © 2010 Renesas Electronics America Inc. All rights reserved.

Multiple Busses Increase Performance
RX CPU RAM TMR SCI ADC Instruction Bus Operand Bus DMA controller Main Bus 1 External bus control External DMA …. External Memory External LCD Flash Main Bus 2 Peripheral Bus External Bus RX CPU DMA controller DMA controller Three simultaneous operations RX CPU executing out of Flash DMA storing ADC data to RAM EXDMAC sending data from external memory to External LCD External DMA controller External DMA controller RX uses an Enhanced Harvard bus architecture having separate dedicated busses for instructions and operands and both busses can access both SRAM and Flash memory. There are also three additional busses. There are two internal main busses and one internal peripheral bus with accompanying data controllers and an external bus with external data controller which together give the RX extremely high data throughput. In the example shown here, three operations are occurring in parallel simultaneously. The RX CPU is executing code out of Flash while the ADC is storing data to RAM and the external bus is used to send data from the external memory to the external LCD. © 2010 Renesas Electronics America Inc. All rights reserved.

RX Architecture … CPU Core and Pipeline
RX600 CISC CPU 5-STAGE PIPELINE D M E F W 5 STAGES OF PIPELINE F = FETCH INSTRUCTION D = DECODE INSTRUCTION E = EXECUTE INSTRUCTION M = READ OR WRITE MEMORY W = WRITE BACK TO REGISTER ENHANCED HARVARD ARCHITECTURE 32bit Operands CODE 64bit Instructions DATA 5-STAGE PIPELINE PRE-FETCH QUEUE Holds 4 to 32 Instructions for Slower Memory Memory Interface 64 32 100MHz CPU Core TICK F D F TICK E D F TICK M E D F TICK W M E D F TICK F W M E D TICK D F W M E TICK E D F W M TICK M E D F W TICK Typically SRAM Typically Flash Memory 16 x 32bit General Purpose Registers 9 x 32bit Control Registers Memory Protection Unit Interrupt Control On-Chip Debug E W M E D F 64bits 32bit Floating Point Unit 32 x 32 MAC to bit or 80bit Result ENHANCED HARVARD ARCHITECTURE WRITE BUFFER For Slower Memory 32 x 32 DIV or MULT to 32bit or 64bit Result Buffer Only for Writes First lets examine the RX CPU core itself, the pipelined instruction path, and the operand path. At the heart of the RX600 MCU is a 100MHz, 32-bit CISC CPU core seen here. The CPU has 16 general purpose 32-bit registers for © 2010 Renesas Electronics America Inc. All rights reserved.

Harvard architecture allows
Five Stage Pipeline Parallel execution of instruction fetch and data memory access provides ideal execution rate of one clock cycle per instruction. 5 stages IF: Instruction Fetch D: Decode E: Execution M: Memory access WB: Write Back Harvard architecture allows parallel execution IF D E M WB IF D E M WB IF D E M WB IF D E M WB This illustrates the basic operation of the 5 stage pipeline. Parallel execution of instruction reads and memory accesses provide an ideal execution rate of one instruction per clock cycle. A 64-bit wide bus allows for single access fetches of multi-cycle instructions. Out-of-order completion of non-dependent subsequent instructions is also utilized for the eventuality of a pipeline stall. IF D E M WB © 2010 Renesas Electronics America Inc. All rights reserved. 26

Out-of-Order Completion
5 Stage Pipeline and Out-of-Order Completion Example. RX efficiently executes the instruction. 1 MOV [R1], R2 IF D E M M M M WB Order Completion 2 ADD R4, R5 IF D S S S S E WB 3 SUB R6, R7 IF S S S S D E WB Loss of instruction 1 MOV [R1], R2 IF D E M M M M WB Out-of-Order Completion 2 ADD R4, R5 IF D E WB 3 SUB R6, R7 IF D E WB IF: Instruction Fetch　　D: Decode　　E: Execution M: Memory access　　WB: Write Back　　S: Stall <<When there is no dependence in the following instruction>> The stall is not generated on the pipeline since it the next orders. 　：The order of executing instruction © 2010 Renesas Electronics America Inc. All rights reserved.

Rx Flash Technology 90nm MONOS cell Processing performance gap 30 MHz
1.5 Billion Flash MCU shipped Zero-Wait access up to 100MHz RX with 100 MHz flash Processing performance Processing performance gap Competing MCU with 30 MHz flash 3 or more 2 wait cycles The RX family utilizes Renesas’s industry leading 90nm flash MONOS technology which has an extremely fast 10ns access time enabling true 100MHz operation with zero-wait states. Because the Flash memory can provide instructions to the RX CPU at the same rate the CPU consumes them (100MHz), there is no need for memory acceleration techniques that use complex pre-fetch queues and branch caching to make up for slower Flash memory. This means the RX has minimal delay when a branch is taken in the code compared to competing Flash MCUs which use acceleration techniques to compensate for slow Flash. Code with many branches is very typical in embedded control applications. You can see in the graph that when slower Flash is used, wait-states are required as the CPU operates faster than the native speed of the Flash memory, and this becomes prevalent after code branches. Even with the use of memory acceleration, it is still not possible to totally compensate for the wait-states, causing the CPU to stall which degrades overall performance. 1 wait cycle 　30 MHz　　100 MHz　 MCU operating frequency 1 wait cycle D E M WB IF W D E M WB IF W 2 wait cycle no wait © 2010 Renesas Electronics America Inc. All rights reserved.

performing sequential
Single-Precision Floating-Point Unit The single-precision (32-bit) data format defined in IEEE 754* is supported. The exceptions defined in IEEE 754 are supported. Subtract, multiply, divide, and integer-convert instructions general registers are supported. Operation using dedicated data registers RX operation using general registers No load/store instruction needed General registers General register Floating-point unit Load/store Dedicated data registers Effective when performing sequential calculations Floating-point unit * IEEE Standard for Binary Floating-Point Arithmetic © 2010 Renesas Electronics America Inc. All rights reserved. 29

RX-FPU Benchmarks Single precision operations are 1.5 times or more faster using FPU Single precision RX600 with FPU (Number of Cycle) Comparison (No FPU/RX-FPU) Sinf 236 122 1.9 Cosf 246 118 2.1 Tanf 556 185 3.0 Asinf 1,330 186 7.2 Acosf 1,683 197 8.5 Atanf 230 154 1.5 Logf 249 168 Expf 223 138 1.6 Powf 5,018 619 8.1 RX600 without FPU © 2010 Renesas Electronics America Inc. All rights reserved.

FPU Improves Performance
We implemented sensorless vector control for 3-phase BLDC motor in RX62T Both, fixed point formulation as well as FPU based formulation were implemented and tested We also implemented full trig functions as well as table based trig functions to reduce the CPU bandwidth in both methods For trig functions, we used library approach with basic FPU instructions Tests were run at 10kHz carrier frequency We compared the performance of both in terms of CPU bandwidth and code size © 2010 Renesas Electronics America Inc. All rights reserved.

FPU Improves Performance
CPU Bandwidth and Code Size Comparison at 10KHz PWM Frequency for Sensorless Vector Control CPU Bandwidth Fixed-Point SVC FPU SVC Sine, Cosine, Atan functions 38% 23% Sine, Cosine, Atan tables 26% 18% Code Size Fixed-Point SVC FPU SVC Sine, Cosine, Atan functions 14.273K 7.222K Sine, Cosine, Atan tables 12.462K 6.221K © 2010 Renesas Electronics America Inc. All rights reserved.

Multifunction Timer Unit 3
© 2010 Renesas Electronics America Inc. All rights reserved.

MTU3 For Motor Control MTU3 can generate two sets of 6 PWM outputs to control two motors Automatic dead time insertion Interrupt skip function for slow current loops ADC triggering during PWM period for current measurements Timer counter clock up to 100MHz Encoder and Hall sensor input measurements Protection Functions PWM output shut down by an external trigger Main clock stop detection – PWM out put shut down Mode registers and counters not accessible by CPU when in operation (protection from CPU malfunction) Register data can be transferred by DTC Additional channels for related functions © 2010 Renesas Electronics America Inc. All rights reserved.

Multi Function Timer Pulse Unit 3（MTU3）
Eight channels with 16 bit counters Maximum 24 pulse input/output, and 3 input Input clock up to 100MHz Operation Modes Output compare match (Low, High, Toggle) Synchronous operation: Multiple channels synchronized simultaneous clear by compare match or input capture PWM Mode: 0 to 100% duty PWM output Input capture event timing, Encoder counting ADC start, Interrupt generation, DMAC/DTC trigger ch0 ch1 ch2 ch3 ch4 ch5 MTU3 3 Ph.PWM Output Encoder Input ch6 ch7 3 ph PWM output Input capture © 2010 Renesas Electronics America Inc. All rights reserved.

Multi Function Timer Pulse Unit 3（MTU3）
Motor Related PWM Output Ch 3 & 4 for first PWM set, Ch 6 & 7 for second PWM set Each set has six PWM output with automatic dead time insertion Types of PWM waveform Reset synchronous PWM mode: saw tooth PWM wave Complementary PWM mode: Triangle waveform TGR3A TGR3B TGR4A TGR4B U phase PWM Carrier period PWM duty Offset = deadtime Ch3 Ch 4 Dead time ON OFF V phase PWM W phasePWM © 2010 Renesas Electronics America Inc. All rights reserved.

0/100% Duty PWM Output 0%duty: same as the value of TGRA_3
Example of 0/100% duty output in complementary PWM mode Value of TGRB_3 TGRA_3 TCNTS TCDR TCNT_3 TCNT_4 TDDR Value of TGRB_3 H'0000 100% TIOC3B 0% TIOC3D 0%duty: same as the value of TGRA_3 100%duty : H’0000 © 2010 Renesas Electronics America Inc. All rights reserved.

Dead-time “0” Generate Ideal PWM Output without dead time
TGR3A TCNT3 TCNT4 TGR3B TGR4A TGR4B Set “0” on Dead time Reg. TIOC3B U-phase TIOC3D TIOC4A V-phase TIOC4C TIOC4B W-phase TIOC4D © 2010 Renesas Electronics America Inc. All rights reserved.

MTU3 Double Buffer Function
With two buffers, one for up counter and another for down counter, MTU3 can generate asymmetric PWM waveforms with reduced CPU overhead ：Temp -> timing of transferring TGRA_3 TCDR TGRB_4 TDDR Buffer-A (for down counter) H'1111 Buffer-B ((for up counter) ) H'1110 Temp-A (for down counter) H'1111 Temp-B ((for up counter) H'1110 TGRB_4 (compare register) H'1110 H'1111 H'1110 H'1111 H'1110 H'1111 TIOC4B(out) TIOC4D(out) © 2010 Renesas Electronics America Inc. All rights reserved.

Interrupt Skip Function
To Reduce CPU Load on Interrupt Handling interrupt skip number can be set from 0 to 7 times interrupt skip request signal: TGI3A（Top） and TGI4V(Bottom） Ex. 1： Interrupt request signal：Top end, skip number：2 times Ex. 2： Interrupt request signal：Bottom end, skip number：one time Interrupt request No interrupt Request Usually, Current Loop frequency is not the same as PWM carrier frequency. This function is used when Interrupt every PWM period is NOT required. © 2010 Renesas Electronics America Inc. All rights reserved.

A/D conversion start trigger A/D conversion start trigger
Synchronizing A/D conversion with PWM Automatic generation of trigger A/D conversion start trigger Counter Time A/D conversion start trigger © 2010 Renesas Electronics America Inc. All rights reserved.

ADC synchronization within PWM
MTU can generate ADC Start Trigger for Motor Control Two sets of a register for generating trigger and its buffer register built-in Can work in conjunction with interrupt skip function Using Interrupt Skip Function：Top end , skip number：2 times A/D start trigger TADCOR4x (MTU reg.) No interrupt & No trigger © 2010 Renesas Electronics America Inc. All rights reserved.

Protection Functions for Inverter Unit
PWM Output shut- down by external trigger The 6-phase PWM output pins can be set automatically to high-impedance state by external signals Halting of PWM Output when Oscillator is Stopped Upon detecting that the clock input to this LSI has stopped, the 6-phase PWM output pins are automatically set to the high-impedance state. Register and Counter Miswrite Prevention Function This function can disable CPU access to the mode registers, control registers, and counters to prevent miswriting due to CPU runaway. In the access-disabled state, the applicable registers are read as undefined and writing to these registers is ignored. © 2010 Renesas Electronics America Inc. All rights reserved.

PWM Output Shut down by External Trigger
POE Function Input pins for Fault Signals from Power Module Can select falling edge or low level sampling respectively for detection PWM output can be set automatically to high-impedance To analyze the cause of fault/error condition, detection flag is available for each input pin If the selected edge or level is detected, interrupt is generated POE block diagram Falling edge detection circuit Low level detection circuit Input POE3 POE2 POE1 POE0 High Impedance control Interrupt request CPU PWM Output Digital Noise Filtering Circuit © 2010 Renesas Electronics America Inc. All rights reserved.

Speed & Position Detection
Two-phase encoder pulse measurement Phase count mode/MTU 16 bit up/down counter Up/down count by detecting phase difference between A and B phase Count up/down condition is able to choose from four conditions (mode1 to 4) Can be utilized as automatic speed / location data measurement Automatic measurement of encoder pulse width Measurement can start every periodic cycle Can be used as 32 bit up counter Ch1 and ch2 can operate as 32 bit counter © 2010 Renesas Electronics America Inc. All rights reserved.

Encoder Pulse Count Function
- Example of phase count mode 1 - TCLKA or TCLKC TCLKB or TCLKD Counter value Count Down Count Up TCNT1 or TCNT2 Time © 2010 Renesas Electronics America Inc. All rights reserved.

Speed & Position detection
- Automatic speed/ Position detection - A Phase Channel 1 Edge TCNT1(Up down counter) B Phase Detect circuit Internal capture trigger signal TGR1A （Capture the value ofTCNT1) Counter clock TGR1B (Capture the value ofTCNT1) TCNT0 (Interval timer) Compare match signal TGR0A (speed control period) TGR0C（Location control period）（Capture the pulse width of counter clock of TCNT1) TGR0B Internal capture trigger signal TGR0D (Buffer register of TGR0B) Channel 0 © 2010 Renesas Electronics America Inc. All rights reserved.

Break Time – Part 2 to follow

Features of 12bit AD Converter
2 units (AD0 and AD1), 4 channels per unit (Total 8 cha ) Each unit has the same functionality, independent operation Simultaneous sampling is possible for 1-3 input channels Conversion time depends on operating voltage 1.0µs per 1 to 5.5V and PCLK=50MHz 2.0µs per 1 to 4.0V and PCLK=50MHz Self-diagnostic functions Voltage can be generated internally (AVREFHx0V, AVREFHx1/2V, or AVREFH) Programmable gain amplifiers, 3 channels/unit Window comparators, 3 channels/unit © 2010 Renesas Electronics America Inc. All rights reserved.

Each unit designed for one shunt or Three shunt current detection
12bit A/D Configuration with PGA Each unit designed for one shunt or Three shunt current detection Unit 0 3 S/H for 3 shunt current detection Double data register for one shunt ch0 Continuous AD Conversion for same channel ＊ Data Register AN0 OP S/H Multiplexer Data Register ch1 AN1 OP S/H Data Register A/D S/H ch2 AN2 OP S/H Data Register External Reference Voltage ch3 AN03/CVref L Data Register Unit1 ch0 Data Register AN4 OP S/H Multiplexer Data Register ch1 AN5 OP S/H Data Register A/D S/H ch2 AN6 OP S/H Data Register ch3 AN07/CVref H Data Register External Reference Voltage ＊Choice of Gain （6ch, x 2.0/2.5/3.077/3.636/4.0/4.444/5.0/5.714/6.667/10.0/13.333） OpAmp can through when you do not needs Comparator Input © 2010 Renesas Electronics America Inc. All rights reserved.

CPU interrupt or POE or timer input
Comparator Configuration Each 12bit AD unit has three window comparators ＊ Window Comparator AN00 OP ch0 Noise Canceller 12bit AD Unit 0 Window Comparator Timer (GPT) Input AN01 OP ch1 Window Comparator AN02 OP ch2 CPU Interrupt Comparator output External Reference Voltage AN03/CVref L POE Circuit Window Comparator AN04 OP ch4 12bit AD Unit 1 Window Comparator Upper side Reference AN05 OP ch5 Window Window Comparator AN06 OP ch6 Lower side Reference Exceeding This level Exceeding This level External Reference Voltage AN07/CVref H ＊Choice of Gain （6ch, x 2.0/2.5/3.077/3.636/4.0/4.444/5.0/5.714/6.667/10.0/13.333） Op Amp can through when you do not needs CPU interrupt or POE or timer input © 2010 Renesas Electronics America Inc. All rights reserved.

Features of PGA On-chip op-amp (3 op-amp per AD unit: Total 6)
Programmable gain: x 2.0, 2.5, 3.077, 3.636, 4.0, 4.444, 5.0, 5.714, 6.667, 10.0, and (11 steps in total) 3ch out of 4ch of 12-bit A/D incorporates the op-amp 12-bit A/D unit0 x bit A/D unit x 3: 6 in total The PGA can be skipped if not necessary. Note1: Load capacitance of operational amplifier monitor terminal is up to 20pF and load resistance is below 1MΩ © 2010 Renesas Electronics America Inc. All rights reserved.

Features of Comparators
6 Window comparators 2 Reference pins: high ‘CVrefH’ and low ‘CVrefL’ Comparison performed before or after OpAmp. (selectable) Comparator output enables several operations Link to POE and convert an output of specific timer to HiZ Interrupt to CPU and monitor active comparators Internally specifies C1 to C6 output and use them as GPT trigger Trigger signal (counter start, stop or clear, IC trigger or OC output forced change (High/Low/HiZ)) Output stage incorporates noise canceller. ADCLK cancels noise (to avoid sensitive reaction). Noise canceller is supported by digital filter. fCLK, /2, /4, /8, /16, and /128 enables level sampling (x 16) 7 levels reference voltage for comparator - 1/8 to 7/8 AVrefh © 2010 Renesas Electronics America Inc. All rights reserved.

General purpose PWM Timer (GPT)

General purpose PWM Timer (GPT)
Design of GPT is based on the following functional capabilities Software PFC One shot PWM, start/stop control by external pin Power Supply Control AC/DC, DC/AC,DC/DC Independent chopping control needed for each phase Output compare with buffering Motor control timer © 2010 Renesas Electronics America Inc. All rights reserved.

AD Trigger register with buffers
Block Diagram of GPT Frame register with double buffer CH0 Clock Source ICLK GTPDBR CH1 GTPBR Internal Comparator Output C1 to C6 CH2 GTPR CH3 Up Down Counter IC GTIOCA Comparator GTIOCB GTCCRA Internal Bus GTCCRB GTCCRC GTCCRD GTETRG GTCCRE GTCCRF GTADTRA GTADTRB GTDVU GTDVF OC/IC register with buffers GTADTBRA GTADTBRB GTDBU GTDBF GTADTDBRA GTADTDBRB Dead time register with buffer Up slope/ Down slope AD Trigger register with buffers Low speed OCO counter Counter Synchronous Circuit Low speed OCO LOCO counter Measured Value Measured Value Control Register Deviation Value Average © 2010 Renesas Electronics America Inc. All rights reserved.

GPT Functionality – Compare Match Output
Saw tooth waveform TCNT Frame period Register GTPR PWM Duty Register GTCCRA GTCCRB Every compare match occur of GTCCR and counter, port will change High/Low/toggle） GTIOCxA Ex.１ GTIOCxB Every compare match of GTCCR and counter, Port will be “high” . And every frame, the port will be “Low” Ex.2 GTIOCxA Buffer operation of compare match register GＴCCRF Buffer register 2 AA GTCCRD GTCCRC GTCCRA BB CC TCNT xx yy GＴCCRD GＴCCRE Buffer register 1 GＴCCRC GＴCCRB Compare match register GＴCCRA © 2010 Renesas Electronics America Inc. All rights reserved. ＴＣＮＴ

GPT Functionality – Compare Match Output
Triangle waveform Frame period Register GTPR Ex.1 GTCCRA GTCCRB PWM Duty Buffer operation of compare match register GＴCCRF Buffer register 2 GＴCCRD AA GTCCRD GTCCRC GTCCRA BB CC TCNT GＴCCRE Buffer register 1 GＴCCRC GＴCCRB Compare match register GＴCCRA ＴＣＮＴ © 2010 Renesas Electronics America Inc. All rights reserved.

GPT Functionality – Complementary PWM
Triangle waveform Frame period Register GTPR Ex.1 GTCCRA GTCCRB PWM Duty Low Active Dead time Up Down (GTCCRA-GTDVU) (GTCCRA-GTDVD) dead time values for up counting and down counting can be specified individually GＴCCRB Buffer operation of compare match register GＴCCRA GＴCCRD GＴCCRC ＴＣＮＴ Compare match register Buffer register 1 Buffer register 2 GＴDVD GＴDVU GＴBD GＴBU PWM Duty Dead time Up Down (GTCCRA-GTDVU/D) AA GTCCRD GTCCRC GTCCRA BB CC TCNT © 2010 Renesas Electronics America Inc. All rights reserved.

GPT Functionality – Complementary PWM
Saw tooth waveform Frame period Register GTPR Ex.1 GTCCRD GTCCRC PWM Duty Low Active Dead time Up Down GTCCRC-GTDVU GTCCRA-GTDVD Internal register Buffer operation of compare match register GＴCCRA GＴCCRD GＴCCRC ＴＣＮＴ Compare match register PWM Duty start PWM Duty end GＴDVD GＴDVU GＴBD GＴBU PWM Duty Dead time Up Down AA GTCCRD GTCCRC GTCCRA BB CC TCNT © 2010 Renesas Electronics America Inc. All rights reserved.

GPT Functionality – Phase Shifting
Counter of CH0 Ex.1)　 Counter of CH1 Counter of CH2 Timer synchronization CH0 CH1 CH2 CH3 GTIOC0A GTIOC0B Synchronous circuit GTIOC1A GTIOC1B GTIOC2A GTIOC2B GTIOC3A GTIOC3B Ex.2)　Phase shift You can specify the timing by using another channel Counter of CH0 Counter of CH1 Counter of CH2 © 2010 Renesas Electronics America Inc. All rights reserved.

IEC60730＊１ Requirements and Rx62T Hardware
Corresponding features of Rx62T IEC60730 Item＊２ Monitoring by Independent Watchdog Timer with Checker software. Interrupt handling and execution Clock Clock stop detection and clock delay monitoring CRC(Cyclic Redundancy Check) on chip External communication Port values are always readable even when pins are other peripheral function Input/Output peripheral A/D converter Provide three level (Avreff,1/2AV ref, AVrefss) for self test ＊１　International fail safe standard ＊２　Not all of IEC60730 © 2010 Renesas Electronics America Inc. All rights reserved.

Examples – Peripherals Usage

3 Phase BLDC Motor with Hall Sensors
Hall sensors are connected with Ch5 as shown It measures the count between each transition giving the speed Interrupt is generated for commutation ADC triggered by PWM for current measurement CMT or any other timer channel can be used for speed loop as well as current loop ch3 ch4 ch5 MTU3 3 Ph.PWM Output Hall sensor Input + ADC0 + CMT Current loop Alternatively Ch 6 and 7 can be used for PWM output And ADC1 can be used for current measurements © 2010 Renesas Electronics America Inc. All rights reserved.

3 Phase BLDC Motor without Hall Sensors
BEMF employed for control Comparators can be used to detect the zero crossing ADC measurements for current loop CMT or any other timer channel for speed and current loop ch3 ch4 MTU3 3 Ph.PWM Output ch6 ch7 3 ph PWM output OR + ADC0 OR ADC1 Comparators & current loop + CMT © 2010 Renesas Electronics America Inc. All rights reserved.

+ CMT 3-Phase BLDC Motor with Digital Encoder + ADC0 OR ADC1 OR
Set up ch 3 and 4 to generate 3-phase PWM Alternate is ch 6 and 7 for the PWM output Use ch 1 or ch 2 for digital encoder inputs CMT or any other timer channel for speed and current loop timings ch1 ch2 ch3 ch4 MTU3 3 Ph.PWM Output Digital Encoder Input ch6 ch7 Alternate PWM + ADC0 OR ADC1 Current Measurements + CMT OR © 2010 Renesas Electronics America Inc. All rights reserved.

+ CMT 3-Phase BLDC Motor with Resolver + ADC0 OR ADC1 OR
Set up ch 3 and 4 to generate 3-phase PWM Alternate ch 6 and 7 for PWM output Operation Mode: Output Compare in Toggle mode, complementary with dead time insertion Use ADC0 or ADC1 for Resolver inputs ch3 ch4 MTU3 3 Ph.PWM Output ch6 ch7 3 ph PWM output + ADC0 OR ADC1 Resolvers OR + CMT © 2010 Renesas Electronics America Inc. All rights reserved.

Two 3-phase Motors Advanced Analog Advanced timers
12-bit ADC with 8-channels and 1ms conversion time per channel 6 Programmable Op Amps 6 Sample/Hold circuits 6 Window comparators RX62T S/H PGA Motor Current 12-bit ADC 3 CAN Analog GPIO Timers Fan Motor Analog Comparator Detection Circuit PWM Generation 6 Timer PWM Output PWM Interrupt Fault Signal Advanced timers PWM Generation using MTU3 (Multi-function Timer Unit) and GPT (General Purpose Timer) PWM Interrupt using Port Output Enable function S/H PGA High performance plus advanced analog and timer peripherals make the RX62T the ideal solution for inverter and motor control applications. In the home appliance example shown here, the RX62T is driving two 3-phase motors simultaneously using the advanced timers in PWM mode. The RX62T also includes integrated programmable operational amplifiers and window comparators which reduces the need for external components and thereby reduces BOM costs. Motor Current 12-bit ADC 3 Compressor Inverter Analog Comparator Detection Circuit PWM Generation 6 Timer PWM Output PWM Interrupt Fault Signal © 2010 Renesas Electronics America Inc. All rights reserved.

+ CMT Two 3-phase Motors with Sensors + ADC0 + ADC1 MTU3
Set up ch 3 and 4 to generate first set of 3-phase PWM Set up ch 6 and 7 for the second set Input clock typically 50 MHz, carrier freq 20kHz Operation Mode: Output Compare in Toggle mode, complementary with dead time insertion Sensor based implementation Use channel 5 for Hall sensor inputs Use ch 1 or ch 2 for digital encoder inputs Use ADC0 and ADC1 for Resolver inputs MTU3 + ADC0 + ADC1 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 Current loop Hall sensor Input + CMT Digital Encoder Input 3 Ph.PWM Output 3 ph PWM output © 2010 Renesas Electronics America Inc. All rights reserved.

+ CMT Two 3-phase Motors Sensorless MTU3
Set up ch 3 and 4 to generate first set of 3-phase PWM Set up ch 6 and 7 for the second set Input clock typically 50 MHz, carrier freq 20kHz Operation Mode: Output Compare in Toggle mode, complementary with dead time insertion Sensorless implementation Set up ADC0 for one motor and ADC1 for second motor Trapezoidal method can use comparators for zero cross Vector control can use current measurements for flux and angle estimation ch3 ch4 MTU3 3 Ph.PWM Output ch6 ch7 3 ph PWM output Trigger ADC0 Trigger ADC1 + CMT © 2010 Renesas Electronics America Inc. All rights reserved.

GPT in 3-Phase Motor Control
Three channels of GPT can be synchronized and used in complementary mode to generate complete set of PWM for a 3 phase motor Timer synchronization CH0 CH1 CH2 CH3 GTIOC0A GTIOC0B Synchronous circuit GTIOC1A GTIOC1B GTIOC2A GTIOC2B GTIOC3A GTIOC3B Counter of CH0 Ex.1)　 Counter of CH1 Counter of CH2 © 2010 Renesas Electronics America Inc. All rights reserved.

GPT in Power Supply Control
Compare Match Output using saw tooth waveform PWM with cycle by cycle GTCCRD GTCCRC GTCCRA AA BB CC TCNT DD EE FF Internal timer Output Comparator Or Trigger Final output wave form when over current is detected, the PWM output is shut off during every carrier period © 2010 Renesas Electronics America Inc. All rights reserved.

GPT in PFC Control Compare Match Output using saw tooth waveform
One shot pulse mode PWM with comparator start GTCCRD GTCCRC GTCCRA BB AA CC TCNT Comparator Output Initialize Operation start CPU interrupt Write DD EE FF Final output wave form Every zero cross timing, GPT starts one shot PWM waveform as shown. © 2010 Renesas Electronics America Inc. All rights reserved.

You can specify the timing by using another channel
GPT in Interleaved PFC Three channels of GPT can be phase shifted to generate proper PWM output for each interleaved PFC wave form Timer synchronization Ex.2)　Phase shift You can specify the timing by using another channel Counter of CH0 Counter of CH1 Counter of CH2 CH0 CH1 CH2 CH3 GTIOC0A GTIOC0B Synchronous circuit GTIOC1A GTIOC1B GTIOC2A GTIOC2B GTIOC3A GTIOC3B © 2010 Renesas Electronics America Inc. All rights reserved.

GPT in Main Clock Monitoring
Main Clock Monitoring function overview This function measure the LOCO clock period using internal count clock as source. Every period, the value is written in LCNT registers. There are 16 such registers to store the values (LCNT0 to 15). Always latest 16 values are kept in those resisters like a FIFO Average value of 16 measurements is calculated in ‘Average’ register (by summation of LCNT0 to 15 and 4bit shift) Firmware can set the acceptable value in compare register. When the measured average value is different compared to acceptable value, GPT generates an interrupt to the CPU. LOCO Average Deviation acceptable value Measurement result 0 counter Divider 1/1 1/16 1/128 1/256 ※IWDT must be in operation Measurement result 1 Measurement result 2 Measurement result 15 Measurement finish interrupt Interrupt GPT count clock © 2010 Renesas Electronics America Inc. All rights reserved.

Many Combinations Are Possible
Rx family provides basic structure to have many combinations possible MTU3 ADC0 and ADC1 GPT CMT Comparators DTC © 2010 Renesas Electronics America Inc. All rights reserved.

Summary Rx62T is a special semiconductor design that provides complete motor control capability CPU combined with FPU provides unique ability for algorithm implementation and execution MTU3 + ADC + protection functions are extremely helpful Comparators and PGA provide enhanced capability to create differentiated solutions DTC reduces CPU load and helps design better firmware architecture © 2010 Renesas Electronics America Inc. All rights reserved.

Questions Question 1: Is it possible to control two motors and also implement PFC using one MCU? Answer 1: Yes, if Renesas devices such Rx62T and SH7216 are used. Look in the custom animation! By putting a picture on top, we will print this page as a handout and it will not contain the answer! The picture is the page being presented, but only the question is showing. I used Snag-It to capture the picture. The picture goes away with previous! (using custom animation) © 2010 Renesas Electronics America Inc. All rights reserved.

Multiply and Accumulation
RX62T Over view RX CPU (100 MHz) Flash up to 256KB High-performance 32bit CPU core : RX CPU 165 DMIPS at 100MHz Single-precision FPU Hardware multiplier, divider & MAC On-chip memory High speed Embedded Flash 256 KB / 128KB 16kB/8kB RAM 32KB/8KB Data Flash (30K E/W) Operation Frequency 100 MHz at Vcc = 3.0 or 5.5 V Package 　 LQFP-100 (14x 14mm, 0.5mm pitch) FPU Data Flash 8KB (30k times E/W) Multiplier, Divider, Multiply and Accumulation RAM 16KB © 2010 Renesas Electronics America Inc. All rights reserved.

RX62T Peripherals Peripheral functions
RX CPU (100 MHz) Flash up to 256KB Peripheral functions Compare Much Timer 16bit x 4 ch (CMT) General purpose 16bit interval timer for internal usage General purpose PWM timer 16bit x 4ch (GPT) Each channel has 2 PWM output Multifunction Timer Unit 16bit x 8ch (MTU3) 16 Output Compare/input capture port & 3 Input capture 2 sets of complementary 3phase output with dead time insertion 12bit AD converter: 4ch x 2Unit (1usec/ch at 5v) Up to 3ch simultaneous sampling function are supported 6 Op Amp, 6Comparator 10bit x AD converter: 12ch x 1Unit (1usec/c at 5v) FPU Data Flash 8KB (30k times E/W) Multiplier, Divider, Multiply and Accumulation RAM 16KB 16-bit timer x 4ch(CMT) Internal Purpose GPT 1ph, PWM with dead time Inverter control,PFC etc 1ph, PWM with dead time Inverter control,PFC etc 1ph, PWM with dead time Inverter control,PFC etc 1ph, PWM with dead time Inverter control,PFC etc 10bit AD 12ch Self diagnostic MTU3 12bit AD 4cht Self diagnostic 3 OpAmp 3 comp 3ph. PWM with dead time (Use two 16-bit timer ch3&4) 3ph. PWM with dead time (Use two 16-bit timer ch6&7) 12bit AD 4cht Self diagnostic 3 OpAmp 3 comp 1 or 2 Encoder Input (Use 1or2 16-bit timer ch1/2) Hall sensor / BEMF Input (Use one 16-bit timer ch0) Dead time compensation (Use one 16-bit timer ch5) © 2010 Renesas Electronics America Inc. All rights reserved.

RX62T Peripherals Peripheral functions
RX CPU (100 MHz) Flash up to 256KB Peripheral functions Watch Dog and independent Watch Dog Timer Serial Interface UART/Clock synchronous serial x 3Unit SPI x 1 Unit , LIN I/F x 1Unit, I2C bus I/F 1 Unit CAN I/F 1unit(Option) Safety functions CRC,Output port monitor, Independent WDT, Clock Stop Detection Shut Down function for 3ph PWM output(POE) Others Data Transfer Controller(DTC) POR（Power On Reset), LVD (Low Voltage Detect) On chip oscillator 125KHz±10% for independent WDT FPU Data Flash 8KB (30k times E/W) Multiplier, Divider, Multiply and Accumulation RAM 16KB CRC SCI x3ch/ SPI x 1ch I2C x 1ch/LIN x 1ch (CAN x 1ch) Option 16-bit timer x 4ch(CMT) Internal Purpose GPT Data Transfer Controller (DTC) 1ph, PWM with dead time Inverter control,PFC etc POR.LVD 1ph, PWM with dead time Inverter control,PFC etc Independent WDT (Internal dedicated clock 125kHz) 1ph, PWM with dead time Inverter control,PFC etc WDT 1ph, PWM with dead time Inverter control,PFC etc 10bit AD 12ch Self diagnostic MTU3 12bit AD 4cht Self diagnostic 3 OpAmp 3 comp 3ph. PWM with dead time (Use two 16-bit timer ch3&4) 3ph. PWM with dead time (Use two 16-bit timer ch6&7) 12bit AD 4cht Self diagnostic 3 OpAmp 3 comp 1 or 2 Encoder Input (Use 1or2 16-bit timer ch1/2) Hall sensor / BEMF Input (Use one 16-bit timer ch0) Protection - External input (POE) Clock stop detection Clock monitoring Dead time compensation (Use one 16-bit timer ch5) © 2010 Renesas Electronics America Inc. All rights reserved.

Features of MTU3 (compared with MTU2 & MTU2S
MTU3 is able to control two motors MTU3 (100MHz) Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 PWM(Output compare), Input Capture, buffer operation Compatible PWM(Output compare), Input Capture , Encoder count mode, Two 16bit or One 32bit counter MTU2 (50MHz) Compatible PWM(Output compare), Input Capture, buffer operation 3p. PWM for motor control with single buffer Improved function Double buffer for PWM duty Input capture, Pulse wide measurement for dead time compensation Compatible Ch3 Ch4 Ch5 Ch6 Ch7 MTU2S (100MHz) PWM(Output compare), Input Capture, buffer operation 3p. PWM for motor control with single buffer Improved function Double buffer for PWM duty Same with ch5 of MTU2 Duty setting MTU 2S Complementary PWM with Single buffer 50MHz resolution with every carrier duty setting MTU 3 Complementary PWM with Single buffer 100MHz resolution With every half carrier duty setting (CPU load is higher) 100MHz resolution With every carrier duty setting (CPU load is lower than previous) © 2010 Renesas Electronics America Inc. All rights reserved.

Wait Cycle Delays When there is no wait, the pipeline continues to operate at its efficiency When there is a ‘wait’ in memory access, it impacts ‘fetch’ operation for sure, and then for some instructions it creates additional pipeline stalls as shown in second figure This is the reason why performance slope changes. no wait 1 wait cycle D E M WB IF W S 1 wait cycle D E M WB IF W © 2010 Renesas Electronics America Inc. All rights reserved.

ID 620C: Complete Motor Control Integration with Rx62T

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