2. IBM ® Systems and Technology Group (STG) © Copyright International Business Machines Corporation 2008-2009. Additions to z/Architecture in the IBM System z10 Enterprise Class Dan Greiner dgreiner@us.ibm.com z/Server Architecture SHARE 112 Session 1291 26 August 2009

3. SHARE 113, Session 12912 Topics du Jour  CPU facilities added in the System z10 EC ►General-Instructions Extension FacilityGeneral-Instructions Extension Facility ►Execute-Extension FacilityExecute-Extension Facility ►Parsing-Enhancement FacilityParsing-Enhancement Facility ►Compare-and-Swap-and-Store Facility 2Compare-and-Swap-and-Store Facility 2 ►Message-Security-Assist ExtensionsMessage-Security-Assist Extensions ►Enhanced-DAT FacilityEnhanced-DAT Facility ►Configuration-Topology FacilityConfiguration-Topology Facility ►Decimal Floating Point (DFP) Facility in Hardware ►Set-Program-Parameters and CPU-Measurement FacilitiesSet-Program-Parameters and CPU-Measurement Facilities  Facility Indications Facility Indications  Why the new facilities were implemented  Only CPU facilities discussed, not I/O

4. SHARE 113, Session 12913 General Instructions Extension Facility  Instruction categories: ►Cache cognizanceCache cognizance ►Compare [logical] [immediate] and branch [relative]Compare [logical] [immediate] and branch [relative] ►Compare [logical] [immediate] and trapCompare [logical] [immediate] and trap ►Immediate second-operand fieldImmediate second-operand field ►Relative-long second operandRelative-long second operand ►Rotate then {AND | OR | XOR | Insert} selected bitsRotate then {AND | OR | XOR | Insert} selected bits ►MiscellanyMiscellany  Primary motivation: PERFORMANCE! PERFORMANCE! Index

5. SHARE 113, Session 12914 General-Instructions Extension Facility: Cache Cognizance Instructions Instruction Mne- monic Op- Code First OperandSecond Operand LocationSizeLocationSize EXTRACT CACHE ATTRIBUTE ECAGEB4CRegister64S(20)N/A PREFETCH DATA PFDE336Mask16S(20)MD PREFETCH DATA RELATIVE LONG PFDRLC62Mask16RLMD Explanation: N/ANot applicable MDModel Dependent RLRelative-long operand; 32-bit immediate value, multiplied by two and added to the current instruction address, provides the storage location of the operand S(20)Storage operand addressed using base, index, and 20-bit signed displacement. Index

6. SHARE 113, Session 12915 EXTRACT CACHE ATTRIBUTE (ECAG) EBB2B2 R1R1 ECAGR 1,R 3,D 2 (B 2 ) [RSY] DL 2 DH 2 4C Condition Code is Unchanged R3R3 Selected bits of 2 nd -operand address form a code: Bits 56-59: Attribute Indication: 0 – Extract topology summary (for up to 8 levels) 1 – Extract line size of cache in bytes. 2 – Extract total cache size in bytes. 3 – Extract set-associativity level. 4:15 – Reserved Bits 60-62: Level indication of cache. Bit 63: Type indication (0=data, 1=instruction) Result placed in R 1.0-63 R1R1 Topology Summary in R 1 (one byte per cache level): Bit 0-3:Reserved, stored as zeros Bits 4-5:Cache scope, as follows: 00 – Cache level does not exist 01 – Cache is private to the CPU 10 – Cache may be shared 11 – Reserved Bits 6-7:Cache type, as follows: 00 – Separate instr. & data caches 01 – Only instruction cache 10 – Only data cache 11 – Unified instruction & data cache Index

7. SHARE 113, Session 12916 PREFETCH DATA (PFD) E3B2B2 M1M1 PFDM 1,D 2 (X 2,B 2 ) [RXY] DL 2 DH 2 36X2X2 Condition Code is Unchanged Storage Location Code: 1 - Prefetch for fetch 2 - Prefetch for store 6 - Release cache line from store, retain for fetch. 7 - Release cache line All other codes reserved; reserved codes act as no-op Index

8. SHARE 113, Session 12917 PREFETCH DATA RELATIVE LONG (PFDRL) C6M1M1 2I2I2 PFDRLM 1,I 2 [RIL] Current Instruction Address + x2 Condition Code is Unchanged Storage LocationCodes same as PFD Index

9. SHARE 113, Session 12918 General-Instructions Extension Facility: Compare [Logical] [Immediate] and Branch [Relative] Instruction Mne- monic Op- Code First OperandSecond Operand Branch Location LocationSizeLocationSize COMPARE AND BRANCH CRBECF6Register32Register32S(12) COMPARE AND BRANCH CGRBECE4Register64Register64S(12) COMPARE AND BRANCH RELATIVE CRJEC76Register32Register32Relative COMPARE AND BRANCH RELATIVE CGRJEC64Register64Register64Relative COMPARE IMMEDIATE AND BRANCH CIBECFERegister32Immediate8S(12) COMPARE IMMEDIATE AND BRANCH CGIBECFCRegister64Immediate8S(12) COMPARE IMMEDIATE AND BRANCH RELATIVE CIJEC7ERegister32Immediate8Relative COMPARE IMMEDIATE AND BRANCH RELATIVE CGIJEC7CRegister64Immediate8Relative COMPARE LOGICAL AND BRANCH CLRBECF7Register32Register32S(12) COMPARE LOGICAL AND BRANCH CLGRBECE5Register64Register64S(12) COMPARE LOGICAL AND BRANCH RELATIVE CLRJEC77Register32Register32Relative COMPARE LOGICAL AND BRANCH RELATIVE CLGRJEC65Register64Register64Relative COMPARE LOGICAL IMMEDIATE AND BRANCH CLIBECFFRegister32Immediate8S(12) COMPARE LOGICAL IMMEDIATE AND BRANCH CLGIBECFDRegister64Immediate8S(12) COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE CLIJEC7FRegister32Immediate8Relative COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE CLGIJEC7DRegister64Immediate8Relative Index S(12)Storage operand addressed using base, index, and 12-bit unsigned displacement.

10. SHARE 113, Session 12919 COMPARE AND BRANCH (CRB) (32-bit register signed operands, storage-designated branch) M 3 Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- ECB4B4 CRBR 1,R 2,M 3,D 4 (B 4 ) [RRS] D4D4 F6R1R1 R2R2 M3M3 //// R 1.32-63//////// //////// R1R1 R 2.32-63//////// //////// R2R2 New PSW Instruction Address Condition Code is Unchanged ? M 3 TRUE ? Index

11. SHARE 113, Session 129110 COMPARE AND BRANCH (CGRB) (64-bit register signed operands, storage-designated branch) ECB4B4 CGRBR 1,R 2,M 3,D 4 (B 4 ) [RRS] D4D4 E4R1R1 R2R2 M3M3 //// R 1.0-63 R1R1 Condition Code is Unchanged R 2.0-63 R2R2 New PSW Instruction Address ? M 3 TRUE ? M 3 Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- Index

12. SHARE 113, Session 129111 COMPARE AND BRANCH RELATIVE (CRJ) (32-bit register signed operands, relative-immediate-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CRJR 1,R 2,M 3,I 4 [RIE] I4I4 76R1R1 R2R2 M3M3 //// R 1.32-63//////// //////// R1R1 R 2.32-63//////// //////// R2R2 Current Instruction Address Condition Code is Unchanged + New PSW Instruction Address x2 ? M 3 TRUE ? Index

13. SHARE 113, Session 129112 COMPARE AND BRANCH RELATIVE (CGRJ) (64-bit register signed operands, relative-immediate-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CGRJR 1,R 2,M 3,I 4 [RIE] 64R1R1 R2R2 M3M3 //// R 1.0-63 R1R1 Condition Code is Unchanged R 2.0-63 R2R2 Current Instruction Address + New PSW Instruction Address x2 I4I4 ? M 3 TRUE ? Index

14. SHARE 113, Session 129113 COMPARE IMMEDIATE AND BRANCH (CIB) (32-bit register, 8-bit immediate, signed operands; storage-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- ECB4B4 CIBR 1,I 2,M 3,D 4 (B 4 ) [RIS] D4D4 FER1R1 M3M3 I2I2 I2I2 SSSSSSSSSSSSS NEW PSW Instruction Address Condition Code is Unchanged ? M 3 TRUE ? R 1.32-63//////// //////// R1R1 Index

15. SHARE 113, Session 129114 COMPARE IMMEDIATE AND BRANCH (CGIB) (64-bit register, 8-bit immediate, signed operands; storage-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- ECB4B4 CGIBR 1,I 2,M 3,D 4 (B 4 ) [RIS] D4D4 FCR1R1 M3M3 I2I2 New PSW Instruction Address Condition Code is Unchanged ? M 3 TRUE ? I2I2 SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSR 1.0-63 R1R1 Index

16. SHARE 113, Session 129115 COMPARE IMMEDIATE AND BRANCH RELATIVE (CIJ) (32-bit register, 8-bit immediate, signed operands; relative-immediate-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CIJR 1,I 2,M 3,I 4 [RIE] I4I4 7ER1R1 M3M3 I2I2 I2I2 SSSSSSSSSSSSS Condition Code is Unchanged ? M 3 TRUE ? R 1.32-63//////// //////// R1R1 Current Instruction Address + New PSW Instruction Address x2 Index

17. SHARE 113, Session 129116 COMPARE IMMEDIATE AND BRANCH RELATIVE (CGIJ) (64-bit register, 8-bit immediate, signed operands; relative-immediate-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CGIJR 1,I 2,M 3,I 4 [RIE] 7CR1R1 M3M3 I2I2 Condition Code is Unchanged ? M 3 TRUE ? I2I2 SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSR 1.0-63 R1R1 Current Instruction Address + New PSW Instruction Address x2 I4I4 Index

18. SHARE 113, Session 129117 COMPARE LOGICAL AND BRANCH (CLRB) (32-bit register unsigned operands; storage-designated branch) M 3 Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- ECB4B4 CLRBR 1,R 2,M 3,D 4 (B 4 ) [RRS] D4D4 F7R1R1 R2R2 M3M3 //// R 1.32-63//////// //////// R1R1 R 2.32-63//////// //////// R2R2 New PSW Instruction Address Condition Code is Unchanged ? M 3 TRUE ? Index

19. SHARE 113, Session 129118 COMPARE LOGICAL AND BRANCH (CLGRB) (64-bit register unsigned operands; storage-designated branch) ECB4B4 CLGRBR 1,R 2,M 3,D 4 (B 4 ) [RRS] D4D4 E5R1R1 R2R2 M3M3 //// R 1.0-63 R1R1 Condition Code is Unchanged R 2.0-63 R2R2 New PSW Instruction Address ? M 3 TRUE ? M 3 Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- Index

20. SHARE 113, Session 129119 COMPARE LOGICAL AND BRANCH RELATIVE (CLRJ) (32-bit register unsigned operands; relative-immediate-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CLRJR 1,R 2,M 3,I 4 [RIE] I4I4 77R1R1 R2R2 M3M3 //// R 1.32-63//////// //////// R1R1 R 2.32-63//////// //////// R2R2 Current Instruction Address Condition Code is Unchanged + New PSW Instruction Address x2 ? M 3 TRUE ? Index

21. SHARE 113, Session 129120 COMPARE LOGICAL AND BRANCH RELATIVE (CLGRJ) (64-bit register unsigned operands; relative-immediate-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CLGRJR 1,R 2,M 3,I 4 [RIE] 65R1R1 R2R2 M3M3 //// R 1.0-63 R1R1 Condition Code is Unchanged R 2.0-63 R2R2 Current Instruction Address + New PSW Instruction Address x2 I4I4 ? M 3 TRUE ? Index

22. SHARE 113, Session 129121 COMPARE LOGICAL IMMEDIATE AND BRANCH (CLIB) (32-bit register, 8-bit immediate, unsigned operands; storage-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- ECB4B4 CLIBR 1,I 2,M 3,D 4 (B 4 ) [RIS] D4D4 FFR1R1 M3M3 I2I2 I2I2 0000000000000000 New PSW Instruction Address Condition Code is Unchanged ? M 3 TRUE ? R 1.32-63//////// //////// R1R1 Index

23. SHARE 113, Session 129122 COMPARE LOGICAL IMMEDIATE AND BRANCH (CLGIB) (64-bit register, 8-bit immediate, unsigned operands; storage-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- ECB4B4 CLGIBR 1,I 2,M 3,D 4 (B 4 ) [RIS] D4D4 FDR1R1 M3M3 I2I2 New PSW Instruction Address Condition Code is Unchanged ? M 3 TRUE ? I2I2 0000000000000000000000000000000000000R 1.0-63 R1R1 Index

24. SHARE 113, Session 129123 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (CLIJ) (32-bit register, 8-bit immediate, unsigned operands; relative-immediate-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CLIJR 1,I 2,M 3,I 4 [RIE] I4I4 7FR1R1 M3M3 I2I2 I2I2 0000000000000000 Condition Code is Unchanged ? M 3 TRUE ? R 1.32-63//////// //////// R1R1 Current Instruction Address + New PSW Instruction Address x2 Index

25. SHARE 113, Session 129124 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (CLGIJ) (64-bit register, 8-bit immediate, unsigned operands; relative-immediate-designated branch) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CLGIJR 1,I 2,M 3,I 4 [RIE] 7DR1R1 M3M3 I2I2 Condition Code is Unchanged ? M 3 TRUE ? I2I2 0000000000000000000000000000000000000R 1.0-63 R1R1 Current Instruction Address + New PSW Instruction Address x2 I4I4 Index

26. SHARE 113, Session 129125 General-Instructions Extension Facility: Compare [Logical] [Immediate] and Trap Instruction Mne- monic Op- Code First OperandSecond Operand LocationSizeLocationSize COMPARE AND TRAP CRTB972Register32Register32 COMPARE AND TRAP CGRTB960Register64Register64 COMPARE IMMEDIATE AND TRAP CITEC72Register32Immediate16 COMPARE IMMEDIATE AND TRAP CGITEC70Register64Immediate16 COMPARE LOGICAL AND TRAP CLRTB973Register32Register32 COMPARE LOGICAL AND TRAP CLGRTB961Register64Register64 COMPARE LOGICAL IMMEDIATE AND TRAP CLFITEC73Register32Immediate16 COMPARE LOGICAL IMMEDIATE AND TRAP CLGITEC71Register64Immediate16 Index

27. SHARE 113, Session 129126 COMPARE AND TRAP (CRT) (32-bit register signed operands) M 3 Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- B972 CRT R 1,R 2,M 3 [RRF] R1R1 R2R2 M3M3 //// R 1.32-63//////// //////// R1R1 R 2.32-63//////// //////// R2R2 Condition Code is Unchanged ? M 3 TRUE ? Data Exception Program Interruption (DXC = FF hex) Index

28. SHARE 113, Session 129127 COMPARE AND TRAP (CGRT) (64-bit register signed operands) M 3 Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- B960 CGRT R 1,R 2,M 3 [RRF] R1R1 R2R2 M3M3 //// Condition Code is Unchanged ? M 3 TRUE ? Data Exception Program Interruption (DXC = FF hex) R 1.0-63 R1R1 R 2.0-63 R2R2 Index

29. SHARE 113, Session 129128 COMPARE IMMEDIATE AND TRAP (CIT) (32-bit register, 16-bit immediate, signed operands) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CITR 1,I 2,M 3 [RIE] I2I2 72R1R1 ////M3M3 R 1.32-63//////// //////// R1R1 Condition Code is Unchanged ? M 3 TRUE ? I2I2 SSSSSSSS Data Exception Program Interruption (DXC = FF hex) Index

30. SHARE 113, Session 129129 COMPARE IMMEDIATE AND TRAP (CGIT) (64-bit register, 16-bit immediate, signed operands) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CGITR 1,I 2,M 3 [RIE] I2I2 70R1R1 ////M3M3 Condition Code is Unchanged ? M 3 TRUE ? Data Exception Program Interruption (DXC = FF hex) R 1.0-63 R1R1 I2I2 SSSSSSSSSSSSSSSSSSSSSSSSSS Index

31. SHARE 113, Session 129130 COMPARE LOGICAL AND TRAP (CLRT) (32-bit register unsigned operands) M 3 Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- B973 CLRT R 1,R 2,M 3 [RRF] R1R1 R2R2 M3M3 //// R 1.32-63//////// //////// R1R1 R 2.32-63//////// //////// R2R2 Condition Code is Unchanged ? M 3 TRUE ? Data Exception Program Interruption (DXC = FF hex) Index

32. SHARE 113, Session 129131 COMPARE LOGICAL AND TRAP (CLGRT) (64-bit register unsigned operands) M 3 Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- B961 CLGRT R 1,R 2,M 3 [RRF] R1R1 R2R2 M3M3 //// Condition Code is Unchanged ? M 3 TRUE ? Data Exception Program Interruption (DXC = FF hex) R 1.0-63 R1R1 R 2.0-63 R2R2 Index

33. SHARE 113, Session 129132 COMPARE LOGICAL IMMEDIATE AND TRAP (CLFIT) (32-bit register, 16-bit immediate, unsigned operands) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CLFITR 1,I 2,M 3 [RIE] I2I2 73R1R1 ////M3M3 R 1.32-63//////// //////// R1R1 Condition Code is Unchanged ? M 3 TRUE ? I2I2 0000000000 Data Exception Program Interruption (DXC = FF hex) Index

34. SHARE 113, Session 129133 COMPARE LOGICAL IMMEDIATE AND TRAP (CLGIT) (64-bit register, 16-bit immediate, unsigned operands) Mask Bit Values: 0 Equal 1 First operand low 2 First operand high 3 -- EC CLGITR 1,I 2,M 3 [RIE] I2I2 71R1R1 ////M3M3 Condition Code is Unchanged ? M 3 TRUE ? Data Exception Program Interruption (DXC = FF hex) R 1.0-63 R1R1 I2I2 00000000000000000000000000000000 Index

35. SHARE 113, Session 129134 General-Instructions Extension Facility: Immediate Second-Operand Instructions Instruction Mne- monic Op- Code First OperandSecond Operand LocationSizeSignLocationSizeSign ADD IMMEDIATEASIEB6AS(20)32SImmediate8S ADD IMMEDIATEAGSIEB7AS(20)64SImmediate8S ADD LOGICAL WITH SIGNED IMMEDIATEALSIEB6ES(20)32UImmediate8S ADD LOGICAL WITH SIGNED IMMEDIATEALGSIEB7ES(20)64UImmediate8S COMPARE HALFWORD IMMEDIATECHHSIE554S(12)16SImmediate16S COMPARE HALFWORD IMMEDIATECHSIE55CS(12)32SImmediate16S COMPARE HALFWORD IMMEDIATECGHSIE558S(12)64SImmediate16S COMPARE LOGICAL IMMEDIATECLHHSIE555S(12)16UImmediate16U COMPARE LOGICAL IMMEDIATECLFHSIE55DS(12)32UImmediate16U COMPARE LOGICAL IMMEDIATECLGHSIE556S(12)64UImmediate16U MOVE [IMMEDIATE]MVHHIE544S(12)16SImmediate16S MOVE [IMMEDIATE]MVHIE54CS(12)32SImmediate16S MOVE [IMMEDIATE]MVGHIE548S(12)64SImmediate16S MULTIPLY SINGLE IMMEDIATEMSFIC21Register32SImmediate32S MULTIPLY SINGLE IMMEDIATEMSGFIC20Register64SImmediate32S Index

36. SHARE 113, Session 129135 ADD IMMEDIATE (ASI) (32-bit storage and 8-bit immediate, signed operands) Resulting Condition Code: 0 Result zero; no overflow 1 Result less than zero; no overflow 2 Result greater than zero; no overflow 3 Overflow EBB1B1 I2I2 ASID 1 (B 1 ),I 2 [SIY] DL 1 DH 2 6A 32-Bit Signed Value (in storage) + SSSSSSSSSSSSSI2I2 Index

37. SHARE 113, Session 129136 ADD IMMEDIATE (AGSI) (64-bit storage and 8-bit immediate, signed operands) Resulting Condition Code: 0 Result zero; no overflow 1 Result less than zero; no overflow 2 Result greater than zero; no overflow 3 Overflow AGSID 1 (B 1 ),I 2 [SIY] EBB1B1 I2I2 DL 1 DH 2 7A 64-Bit Signed Value (in storage) SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSI2I2 + Index

38. SHARE 113, Session 129137 ADD LOGICAL WITH SIGNED IMMEDIATE (ALSI) (32-bit unsigned storage and 8-bit signed immediate operands) EBB1B1 I2I2 ALSID 1 (B 1 ),I 2 [SIY] DL 1 DH 2 6E 32-Bit Unsigned Value (in storage) + SSSSSSSSSSSSSI2I2 Resulting Condition Code: 0 Result zero; no carry 1 Result not zero; no carry 2 Result zero; carry 3 Result not zero; carry (when I 2 is negative) 0 -- 1 Result not zero; borrow 2 Result zero; no borrow 3 Result not zero; no borrow Index

39. SHARE 113, Session 129138 ADD LOGICAL WITH SIGNED IMMEDIATE (ALGSI) (64-bit unsigned storage and 8-bit signed immediate operands) Resulting Condition Code: 0 Result zero; no carry 1 Result not zero; no carry 2 Result zero; carry 3 Result not zero; carry (when I 2 is negative) 0 -- 1 Result not zero; borrow 2 Result zero; no borrow 3 Result not zero; no borrow ALGSID 1 (B 1 ),I 2 [SIY] EBB1B1 I2I2 DL 1 DH 2 7E 64-Bit Unsigned Value (in storage) SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSI2I2 + Index

40. SHARE 113, Session 129139 COMPARE HALFWORD IMMEDIATE (CHHSI) (16-bit storage, 16-bit immediate, signed operands) E554B1B1 CHHSID 1 (B 1 ),I 2 [SIL] D1D1 I2I2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- 16-bit Signed (storage) ? Index

41. SHARE 113, Session 129140 COMPARE HALFWORD IMMEDIATE (CHSI) (32-bit storage, 16-bit immediate, signed operands) E55CB1B1 CHSID 1 (B 1 ),I 2 [SIL] D1D1 I2I2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- 32-bit Signed (storage) ? I2I2 SSSSSSSS Index

42. SHARE 113, Session 129141 COMPARE HALFWORD IMMEDIATE (CGHSI) (64-bit storage, 16-bit immediate, signed operands) E558B1B1 CGHSID 1 (B 1 ),I 2 [SIL] D1D1 I2I2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- 64-bit Signed (storage) ? I2I2 SSSSSSSSSSSSSSSSSSSSSSSSSSS Index

43. SHARE 113, Session 129142 COMPARE LOGICAL IMMEDIATE (CLHHSI) (16-bit storage, 16-bit immediate, unsigned operands) E555B1B1 CLHHSID 1 (B 1 ),I 2 [SIL] D1D1 I2I2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- 16-bit Unsigned (storage) ? Index

44. SHARE 113, Session 129143 COMPARE LOGICAL IMMEDIATE (CLFHSI) (32-bit storage, 16-bit immediate, unsigned operands) E55DB1B1 CLFHSID 1 (B 1 ),I 2 [SIL] D1D1 I2I2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- 32-bit Unsigned (stg.) ? I2I2 0000000000 Index

45. SHARE 113, Session 129144 COMPARE LOGICAL IMMEDIATE (CLGHSI) (64-bit storage, 16-bit immediate, unsigned operands) E559B1B1 CLGHSID 1 (B 1 ),I 2 [SIL] D1D1 I2I2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- 64-bit Unsigned (storage) ? I2I2 00000000000000000000000000000000 Index

46. SHARE 113, Session 129145 MOVE (MVHHI) (16-bit storage, 16-bit immediate, signed operands) E544B1B1 MVHHID 1 (B 2 ),I 2 [SIL] D1D1 I2I2 16-bit (storage) Condition Code is Unchanged Index

47. SHARE 113, Session 129146 MOVE (MVHI) (32-bit storage, 16-bit immediate, signed operands) E54CB1B1 MVHID 1 (B 2 ),I 2 [SIL] D1D1 I2I2 16-Bit ValueSSSSSSSS Condition Code is Unchanged 32-bit Signed (storage) Index

48. SHARE 113, Session 129147 MOVE (MVGHI) (64-bit storage, 16-bit immediate, signed operands) E548B1B1 MVGHID 1 (B 2 ),I 2 [SIL] D1D1 I2I2 16-Bit ValueSSSSSSSSSSSSSSSSSSSSSSSSSS Condition Code is Unchanged 64-bit Signed (storage) Index

49. SHARE 113, Session 129148 MULTIPLY SINGLE IMMEDIATE (MSFI) (32-bit register multiplicand, 32-bit immediate multiplier, 32-bit register product) 32-Bit (multiplier) R 1.32-63 (product)//////// //////// R1R1 Condition Code is Unchanged R 1.32-63 (multiplicand)//////// //////// R1R1 X C2R1R1 1I2I2 MSFIR 1,I 2 [RIL] Index

50. SHARE 113, Session 129149 MULTIPLY SINGLE IMMEDIATE (MSGFI) (64-bit register multiplicand, 32-bit immediate multiplier, 64-bit register product) 32-Bit (multiplier) Condition Code is Unchanged X C2R1R1 0I2I2 MSGFIR 1,I 2 [RIL] R 1.0-63 (multiplicand) R1R1 R 1.0-63 (product) R1R1 Index

51. SHARE 113, Session 129150 General-Instructions Extension Facility: Relative-Long Second Operands (1 of 2) Instruction Mne- monic Op- Code First OperandSecond Operand LocationSizeLocationSize ‡ COMPARE RELATIVE LONG CRLC6DRegister32RL32 COMPARE RELATIVE LONG CGFRLC6CRegister64RL32 COMPARE RELATIVE LONG CGRLC68Register64RL64 COMPARE HALFWORD RELATIVE LONG CHRLC65Register32RL16 COMPARE HALFWORD RELATIVE LONG CGHRLC64Register64RL16 COMPARE LOGICAL RELATIVE LONG CLRLC6FRegister32RL32 COMPARE LOGICAL RELATIVE LONG CLGFRLC6ERegister64RL32 COMPARE LOGICAL RELATIVE LONG CLGRLC6ARegister64RL64 COMPARE LOGICAL RELATIVE LONG CLHRLC67Register32RL16 COMPARE LOGICAL RELATIVE LONG CLGHRLC66Register64RL16 Index Explanation: ‡ Operand must be aligned on an integral boundary; otherwise, a specification exception is recognized! RLRelative-long operand; 32-bit immediate value, multiplied by two and added to the current instruction address, provides the storage location of the operand

52. SHARE 113, Session 129151 General-Instructions Extension Facility: Relative-Long Second Operands (2 of 2) Instruction Mne- monic Op- Code First OperandSecond Operand LocationSizeLocationSize ‡ LOAD RELATIVE LONG LRLC4DRegister32RL32 LOAD RELATIVE LONG LGFRLC4CRegister64RL32 LOAD RELATIVE LONG LGRLC48Register64RL64 LOAD HALFWORD RELATIVE LONG LHRLC45Register32RL16 LOAD HALFWORD RELATIVE LONG LGHRLC44Register64RL16 LOAD LOGICAL RELATIVE LONG LLGFRLC4ERegister64RL32 LOAD LOGICAL HALFWORD RELATIVE LONG LLHRLC42Register32RL16 LOAD LOGICAL HALFWORD RELATIVE LONG LLGHRLC46Register64RL16 STORE RELATIVE LONG STRLC4FRegister32RL32 STORE RELATIVE LONG STGRLC4BRegister64RL64 STORE HALFWORD RELATIVE LONG STHRL C47Register16RL16 Index Explanation: ‡ Operand must be aligned on an integral boundary; otherwise, a specification exception is recognized! RLRelative-long operand; 32-bit immediate value, multiplied by two and added to the current instruction address, provides the storage location of the operand

53. SHARE 113, Session 129152 COMPARE RELATIVE LONG (CRL) (32-bit register and 32-bit relative-immediate, signed operands) C6R1R1 DI2I2 CRLR 1,I 2 [RIL] Signed Word (storage) Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- Current Instruction Address R 1.32-63//////// //////// R1R1 + x2 ? Index

54. SHARE 113, Session 129153 COMPARE RELATIVE LONG (CGFRL) (64-bit register and 32-bit relative-immediate, signed operands) C6R1R1 CI2I2 CGFRLR 1,I 2 [RIL] Signed Word (storage) Current Instruction Address R 1.0-63 R1R1 + x2 SSSSSSSSSSSSSSSSS Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- ? Index

55. SHARE 113, Session 129154 COMPARE RELATIVE LONG (CGRL) (64-bit register and 64-bit relative-immediate, signed operands) C6R1R1 8I2I2 CGRLR 1,I 2 [RIL] Signed Doubleword (storage) Current Instruction Address R 1.0-63 R1R1 + x2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- ? Index

56. SHARE 113, Session 129155 COMPARE HALFWORD RELATIVE LONG (CHRL) (32-bit register, 16-bit relative-immediate-designated, signed operands) C6R1R1 5I2I2 CHRLR 1,I 2 [RIL] S Halfword Current Instruction Address + x2 SSSSSSSS Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- ? R 1.32-63//////// //////// R1R1 Index

57. SHARE 113, Session 129156 COMPARE HALFWORD RELATIVE LONG (CGHRL) (64-bit register, 16-bit relative-immediate-designated, signed operands) C6R1R1 4I2I2 CGHRLR 1,I 2 [RIL] Current Instruction Address + x2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- ? R 1.0-63 R1R1 S HalfwordSSSSSSSSSSSSSSSSSSSSSSSSSS Index

58. SHARE 113, Session 129157 COMPARE LOGICAL RELATIVE LONG (CLRL) (32-bit register and 32-bit relative-immediate, unsigned operands) C6R1R1 FI2I2 CLRLR 1,I 2 [RIL] Unsigned Word (storage) Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- Current Instruction Address R 1.32-63//////// //////// R1R1 + x2 ? Index

59. SHARE 113, Session 129158 COMPARE LOGICAL RELATIVE LONG (CLGFRL) (64-bit register and 32-bit relative-immediate, unsigned operands) C6R1R1 EI2I2 CLGFRLR 1,I 2 [RIL] Unsigned Word (storage) Current Instruction Address R 1.0-63 R1R1 + x2 000000000000000000000 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- ? Index

60. SHARE 113, Session 129159 COMPARE LOGICAL RELATIVE LONG (CLGRL) (64-bit register and 64-bit relative-immediate, unsigned operands) C6R1R1 AI2I2 CLGRLR 1,I 2 [RIL] Unsigned Doubleword (storage) Current Instruction Address R 1.0-63 R1R1 + x2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- ? Index

61. SHARE 113, Session 129160 COMPARE LOGICAL RELATIVE LONG (CLHRL) (32-bit register, 16-bit relative-immediate-designated, unsigned operands) C6R1R1 7I2I2 CLHRLR 1,I 2 [RIL] Current Instruction Address + x2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- ? R 1.32-63//////// //////// R1R1 U Halfword0000000000 Index

62. SHARE 113, Session 129161 COMPARE LOGICAL RELATIVE LONG (CLGHRL) (64-bit register, 16-bit relative-immediate-designated, unsigned operands) C6R1R1 6I2I2 CLGHRLR 1,I 2 [RIL] Current Instruction Address + x2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- ? R 1.0-63 R1R1 U Halfword00000000000000000000000000000000 Index

63. SHARE 113, Session 129162 LOAD RELATIVE LONG (LRL) (32-bit register and 32-bit relative-immediate operands) C4R1R1 DI2I2 LRLR 1,I 2 [RIL] Word (storage) Current Instruction Address R 1.32-63//////// //////// R1R1 + x2 Condition Code is Unchanged Index

64. SHARE 113, Session 129163 LOAD RELATIVE LONG (LGFRL) (64-bit register and 32-bit relative-immediate, signed operands) C4R1R1 CI2I2 LGFRLR 1,I 2 [RIL] Signed Word (storage) Current Instruction Address R 1.0-63 R1R1 + x2 SSSSSSSSSSSSSSSSS Condition Code is Unchanged Index

65. SHARE 113, Session 129164 LOAD RELATIVE LONG (LGRL) (64-bit register and 64-bit relative-immediate, signed operands) C4R1R1 8I2I2 LGRLR 1,I 2 [RIL] Doubleword (storage) Current Instruction Address R 1.0-63 R1R1 + x2 Condition Code is Unchanged Index

66. SHARE 113, Session 129165 LOAD HALFWORD RELATIVE LONG (LHRL) (32-bit register and 16-bit relative-immediate, signed operands) C4R1R1 5I2I2 LHRLR 1,I 2 [RIL] S Halfword Current Instruction Address + x2 SSSSSSSS Condition Code is Unchanged R 1.32-63//////// //////// R1R1 Index

67. SHARE 113, Session 129166 LOAD HALFWORD RELATIVE LONG (LGHRL) (64-bit register and 16-bit relative-immediate, signed operands) C4R1R1 4I2I2 LGHRLR 1,I 2 [RIL] S Halfword Current Instruction Address + x2 SSSSSSSSSSSSSSSSSSSSSSSSSS Condition Code is Unchanged R 1.0-63 R1R1 Index

68. SHARE 113, Session 129167 LOAD LOGICAL RELATIVE LONG (LLGFRL) (64-bit register and 32-bit relative-immediate, unsigned operands) C4R1R1 EI2I2 LLGFRLR 1,I 2 [RIL] Unsigned Word (storage) Current Instruction Address + x2 000000000000000000000 Condition Code is Unchanged R 1.0-63 R1R1 Index

69. SHARE 113, Session 129168 LOAD LOGICAL HALFWORD RELATIVE LONG (LLHRL) (32-bit register and 16-bit relative-immediate, unsigned operands) C4R1R1 2I2I2 LLHRLR 1,I 2 [RIL] U Halfword Current Instruction Address + x2 0000000000 Condition Code is Unchanged R 1.32-63//////// //////// R1R1 Index

70. SHARE 113, Session 129169 LOAD LOGICAL HALFWORD RELATIVE LONG (LLGHRL) (64-bit register and 16-bit relative-immediate, unsigned operands) C4R1R1 6I2I2 LLGHRLR 1,I 2 [RIL] U Halfword Current Instruction Address + x2 00000000000000000000000000000000 Condition Code is Unchanged R 1.0-63 R1R1 Index

71. SHARE 113, Session 129170 STORE RELATIVE LONG (STRL) (32-bit register and 32-bit relative-immediate operands) C4R1R1 FI2I2 STRLR 1,I 2 [RIL] Word (storage) Current Instruction Address R 1.32-63//////// //////// R1R1 + x2 Condition Code is Unchanged Index

72. SHARE 113, Session 129171 STORE RELATIVE LONG (STGRL) (64-bit register and 64-bit relative-immediate, signed operands) C4R1R1 BI2I2 STGRLR 1,I 2 [RIL] Doubleword (storage) Current Instruction Address R 1.0-63 R1R1 + x2 Condition Code is Unchanged Index

73. SHARE 113, Session 129172 STORE HALFWORD RELATIVE LONG (STHRL) C4R1R1 7I2I2 STHRLR 1,I 2 [RIL] Halfword (storage) Current Instruction Address R 1.48-63//////// //////// //////// R1R1 + x2 Condition Code is Unchanged Index

74. SHARE 113, Session 129173 General-Instructions Extension Facility: Rotate Then xxx Selected Bits Instruction Mne- monic Op- Code First OperandSecond Operand LocationSizeLocationSize ROTATE THEN AND SELECTED BITS RNSBGEC54Register64RegisterV ROTATE THEN EXCLUSIVE OR SELECTED BITS RXSBGEC57Register64RegisterV ROTATE THEN INSERT SELECTED BITS RISBGEC55Register64RegisterV ROTATE THEN OR SELECTED BITS ROSBGEC56Register64RegisterV Index Explanation: VVariable number of bits processed, based on I 3 and I 4 operands of the instruction.

75. SHARE 113, Session 129174 General-Instructions Extension Facility: ROTATE THEN {AND | OR | XOR} SELECTED BITS ECR1R1 R ? SBGR 1,R 2,I 3,I 4 [,I 5 ] [RIE] I5I5 5xR2R2 I4I4 I3I3 R 2.0-63 R2R2 Rotated Second Operand R 1 Bits I 3 – I 4 R1R1 Perform Logical Operation on selected Bits Resulting Condition Code: 0 Selected bits zero 1 Selected bits not zero 2 -- 3 -- MnemonicOpcodeFunction RNSBGEC-54AND ROSBGEC-56OR RXSBGEC-57Exclusive OR Index I3I3 I4I4

76. SHARE 113, Session 129175 ROTATE THEN xxx SELECTED BITS (RxSBG) (continued)  Bits 2-7 of I 5 field are the rotate amount ►Bits rotate to the left; bits that rotate out of bit zero reenter at bit 63 ►Negative amount effectively rotates to the right ►I 5 field is optional – defaults to zero if not coded  Bits 2-7 of I 3 and I 4 fields are starting- and ending-bit positions of selected bits in R 1 ►When I 3 > I 4, wrap-around occurs ►All other bits in R 1 are unmodified  Bit 0 of the I 3 field is the Test-Results Control (T) ►When T is one, only CC is set; no change to R 1 ►HLASM extended mnemonic: RxSBGT  Only the selected bits are used in determining condition code! Index

77. SHARE 113, Session 129176 ROTATE THEN INSERT SELECTED BITS (RISBG) ECR1R1 RISBGR 1,R 2,I 3,I 4 [,I 5 ] [RIE] I5I5 55R2R2 I4I4 I3I3 R 2.0-63 R2R2 Rotated Second Operand R 1 Bits I 3 – I 4 R1R1 Rotated Bits are Inserted into Selected Bits of R 1 Resulting Condition Code: 0 Result zero 1 Result less than zero 2 Result greater than zero 3 -- Remaining bits of R 1 either: Left unchanged, or Set to zero Depending on the Z control (bit 0 of the I 4 field) Index I3I3 I4I4

78. SHARE 113, Session 129177 ROTATE THEN INSERT SELECTED BITS (RISBG) (continued)  Bits 2-7 of I 5 field are rotate amount ►Bits rotate to the left; bits that rotate out of bit zero reenter at bit 63 ►Negative amount effectively rotates to the right ►I 5 field is optional – defaults to zero if not coded  Bits 2-7 of I 3 and I 4 fields are starting- and ending-bit position of selected bits in R 1 ►When I 3 > I 4, wrap-around occurs  Bit 0 of the I 4 field is the Zero-Remaining-Bits Control (Z): ►When Z is zero, remaining bits of R 1 left unchanged ►When Z is one, remaining bits of R 1 set to zero ►HLASM extended mnemonic: RISBGZ  Condition code set à la LOAD AND TEST (based on all 64 bits) Index

79. SHARE 113, Session 129178 General-Instructions Extension Facility: Miscellany Instruction Mne- monic Op- Code First OperandSecond Operand LocationSizeLocationSize COMPARE HALFWORD CGHE334Register64S(20)16 LOAD ADDRESS EXTENDED LAEYE375Register24/31/64S(20)N/A LOAD AND TEST LTGFE332Register64S(20)32 MULTIPLY MFYE35CRegister 64  32 S(20)32 MULTIPLY HALFWORD MHYE37CRegister32S(20)16 Index Explanation: N/ANot applicable S(20)Storage operand addressed using base, index, and 20-bit signed displacement.

80. SHARE 113, Session 129179 COMPARE HALFWORD (CGH) (64-bit register, 16-bit storage, signed operands) E3B2B2 R1R1 CGHR 1,D 2 (X 2,B 2 ) [RXY] DL 2 DH 2 34X2X2 Resulting Condition Code: 0 Operands equal 1 First operand low 2 First operand high 3 -- ? R 1.0-63 R1R1 16-Bit (stg)SSSSSSSSSSSSSSSSSSSSSSSSSS Index

81. SHARE 113, Session 129180 LOAD ADDRESS EXTENDED (LAEY) (long-displacement form of LAE) Bits 40-63, 31-63, or 0-63 GR R 1 Condition Code is Unchanged E3B2B2 R1R1 LAEYR 1,D 2 (X 2,B 2 ) [RXY] DL 2 DH 2 75X2X2 ALET AR R 1 00000000 00 00000000 or AR B 2 01 00000001 10 00000002 11 PSW Bits 16-17 Index

82. SHARE 113, Session 129181 LOAD AND TEST (LTGF) (64-bit register, 32-bit storage, signed operands) E3B2B2 R1R1 LTGFR 1,D 2 (X 2,B 2 ) [RXY] DL 2 DH 2 32X2X2 32-Bit Signed ValueSSSSSSSSSSSSSSSSS Resulting Condition Code: 0 Result zero 1 Result less than zero 2 Result greater than zero 3 -- R 1.0-63 R1R1 Index

83. SHARE 113, Session 129182 MULTIPLY (MFY) (32-bit register multiplicand, 32-bit storage multiplier, 64-bit even/odd register product) E3B2B2 R1R1 MFYR 1,D 2 (X 2,B 2 ) [RXY] DL 2 DH 2 5CX2X2 32-Bit (multiplier) R 1.32-63 (product)//////// //////// R1R1 R 1 +1.32-63 (product)//////// //////// R 1 +1 Condition Code is Unchanged R 1.32-63 (multiplicand)//////// //////// R1R1 X Index

84. SHARE 113, Session 129183 MULTIPLY HALFWORD (MHY) (32-bit register multiplicand, 16-bit storage multiplier, 32-bit register product) E3B2B2 R1R1 MHYR 1,D 2 (X 2,B 2 ) [RXY] DL 2 DH 2 7CX2X2 16-Bit (mult) R 1.32-63 (product)//////// //////// R1R1 Condition Code is Unchanged R 1.32-63 (multiplicand)//////// //////// R1R1 X Index

85. SHARE 113, Session 129184 Execute-Extensions Facility:  Provides EXECUTE RELATIVE LONG (EXRL) C6R1R1 0I2I2 EXRLD 1 (B 1 ),I 2 [RIL] 2-, 4-, or 6-Byte Instruction in Storage Current Instruction Address + x2 Condition Code set by Executed Instruction 56-63//////// //////// //////// //////// //////// //////// //////// R1R1 OR When R 1 field is not zero, bits 56-63 of the general register R 1 are ORed with bits 8-15 of the target instruction. Index

86. SHARE 113, Session 129185 Execute-Extensions Facility (2):  With EXECUTE (EX), interruption-length code is always 4 ►Regardless of the length of the executed instruction  With EXECUTE RELATIVE LONG (EXRL), the interruption- length code is always 6! Index

87. SHARE 113, Session 129186 Parsing-Enhancement Facility:  Two instructions provide enhanced translate-and-test function ►Left-to-right (TRTE) or right-to-left (TRTRE) processing ►One-byte or two-byte argument characters –Useful for Unicode or other DBCS support ►One-byte or two-byte function-code table ►Length specified in a register – no EXECUTE required! ►Abbreviated function-code table option for 2-byte argument characters –Don’t need 64K or 128K table for certain 2-byte argument- character scanning Index

88. SHARE 113, Session 129187 Parsing-Enhancement Facility: TRANSLATE AND TEST EXTENDED (TRTE) TRANSLATE AND TEST REVERSE EXTENDED (TRTRE) B9BF TRTE R 1,R 2 [,M 3 ] [RRF] R1R1 R2R2 M3M3 //// Pointer to Argument-Characters R1R1 Length of Argument-Characters (in bytes) R 1 +1 Pointer to Function-Code Table GR1 //////// //////// //////// R2R2 Func Code M 3 Bit Positions: 0 – Argument-Character Control (A) 0 = one-byte argument characters 1 = two-byte argument characters 1 – Function-Code Control (F) 0 = one-byte function codes 1 = two-byte function codes 2 – Argument-Character Limit (L) 0 = unlimited argument characters 1 = argument character > 255 assumed to be zero 3 – Reserved B9BD TRTRE R 1,R 2 [,M 3 ] [RRF] R1R1 R2R2 M3M3 //// Index Resulting Condition Code: 0 Entire 1 st operand processed w/o selecting nonzero function code 1 Nonzero function code selected 2 -- 3 CPU-determined timeout

89. SHARE 113, Session 129188 Parsing Enhancement Facility:  TRTE scans left to right  TRTRE scans right to left ►First-operand argument character used as index into function-code table. ►If function-code table entry is zero, continue with next argument character (incrementing R 1 and decrementing R 1 +1 by argument-character size) ►If function-code table entry is nonzero, return its value in bits 56-63 or 48-63 of R 2 (depending on setting of F bit)  Argument-Character Limit (L) bit allows scanning of 2-byte argument characters with an abbreviated (256 entry) function-code table. ►For most 2-byte character sets, the common delimiting characters (E.g., comma, period, parentheses, mathematical symbols, &c.) are in the first 256 positions of the function-code table ►Uninteresting characters (i.e., > 256) are assumed to have a function code of zero, without actually accessing function-code table. Index

90. SHARE 113, Session 129189 Compare-and-Swap-and-Store Facility 2: C8B1B1 R3R3 CSSTD 1 (B 1 ),D 2 (B 2 ),R 3 [SSF] D1D1 B2B2 D2D2 2 ? R 3.32-63 (FC=0), R 3.0-63 (FC=1) R3R3 4, 8, or 16 bytes in storage R 3.0-63 and R 3 +1.0-63 (FC=2) R 3 +1 FCSC//////// //////// //////// GR0Function Code (FC) Values: 0 – Compare R 3.32-63 with 4 bytes in storage 1 – Compare R 3.0-63 with 8 bytes in storage 2 – Compare R 3.0-63 and R 3 +1.0-63 with 16 bytes in storage (new in Z10) = Index

91. SHARE 113, Session 129190 Compare-and-Swap-and-Store Facility 2 (operands equal): C8B1B1 R3R3 CSSTD 1 (B 1 ),D 2 (B 2 ),R 3 [SSF] D1D1 B2B2 D2D2 2 Resulting Condition Code: 0 1 st & 3 rd operands equal; 1 st operand replaced by replacement value, 2 nd operand replaced by store value 1 1 st & 3 rd operands unequal; 3 rd operand replaced by 1 st operand 2 -- 3 -- R 3.32-63 (FC=0), R 3.0-63 (FC=1) R3R3 4, 8, or 16 bytes in storage R 3.0-63 and R 3 +1.0-63 (FC=2) R 3 +1 FCSC//////// //////// //////// GR0 Parameter List Address GR1 Replacement Value (4, 8, or 16 bytes) Store Value (2 SC bytes, 1, 2, 4, 8, or 16 bytes) 2 SC bytes in storage = = Block concurrent interlocked-update with compare Index

92. SHARE 113, Session 129191 Message-Security Assist Extension 2:  Message-Security-Assist Extension 2: ►Adds advanced-encryption-standard (AES) functions for message ciphering –AES-192 algorithm –AES-256 algorithm –With or without chaining  MSA SHA-512 Facility. ►Adds two functions for generating intermediate- and final-message digests –SHA-512 algorithm –Also, SHA-384 (same as SHA-512 algorithm, but with different initial chaining values). Index

93. SHARE 113, Session 129192 Enhanced-DAT Facility:  Current z/Architecture has 4K-byte page frames. ►TLB entry for each translation ►TLB space is very costly, thus limited scope with larger memory.  Enhanced-DAT facility implements substantially-larger frame size ►Similar features in other architectures ►Implemented 1 megabyte frames ►Other future possibilities, 2GB? 4TB??, 8PB???  Assumes operating system does not do a lot of paging (segmenting?)  Changes to control instructions: ►LOAD PAGE TABLE ENTRY ADDRESS – Additional results returned. ►LOAD REAL ADDRESS – Additional results returned. ►SET STORAGE KEY EXTENDED - multiple-block mode (set up to 1M-byte)  Facility enabled by control register 0, bit 40: ►0 – Classic DAT ►1 – Enhanced DAT enabled Index

94. SHARE 113, Session 129193 Enhanced-DAT Facility: DAT-Table Entry Changes Index Region-Table Entry Region-Second-Table Origin, Region-Third-Table Origin, or Segment-Table Origin//P/TFI/TTTL 052545658606263 Page-Table Entry Page-Frame Real Address0IP COCO //////// 05263 Segment-Table Entry (FC=0) Page-Table Origin FCFC P///ICTT// 053545859606263 Segment-Table Entry (FC=1) Segment-Frame Absolute Address/// AVAV ACCF FCFC P COCO //ICTT// 044474852535455565859606263 ACCAccess-control bits for the segment AVValidity control for ACC and F bits CCommon-segment bit COChange-bit override FFetch-protection bit for the segment FCFormat control ITable-entry invalid bit PDAT-protection bit TFTable offset TLTable length TTTable type

95. SHARE 113, Session 129194 Enhanced-DAT Facility: PERFORM FRAME MANAGEMENT FUNCTION B9AF PFMF R 1,R 2 [RRE] R1R1 R2R2 //// Index General Register R 1 ////////////////////////////////000000000000FMFI UIUI FSC0 MRMR MCMC 0 Key 0 00 SKSK CFCF ACCFRC 0324446474849525354555660616263 General Register R 2 Second-Operand Address (AMODE dependent)//////////// 033405263 ACCAccess-control bits CChange bit of storage key CFClear-frame control FFetch-protection bit of storage key FMFIFrame-management function indication FSCFrame-size code (0:4K, 1:1M, 2-7:rsvd.) KeyStorage-protection key MCChange-bit update mask MRReference-bit update mask RReference bit of storage key SKSet-key control UIUsage indication

96. SHARE 113, Session 129195 Enhanced-DAT Facility: PERFORM FRAME MANAGEMENT FUNCTION:  New control (privileged) instruction: ►Clear up to 1MB of storage ►Set keys for underlying 4K-byte blocks ►Indicate intended usage (for guest running under z/VM)  Condition code is unchanged Index

97. SHARE 113, Session 129196 Configuration-Topology Facility  Enhancements to the STORE SYSTEM INFORMATION instruction: ►Returns new system-information block (SYSIB) 15.1.2 ►Indicates topology of processors in the configuration –Dedicated –Horizontal polarization –Vertical polarization ●Low, medium, or high entitlement  PERFORM TOPOLOGY FUNCTION instruction ►Privileged Operation ►Allows manipulation of topology for the configuration Index

98. SHARE 113, Session 129197 Configuration-Topology Facility: PERFORM TOPOLOGY FUNCTION B9A2 PTF R 1 [RRE] R1R1 //// Index ////////////////////////////////////////////////Response CodeFunction Code 0485663 Function Code (FC): 0Request horizontal polarization 1Request vertical polarization 2Check topology-change status 3-255Reserved Response Code: 0No reason specified 1Already in requested state 2Topology change already active 3-255Reserved Resulting Condition Code: 0Change initiated (FC 0 & 1) Change-report not pending (FC 2) 1Change report pending (FC 2) 2Request rejected (FC 0 & 1) 3--

99. SHARE 113, Session 129198 CPU-Measurement Facilities  Set-program-parameters facility ►SET PROGRAM PARAMETERS (SPP) privileged operation ►Used by the CPU-measurement sampling facility ►Facility bit 40 indicates presence of the facility  CPU-measurement facility ►CPU-measurement counter facility ►CPU-measurement sampling facility  Documentation: ►The Set-Program-Parameter and CPU-Measurement Facilities (SA23- 2260-00), http://publibfi.boulder.ibm.com/epubs/pdf/a2322600.pdfhttp://publibfi.boulder.ibm.com/epubs/pdf/a2322600.pdf ►The CPU-Measurement Facility Extended Counters Definition for z10 (SA23-2261-00), http://publibfi.boulder.ibm.com/epubs/pdf/a2322610.pdfhttp://publibfi.boulder.ibm.com/epubs/pdf/a2322610.pdf Index

100. SHARE 113, Session 129199 CPU-Measurement Counter Facility: Overview  For each CPU in the configuration: ►Local counter-set-state control register ►Various counters –Local counters –Global counters ►Several external-interruption events –Counter-authorization-change alert –Loss-of-counter-data alert –Masked by CR0.58 ►Measurement-counter-extraction-authorization control (CR0.15) ►Various instructions –All privileged operations Index

101. SHARE 113, Session 1291100 CPU-Measurement Counter Facility: CPU Counter Sets  Basic counter set ►Cycles, instructions, directory-write and penalty-cycle counts for L1 instruction and data caches  Problem-state counter set ►Cycles, instructions, directory-write and penalty-cycle counts for L1 instruction and data caches  Crypto-activity counter set ►Functions, cycle, blocked-function, and blocked-cycle counts for PRNG, SHA, DEA, and AES functions  Extended counter set (model dependent) Index

102. SHARE 113, Session 1291101 CPU-Measurement Counter Facility: Peripheral Counter Sets  Coprocessor-Group Address  Coprocessor-Group Counter Set ►Function counts, ►Cycle counts, ►Blocked-function counts, and ►Blocked-cycle counts for SHA and DEA/AES/MAC functions Index

103. SHARE 113, Session 1291102 CPU-Measurement Counter Facility: Instructions  EXTRACT COPROCESSOR GROUP ADDRESS (ECA)  EXTRACT CPU COUNTER (ECCTR)  EXTRACT PERIPHERAL COUNTER (EPCTR)  QUERY COUNTER INFORMATION (QCTRI)  SET CPU COUNTER (SCCTR)  SET CPU COUNTER SET CONTROLS (SCCTL)  SET PERIPHERAL COUNTER (SPCTR)  SET PERIPHERAL COUNTER SET CONTROLS (SPCTL) Index

104. SHARE 113, Session 1291103 CPU-Measurement Sampling Facility: Overview  Two sampling functions ►Basic sampling ►Diagnostic sampling  Several sampling control registers ►Table-entry-address register ►Data-entry-address register ►Maximum-buffer-size indicator ►Sampling-function-state control register ►Sampling-interval register ►Host indicator  Several interruption events  Two instructions: ►QUERY SAMPLING INFORMATION (QSI) ►SET SAMPLING CONTROLS Index

105. SHARE 113, Session 1291104 CPU-Measurement Sampling Facility: Sampling Buffers Index

106. SHARE 113, Session 1291105 CPU-Measurement Sampling Facility: Basic Sampling Data Entry Index  PSW-related objects: ►TDAT-mode bit ►WWait-state bit ►PProblem-state bit ►ASAddress-space control ►IAInstruction address  Primary ASN (from CR4.48-63)  Number of unique instructions executed simultaneously during the sampling cycle  Host and guest program parameters

107. SHARE 113, Session 1291106 Facility Indication  New facility indications for System z10 EC stored by STFL* and STFLE BitMeaning 8The enhanced-DAT facility is installed 11The configuration-topology facility is installed 26The parsing-enhancement facility is installed 33*The compare-and-swap-and-store facility 2 is installed 34*The general-instructions-extension facility is installed 35*The execute-extensions facility is installed. 40*The set-program-parameters facility is installed. 43*The DFP facility has high performance. 67*The CPU-measurement counter facility is installed. 68*The CPU-measurement sampling facility is installed. * Note, STFL cannot store beyond bit 31. Index

108. SHARE 113, Session 1291107 Summary:  A large variety of facilities added in the System z10 EC ►General-Instructions Extension Facility (72 new)General-Instructions Extension Facility ►Execute-Extension Facility (1 new)Execute-Extension Facility ►Parsing-Enhancement Facility (2 new)Parsing-Enhancement Facility ►Compare-and-Swap-and-Store Facility 2 (new function)Compare-and-Swap-and-Store Facility 2 ►Message-Security-Assist Extensions (new functions)Message-Security-Assist Extensions ►Enhanced-DAT Facility (1 new, 3 changed)Enhanced-DAT Facility ►Configuration-Topology Facility (1 new, 1 changed)Configuration-Topology Facility ►CPU Measurement Facilities (11 new)CPU Measurement Facilities  Potential for: ►Significant performance improvement ►Enhanced capabilities ►Simpler code Index

109. SHARE 113, Session 1291108 Questions? Topics