1. Burkard Reisert June 11 th, 2004 Fermilab, High Rise, Hornet Nest Pulsar Meeting Ted’s overview talk: Pulsar production/testing success !  all hardware in place (see Burkard’s talk) New VME DAQ readout code in place (see Jane and Burkard’s talk) Pulsar crate almost FULL  platform for integration in place (see Burkard’s talk) Lots of stuff to cover: Title on Agenda: Muon/XTRP/L1/SVT/Merger readiness Ted’s email: Beam tests coordination. "In God we trust, everything else we test with beam" come up with plans on how to do this. train people to rotate on weekly bases... all requests coordinate with trigger SPLs. setup web page for instructions...etc. plans... train people in the next few weeks for all data paths. start rotation by end of month.

2. Test Stand for Production Testing TS L1 Mezz. VME access Internal RAM and SRAM Internal com. TS interface SVT/XTRP L1 Signals Mezzanine card Interface Slink Interface AUX Tx Rx Mezz. SVT/XTRP SLINK

3. Production batch: 45 boards 43 delivered (2 more to be assembled) 24 w/o P3 connector 15 boards w/o P3 available for SVT all boards passed Pulsar test stand test and SVT RW test stand tests (~10 boards w/ P3 have been tested for SVT as well) 5 out of 43 had minor problems 2 already fixed, 2 @ HR, 1 demo for Zita Young (our summer student)  Very successful production & testing PULSAR Production Testing (~Last Month) Up to 9 boards tested per day

4. Test of Slink formatter on Muon board: - standalone (with Pulsar Tx) March - in beam (Muon input splitted, DAQ readout for Muon and Merger Input) April - release Slink formatter for use on other paths April SLink Formatter & Slink Merger (schedule as given on 03/12/04, revisited 04/22/04) Beam Test of Slink Merger: - Merge Muon Slink package with other Slink inputs DAQ readout of Merger inputs and outputs May - Platform for system integration in June Working hard to make it happen Conclusion: on Track Slink Tx for now Some data recorded, but not looked at It’s coming !

5. Move test stand setup to Pulsar crate in Trigger room Input to Muon Pulsar: split muon signals and Pulsar XTRP Test pattern Enable one input on Slink Merger Some DAQ issues: - FER code overwrites SLink input enable register - only 2 fiber inputs per FPGA  FER expects 8 work around: use standalone Pulsar VME code to - load proper values manually in RC CONFIG state - Dump Muon and SLink DAQ RAMs in RC HALT state  Cosmic and L2 Torture runs look promising muon fibers Muon Rx Muon & Slink Merger Installation in Trigger Room SLink Merger XTRP SLink formatter XTRP Tx L2 Muons CDF RunIIa “  ” April 21 th

6. muon fibers Muon Rx April 22 nd Status in Trigger Room SLink Merger XTRP Tx L2 Muons CDF RunIIa “  ” 16/48 RECES Reces Rx Cluster Rx CList & IsoList Muon Rx L2 Muon  Merger Reces Rx Reces  input DAQ Output  SLink Tx Cluster Rx Cluster  input DAQ Output  SLink Tx Plan for next week: -- solve DAQ issues -- go for Cosmic, L2Torture & Beam  Fibers are split

7. DAQ issues: Why we needed a new Readout? Readout of 1 board takes 0.7 ms ! Why? 1 board full cycle 2 boards full Data volume Front end readout: Overhead ~ 5  s block transfer setup time ~ 0.5  s/word Same as most CDF boards (hadron TDC is twice as fast)

8. New parameters Dial number of words per DAQ RAM Board level Readout list Deal with remapped Fiber Input DAQ Solution: more flexible Readout Configurartion: C0C0 C1C1 D1 0 D1 1 D2 0 D2 1 Muon var 256---256--- Reces 21---16---16--- SVT var (var)---------- Cluster var---8*64---8*64--- Merger var---var (var) L2toTS --- var--- Thanks to Bill & Jane

9. While new DAQ code was developed We made use of COT downtime during store  read two boards Muon Rx SLink Merger XTRP L2 Muon Slink Tx XTRP Tx Compare: Muon Output  Slink Merger (input & output) Test pattern  Slink Merger (input & output)  50k events 0 errors ready to distribute Slink Formatter Beam test of Slink Merger

10. Firmware factory LVDS Fanout board L1 SVT XTRP TS Clist These guys have been busy as bees while the new DAQ code was developed.

11. Pulsar methodology at work at its best: Testing of the new DAQ Code Reces Rx SLink Merger SVT SVT Rx Reces Tx SVT Tx Reces Fibers SLink Tx Enjoy the flexibility of the new readout code e.g.: readout 1,2,3 Pulsars 1,2,6 Buffers etc.. Add some features, fix some bugs ready for prime time!

12. Pulsar Crate in Trigger Room B0L2PU00 Muon (w/o L1) XTRP L2 Muons Run IIa Level 2 Decision Crate  - Processor 1/3 RECES Reces Cluster SVT CList Master CList ISOList MergerSlink Rx Pulsar Tx B0L2PU00 Level2_Pulsar_00 Tx crate is filling up (= SVT DataIO)

13. TRACERTRACER SVTSVT RECESRECES CLUSTERCLUSTER SLINKMERGERSLINKMERGER CRATECPUCRATECPU TRACERTRACER MUON /XTRPMUON /XTRP SLINKRX SVTSLINKRX SVT RECESRECES CLUSTERCLUSTER TXRECES&SVTTXRECES&SVT SLINKMERGERSLINKMERGER SLink Tx CRATECPUCRATECPU TRACERTRACER MUON MUON L2TS?L2TS? CLUSTERCLUSTER RECESSVTRECESSVT CRATECPUCRATECPU RECESRECES RECESRECES RECESMERGERRECESMERGER MUON /XTRPMUON /XTRP L2TS?L2TS? Future Pulsar crate (one possible config.) Present Pulsar Crate RECES XTRPRECES XTRP RECESRECES Pulsar Transmitter crate Boards w/o P3 fit in “Bottom  ” crate We have Hardware (Pulsars, Mezz., Aux. fiber & LVDS splitters) the DAQ Code (new TP2D) the Monitoring frame work We need to test all Firmware in beam to do system level tests to make a plan Crates are filling up

14. Beam tests coordination: "In God we trust, everything else we test with beam“ With beam? Yes with beam! (parasitically of course ) Ted’s charge to me: “Come up with plans” BR: “Learn from the past” CDF RunIIa (our legacy at CDF): “Level 2 pager carrier” That is exactly as much as I can do for the present system, carry the pager (more or less) H1@HERA (my previous experiment): “Expert on call” Note the difference in attitude !

15. 1 st attempt on a plan of three phases Time we spent in beam 100% Single board tests: Need access to debug connectors on the board Firmware completion: L1, PreFred, Cluster Algo now Aug ??th “Online” Monitoring Monitoring massaging High stat System level tests, Firmware massaging (performance) Fill up the crate: System level tests Single board high statstic Firmware massaging (make it work) Monitoring Completion Hardware/Firmware End of June 4 th July End of July PC PC receives beam data (incomplete event) PC returns something Pulsar Level2 triggers on Cosmics What will we be able to do in beam?

16. I know all this is common knowledge, but worth spelling it out Motivation: “I want to be an expert” “I want to know more than just my system” Education: Teaching = share knowledge Learning = spent time on the system try things out Training = do it all over again Communication (means of communication): group: informal meeting (Tue), bi-weekly meeting (Fr), email point-to-point: list of phone numbers, cell phones are superior to pagers Documentation: e-log entries HowTo pages for useful tools and trouble shooting Informal & CDF notes Celebration: have fun