Presentation is loading. Please wait.

Presentation is loading. Please wait.

Figure 5.1 Conversion from decimal to binary. Table 5.1 Numbers in different systems.

Published byDamon Allen Modified over 9 years ago

Similar presentations

Presentation on theme: "Figure 5.1 Conversion from decimal to binary. Table 5.1 Numbers in different systems."— Presentation transcript:

1 Figure 5.1 Conversion from decimal to binary

2 Table 5.1 Numbers in different systems

3 Figure 5.2 Half-adder Please see “portrait orientation” PowerPoint file for Chapter 5

4 Figure 5.3 An example of addition

5 Figure 5.4 Full-adder Please see “portrait orientation” PowerPoint file for Chapter 5

6 Figure 5.5 A decomposed implementation of the full-adder circuit HA s c s c c i x i y i c i1+ s i c i x i y i c i1+ s i (a) Block diagram (b) Detailed diagram

7 Figure 5.6 An n-bit ripple-carry adder FA x n –1 c n c n1” y n1– s n1– FA x 1 c 2 y 1 s 1 c 1 x 0 y 0 s 0 c 0 MSB positionLSB position

8 Figure 5.8 Formats for representation of integers b n1– b 1 b 0 Magnitude MSB (a) Unsigned number b n1– b 1 b 0 Magnitude Sign (b) Signed number b n2– 0 denotes 1 denotes + –MSB

9 Table 5.2 Interpretation of four-bit signed integers

10 Figure 5.9 Examples of 1’s complement addition ++ 1 1 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 ++ 0 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 2+ () 5–  3-  + 5–  7–  + 2–  5+ () 2+ () 7+ () + 5+ () 3+ () + 2– 

11 Figure 5.10 Examples of 2’s complement addition ++ 1 1 0 1 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 ++ 1 0 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 11 ignore 5+ () 2+ () 7+ () + 5+ () 3+ () + 2– () 2+ () 5– () 3– () + 5– () 7– () + 2– ()

12 Figure 5.11 Examples of 2’s complement subtraction – 0 1 0 0 1 0 5+ () 2+ () 3+ () – 1 ignore + 0 0 1 1 0 1 1 1 1 0 – 1 0 1 1 0 0 1 0 – 1 ignore + 1 0 0 1 1 0 1 1 1 1 1 0 – 0 1 1 1 1 0 5+ () 7+ () – + 0 1 1 1 0 1 0 0 1 0 5– () 7– () 2+ () 2– () – 1 0 1 1 1 1 1 0 – + 1 1 0 1 1 0 1 1 0 0 1 02– () 5– () 3– ()

13 Figure 5.12 Graphical interpretation of four-bit 2’s complement numbers 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1+1– 2+ 3+ 4+ 5+ 6+ 7+ 2– 3– 4– 5– 6– 7– 8– 0

14 Figure 5.13 Adder/subtractor unit s 0 s 1 s n1– x 0 x 1 x n1– c n n-bit adder y 0 y 1 y n1– c 0 Add ¤ Sub control

15 Figure 5.14 Examples of determination of overflow ++ 1 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 0 1 0 7+ () 2+ () 9+ () + ++ 0 1 1 1 1 0 0 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 7+ () 5+ () + 2– () 11 c 4 0= c 3 1= c 4 0= c 3 0= c 4 1= c 3 1= c 4 1= c 3 0= 2+ () 7– () 5– () + 7– () 9– () +2– ()

16 x 1 y 1 g 1 p 1 s 1 Stage 1 x 0 y 0 g 0 p 0 s 0 Stage 0 c 0 c 1 c 2 Figure 5.15 A ripple-carry adder with generate/propagate signals

17 Figure 5.16 The first two stages of a carry-lookahead adder x 1 y 1 g 1 p 1 s 1 x 0 y 0 s 0 c 2 x 0 y 0 c 0 c 1 g 0 p 0

18 Figure 5.17 A hierarchical carry-lookahead adder with ripple-carry between blocks Block x 3124– c 32 c 24 y 3124– s 3124– x 158– c 16 y 158– s 8– c 8 x 70– y 70– s 70– c 0 3 Block 1 0

19 Figure 5.18 A hierarchical carry-lookahead adder Block x 158– y 8– x 70– y 70– 3 Block 1 0 Second-level lookahead c 0 s 70– P 0 G 0 P 1 G 1 P 3 G 3 s 158– s 3124– c 8 c 16 c 32 x 3124– y 3124– c

20 Figure 5.19 An alternative design for a carry-lookahead adder x 1 y 1 g 1 p 1 s 1 s 0 c 2 x 0 y 0 c 0 c 1 g 0 p 0

21 Figure 5.20 Schematic using an LPM adder/subtractor module

22 Figure 5.21 Simulation results for the LPM adder Optimized for cost Optimized for speed

23 Figure 5.23 VHDL code for the full-adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT (Cin, x, y: IN STD_LOGIC ; s, Cout: OUT STD_LOGIC ) ; END fulladd ; ARCHITECTURE LogicFunc OF fulladd IS BEGIN s <= x XOR y XOR Cin ; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ; END LogicFunc ;

24 Figure 5.24 VHDL code for a four-bit adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY adder4 IS PORT (Cin: IN STD_LOGIC ; x3, x2, x1, x0 : IN STD_LOGIC ; y3, y2, y1, y0 : IN STD_LOGIC ; s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL c1, c2, c3 : STD_LOGIC ; COMPONENT fulladd PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END COMPONENT ; BEGIN stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: fulladd PORT MAP ( Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ; END Structure ;

25 Figure 5.25 Declaration of a package LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE fulladd_package IS COMPONENT fulladd PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END COMPONENT ; END fulladd_package ;

26 Figure 5.26 Using a package for the four-bit adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.fulladd_package.all ; ENTITY adder4 IS PORT ( Cin : IN STD_LOGIC ; x3, x2, x1, x0 : IN STD_LOGIC ; y3, y2, y1, y0 : IN STD_LOGIC ; s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL c1, c2, c3 : STD_LOGIC ; BEGIN stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: fulladd PORT MAP ( Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ; END Structure ;

27 Figure 5.27 A four-bit adder defined using multibit signals LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.fulladd_package.all ; ENTITY adder4 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ; BEGIN stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ; stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ; stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ; stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ; END Structure ;

28 Figure 5.28 VHDL code for a 16-bit adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY adder16 IS PORT ( X, Y: IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ;

29 Figure 5.29 A 16-bit adder with carry and overflow LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout, Overflow: OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ; END Behavior ;

30 Figure 5.30 Use of the arithmetic package LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; ENTITY adder16 IS PORT (Cin : IN STD_LOGIC ; X, Y : IN SIGNED(15 DOWNTO 0) ; S : OUT SIGNED(15 DOWNTO 0) ; Cout, Overflow : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : SIGNED(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ; END Behavior ;

31 Figure 5.31 A 16-bit adder using INTEGER signals ENTITY adder16 IS PORT (X, Y: ININTEGER RANGE -32768 TO 32767 ; S : OUT INTEGER RANGE -32768 TO 32767 ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ;

32 Figure 5.32 Multiplication of unsigned numbers Please see “portrait orientation” PowerPoint file for Chapter 5

33 Figure 5.33 A 4 x 4 multiplier circuit Please see “portrait orientation” PowerPoint file for Chapter 5

34 Figure 5.34 Multiplication of signed numbers Please see “portrait orientation” PowerPoint file for Chapter 5

35 Figure 5.35 IEEE standard floating-point formats Sign 32 bits 23 bits of mantissa excess-127 exponent 8-bit 52 bits of mantissa11-bit excess-1023 exponent 64 bits Sign SM SM (a) Single precision (c) Double precision E + E 0 denotes – 1 denotes

36 Table 5.3 Binary-coded decimal digits

37 Figure 5.36 Addition of BCD digits + 1 1 0 0 0 1 1 1 0 1 + X Y Z + 7 5 12 0 1 1 0 + 1 0 0 1 0 carry + 1 0 0 0 1 1 0 0 0 1 0 0 1 + X Y Z + 8 9 17 0 1 1 0 + 1 0 1 1 1 carry S = 2 S = 7

38 Figure 5.37 Block diagram for a one-digit BCD adder

39 Figure 5.38 VHDL code for a one-digit BCD adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY BCD IS PORT (X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ) ; END BCD ; ARCHITECTURE Behavior OF BCD IS SIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0) ; SIGNAL Adjust : STD_LOGIC ; BEGIN Z <= ('0' & X) + Y ; Adjust 9 ELSE '0' ; S <= Z WHEN (Adjust = '0') ELSE Z + 6 ; END Behavior ;

40 Figure 5.39 Functional simulation of the one-digit BCD adder

41 Figure 5.40 Circuit for a one-digit BCD adder c out Four-bit adder Two-bit adder s 3 s 2 s 1 s 0 z 3 z 2 z 1 z 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 c in

42 Figure P5.1 C ircuit for problem 5.11

43 Figure P5.2 The VHDL code for problem 5.17 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY problem IS PORT ( Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END problem ; ARCHITECTURE LogicFunc OF problem IS BEGIN WITH Input SELECT Output <="0001" WHEN "0101", "0010" WHEN "0110", "0011" WHEN "0111", "0010" WHEN "1001", "0100" WHEN "1010", "0110" WHEN "1011", "0011" WHEN "1101", "0110" WHEN "1110", "1001" WHEN "1111", "0000" WHEN OTHERS ; END LogicFunc ;

44 Figure P5.3 Ternary half-adder 0000 0101 0202 1001 1102 1210 2002 2110 2211

Download ppt "Figure 5.1 Conversion from decimal to binary. Table 5.1 Numbers in different systems."

Similar presentations

Adder Discussion D6.2 Example 17. s i = c i ^ (a i ^ b i ) c i+1 = a i * b i + c i * (a i ^ b i ) Full Adder (Appendix I)

Adder Discussion D6.2 Example 17. s i = c i ^ (a i ^ b i ) c i+1 = a i * b i + c i * (a i ^ b i ) Full Adder (Appendix I)
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.
Arithmetic Operations and Circuits

Arithmetic Operations and Circuits
ECE 331 – Digital System Design

ECE 331 – Digital System Design
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.
George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.
ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #12) The slides included herein were taken from the materials.

ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #12) The slides included herein were taken from the materials.
ECE 331 – Digital System Design

ECE 331 – Digital System Design
CSET 4650 Field Programmable Logic Devices Dan Solarek VHDL Behavioral & Structural.

CSET 4650 Field Programmable Logic Devices Dan Solarek VHDL Behavioral & Structural.
Chapter 7 Arithmetic Operations and Circuits 1. 7-4 Hexadecimal Arithmetic 4 binary bits represent a single hexadecimal digit Addition –Add the digits.

Chapter 7 Arithmetic Operations and Circuits Hexadecimal Arithmetic 4 binary bits represent a single hexadecimal digit Addition –Add the digits.
Arithmetic Operations and Circuits

Arithmetic Operations and Circuits
L23 – Arithmetic Logic Units. Arithmetic Logic Units (ALU)  Modern ALU design  ALU is heart of datapath  Ref: text Unit 15 9/2/2012 – ECE 3561 Lect.

L23 – Arithmetic Logic Units. Arithmetic Logic Units (ALU)  Modern ALU design  ALU is heart of datapath  Ref: text Unit 15 9/2/2012 – ECE 3561 Lect.
AND Gate: A Logic circuit whose output is logic ‘1’ if and only if all of its inputs are logic ‘1’.

AND Gate: A Logic circuit whose output is logic ‘1’ if and only if all of its inputs are logic ‘1’.
CS 105 Digital Logic Design

CS 105 Digital Logic Design
George Mason University Modeling of Arithmetic Circuits ECE 545 Lecture 7.

George Mason University Modeling of Arithmetic Circuits ECE 545 Lecture 7.
 Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-1 Arithmetic and CAD Tools CAD tools work great with arithmetic functions Adding,subtracting,multiplying,

 Seattle Pacific University EE Logic System DesignCADNumbers-1 Arithmetic and CAD Tools CAD tools work great with arithmetic functions Adding,subtracting,multiplying,
Digital Arithmetic and Arithmetic Circuits

Digital Arithmetic and Arithmetic Circuits
A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.

A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.
Chapter 4 – Arithmetic Functions and HDLs Logic and Computer Design Fundamentals.

Chapter 4 – Arithmetic Functions and HDLs Logic and Computer Design Fundamentals.
VHDL TUTORIAL Preetha Thulasiraman ECE 223 Winter 2007.

VHDL TUTORIAL Preetha Thulasiraman ECE 223 Winter 2007.

Similar presentations

Ads by Google