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1/65 Potentials of R&D for ICT in Cooperation with IPSI Belgrade An Overview of IPSI Belgrade Projects for High-Tech Computer Industry in the USA and EU.

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Presentation on theme: "1/65 Potentials of R&D for ICT in Cooperation with IPSI Belgrade An Overview of IPSI Belgrade Projects for High-Tech Computer Industry in the USA and EU."— Presentation transcript:

1 1/65 Potentials of R&D for ICT in Cooperation with IPSI Belgrade An Overview of IPSI Belgrade Projects for High-Tech Computer Industry in the USA and EU

2 2/65 IPSI Belgrade IPSI Belgrade IPSI Belgrade - Jointly founded by German/USA/Serbian capital Some of the most recent partners: - Fraunhofer IPSI, Darmstadt, Germany - Telecom Italia Learning Services, L’Aquila, Italy - NYU, School of Continuous Professional Studies, USA - StorageTek, Colorado, USA

3 3/65 Employees and Associates CEOCEO Prof. Dr. Veljko Milutinovic, Fellow of the IEEE, Electrical Engineering, University of Belgrade, Serbia Senior ConsultantSenior Consultant Prof. Dr. Erich Neuhold IPSI Fraunhofer, Darmstadt, Germany Jovic Darko, Babovic Zoran, Toskov Ivan, Vujovic Ivana, Omerovic Sanida, Vujnovic Damjan, Krunic Jelena, Milic Bratislav, Milutinovic Darko, Nikezic Gavro, Radakovic Miroslav, Skundric Nikola, Minic Predrag, Stanic Sasa, Korolija Nenad, Rudan Sasa, Kovacevic Aleksandra, etc.

4 4/65

5 5/65 Selected IPSI Belgrade Services - Workspaces of the Future - Environments for Cooperative Working and Learning - Virtual Information and Knowledge Environments - Mobile Interactive Media - Open Adaptive Information Management Systems - Publication Engineering and Technology - Hardware Design and Operating Systems - Networks and WWW - Infrastructure for E-Business on the Internet

6 6/65 General Project Structure Industrial Research: Phase #1: Survey, and Generation of Embryonic Ideas Phase #2: Analytic Analysis and Comparison (1+K) Phase #3: Simulation Analysis and Comparison Phase #4: Implementation Analysis and Comparison

7 7/65 General Project Structure Industrial Development: Phase #1: Product Requirements Phase #2: Intra Module Coding Phase #3: Inter Module Integration Phase #4: Exhaustive Verification

8 8/65 Some Recent Educ Projects Frankfurt/M, Frankfurt/O, Magdeburg, Berlin, Hagen, Koblenz, Kaiserslautern, Erlangen, TUM, IPSI FhG, Karlsruhe, Ulm,... NYU, Purdue, Dartmouth, Hawaii, … Modena, Ferrara, Siena, Pisa, Salerno, Napoli, … Tech De Monterrey, Tech De Durango, UNAM, La Salle, … St. Mary’s, Dalhousie, … RIT, Skoevde, Karlskrona, Karlstadt, … Valencia, Barcelona, Madrid, Oviedo, …

9 9/65 Some Recent R&D Projects NCR, Encore/Compaq/HP, SUN, Intel, … Comshare, Zycad, QSI, Virtual, … TechnologyConnect, BioPop, eT, MainStreetNetworks, … Salerno, Pisa, Siena, L’Aquila,... Ulm, Darmstadt, …

10 10/65 R&D Methodology Introduction Problem Statement Criticism of Existing Solutions Proposed Solution Conditions and Assumptions Details (1+k) Mathematical Analysis Simulation Analysis Implementation Analysis Conclusion

11 11/65 Internet Servers

12 12/65 NCR: NextGen PC for E-Business  Cache coherence maintenance: Hardware approach  Cache coherence maintenance: Software approach  Accelerator chip for windowing  Accelerator board for dbase applications  Prefetching on the "silence" for disk cacheing  Accelerator chip for text compression  Accelerator chip for JPEG/MPEG

13 13/65 SMP in Action M P

14 14/65 ENCORE/COMPAQ/HP  Improved RMS for PC, and its prototype  The RM/MC for PC approach, and its analysis  Simulation of selected DSM approaches, and their comparison (RMS, KSR, and SCI)  Search for the optimal RMS inteconnect technology

15 15/65 DSM in Action

16 16/65 Prologue

17 17/65 Epilogue

18 18/65 Cutting the Edge Top Down Technologies  i860  Selected microprocessor models QSI  An ATM router chip  In-memory processing

19 19/65 Response: Industry

20 20/65 Response: Academia Flynn, M. J., Computer Architecture, Jones and Bartlett, USA (96) position 1 (12 citations) Bartee, T. C., Computer Architecture and Logic Design, McGraw-Hill, USA (91) position 1 (2 citations) Tabak, D., RISC Systems (RISC Processor Architecture), Wiley, USA (91) position 1s (6 citations) Stallings, W., Reduced Instruction Set Computers (RISC Architecture), IEEE CS Press, Los Alamitos, California, USA (90) position 1s (3 citations) Heudin, J. C., Panetto, C., RISC Architectures, Chapman-Hall, London, England (92) position 3s (2 citations) van de Goor, A. J., Computer Architecture and Design, Addison Wesley, Reading, Massachusetts, USA (2 nd printing, 91) position 4s (3 citations) Tannenbaum, A., Structured Computer Organization (Advanced Computer Architecures), Prentice-Hall, USA (90) position 5s (4 citations) Feldman, J. M., Retter, C. T., Computer Architecture, McGraw-Hill, USA (94) position 7s (2 citations) Stallings, W., Computer Organization and Architecture, Prentice-Hall, USA (96) position 9s (3 citations) Murray, W., Computer and Digital System Architecture, Prentice-Hall, USA (90) position >10s (2 citations) Wilkinson, B., Computer Architecture, Prentice-Hall, USA (91) position >10 (2 citations) Decegama, A., The Technology of Parallel Processing (Parallel Processing Architectures), Prentice-Hall, USA (90) position >10s (2 citations) Baron, R. J., Higbie, L., Computer Architecture, Addison-Wesley, USA (92) position >10s (1 citation) Tabak, D., Advanced Microprocessors (Microcomputer Architecture), McGraw-Hill, USA (95) position >10s (1 citation) Zargham, M. R., Computer Architecture, Prentice-Hall, USA (96) position >10s (1 citation) Hennessy, J. L., Patterson, D. A., Computer Architecture: A Quantitative Approach, Morgan-Kaufmann, USA (96) na (0 citations) Hwang, K., Advanced Computer Architecture, McGraw-Hill, USA (93) na (0 citations) Kain, K., Computer Architecture, Addison-Wesley, USA (95) na (0 citations)

21 21/65 N.B. ERRORS MADE & LESSONS LEARNED

22 22/65 1

23 23/65 2

24 24/65 3

25 25/65 The Split Temporal/Spatial Cache Veljko Milutinović, Boris Marković*, Milo Tomašević, Aleksandar Milenković, and MarkTremblay** IFACT Department of Computer Engineering School of Electrical Engineering University of Belgrade POB 35-54 11120 Beograde, Serbia  ___________________________________________________________________________ * Boris Marković is with the University of Montenegro, Podgorica, Montenegro ** Mark Tremblay is with the SUN Microsystems, Palo Alto, California, USA

26 26/65 C1.spat COMPILE.time C2.temp C1.temp RUN.time PFB SPLIT TEMPORAL/SPATIAL CACHE MM

27 27/65 The Injection Cache Veljko Milutinović, Aleksandar Milenković, Davor Magdić, and Gad Sheaffer* IFACT Department of Computer Engineering School of Electrical Engineering University of Belgrade POB 35-54 11120 Beograde, Serbia  ________________________________________________________________________ * Gad Sheaffer is with the Intel Corporation, Beverton, Oregon, USA

28 28/65 IN PRODUCER CONSUMER C2 C1 P EARLYLATE t c t CACHE INJECTION

29 29/65 Integrated Systems

30 30/65 VLSI Detection for Internet/Telephony Interfaces Goran Davidović, Miljan Vuletić, Veljko Milutinović, Tom Chen, and Tom Brunett * eT 

31 31/65 INTERNET SERVICE PROVIDER REMOTE SITE Superposition/DETECTION... USERS... HOME/OFFICE/FACTORY AUTOMATION ON THE INTERNET SPECIALIZED

32 32/65 Reconfigurable FPGA for EBI Božidar Radunović, Predrag Knežević, Veljko Milutinović, Steve Casselman, and John Schewel *  * Virtual

33 33/65 INTERNET PROVIDER... USERS VCC CUSTOMER SATISFACTION vs CUSTOMER PROFILE SPECIALIZED SERVICE

34 34/65 Browser Acceleration Gvozden Marinković, Dragan Jandrić, Vladimir Ivanović, Veljko Milutinović, and Tom Chen  * MainStreetNetworks

35 35/65 What is the Major Bottleneck? Rendering!

36 36/65 BioPoP Veljko Milutinovic, Vladimir Jovicic, Milan Simic, Bratislav Milic, Milan Savic, Veljko Jovanovic, Stevo Ilic, Djordje Veljkovic, Stojan Omorac, Nebojsa Uskokovic, and Fred Darnell isItWorking.com 

37 37/65 Testing the Infrastructure for EBI Phones Faxes Email Web links Servers Routers Software Statistics Correlation Innovation

38 38/65 CNUCE Integration and Datamining on Ad-Hoc Networks and the Internet Veljko Milutinović, Luca Simoncini, and Enrico Gregory  *University of Pisa, Santanna, CNUCE

39 39/65 GSM DM Ad-Hoc Internet Ad-Hoc

40 40/65 Intelligent Search

41 41/65 Genetic Search with Spatial/Temporal Mutations Jelena Mirković, Dragana Cvetković, and Veljko Milutinović  *Comshare

42 42/65 Drawbacks of INDEX-BASED: Time to index + ranking Advantages of LINKS-BASED: Mission critical applications + customer tuned ranking Provider Well organized markets: Best first search If elements of disorder: G w DB mutations Chaotic markets: G w S/T mutations

43 43/65 e-Banking on the Internet Miloš Kovačević,Veljko Milutinović, Marco Gori, and Roberto Giorgi  *University of Siena

44 44/65 Bottleneck#1: Search for Clients and Investments 1472++ *University of Siena + Banco di Monte dei Paschi

45 45/65 Infrastructure for Collaboration

46 46/65 Technology Transfer Veljko Milutinović, Wendy Chin, Bob Richardson, and Jerome Friedman  *TechnologyConnect.com

47 47/65 BuyersBuyers Reseller/R&D Manager/ Product Line Manager/ Business Development Manager Reseller/R&D Manager/ Product Line Manager/ Business Development Manager License Agreement Reseller Agreement Dev. Contract Acquisition Merger ConsultantsConsultants Business Development Consultant Services Expertise SellersSellers Product Line Manager/ IP Licensing Manager Product Line Manager/ IP Licensing Manager Products Technologies Patents Expertise $ 216 B <10 % <1%

48 48/65 Socratenon Distant Web Education Engine Nenad Nikolić, Milan Milićević, Milan Trajković, Dragan Milićev, Veljko Milutinović, and Massimo Desanto  *University of Salerno

49 49/65 Intranet Internet Database Server Application Server Client Web Browser Web Server & Application SQL Server Web pages

50 50/65 SSGRR Organizing Conferences via the Internet Zoran Horvat, Natasa Kukulj, Vlada Stojanovic, Dusan Dingarac, Marjan Mihanovic, Miodrag Stefanovic, Dusan Savic, Bratislav Milic, Zaharije Radivojevic, Ivana Vujovic, and Ivan Toskov, Veljko Milutinovic, and Frederic Patricelli  *SSGRR, L’Aquila

51 51/65 2000: Arno Penzias 2001: Bob Richardson 2002: Jerry Friedman 2003: Harry Kroto

52 52/65 University of Ulm Reverse Engineering of GeForce2-4 Sasa Jandric, Zaharije Radivojevic, Milos Cvetanovic, and Veljko Milutinovic 

53 53/65 010101000001101101 Developing system control programs (drivers) for GeForce 2-4, for the Plurix operating system Main advantage of the GeForce chip (called graphical processor) is the use of 3D accelerating functions Reversed engineering is used as a technology for finding previous information on the GeForce chip

54 54/65 IPSI FhG Darmstadt Internet 3D Gallery Marinkovic Ivan, Stojanovski Aleksandar, Radakovic Miroslav, Nikezic Gavro, Skundric Nikola, Milutinovic Darko, Zivic Marko, Anucojic Goran, Vujovic Ivana, Toskov Ivan, and Milutinovic Veljko 

55 55/65 Dream Search Creating Web based art gallery with “look and feel” of the real world exhibitions Dynamically generated, with content based search engine (including image recognition) Made in ASP.NET using C# as code-behind, and ADO.NET for database access; database server is SQL Server 2000; communication with the database through XML; 3D designed with VRML

56 56/65 3D MMI

57 57/65 Summary The world’s best journals - IEEE: A European record in ICT (50) Books with Nobel Laureates (7): Kenneth Wilson, Ohio (North-Holland) Leon Cooper, Brown (Prentice-Hall) Robert Richardson, Cornell (Kluwer-Academics) Jerome Friedman, MIT (IOS Press) Herb Simon (Kluwer-Academics) Harold Kroto (Academic Mind Press) Arno Penzias (Academic Mind Press)

58 58/65 The On-Going Projects StorageTek, Colorado, USA Panthesis (exBoeing), Oregon, USA Wall Street Journal, New York, USA Fraunhofer IPSI, Darmstadt, Germany Finsoft, London, England STC, Uppsala, Sweden

59 59/65 DSFS - Digital Sealed File System Goal: System for Data Modification Detection StampTool = Smart Card –Input: Hash –Output: Stamp + Public Key Verification Body –Calculation of Hash Value –Comparison with Encrypted Stamp PublishingTool –Public Key Distribution –Several Possible Solutions Depending on a Purpose StorageTek/A Stamp Tool Server Signer Publishing Tool Verification Body

60 60/65 Multi-Domain Metadata for a More Automated ILM Storage Manager Motivation: The human component of the TCO (total cost of ownership) becomes significant today due to costs of monitoring and control. Idea: More important and useful data (or metadata) about stored information can be gleaned and collected from the storage systems and the servers that use them. StorageTek/B

61 61/65 MPEG-1/2 Multiplexer A Software Tool/Framework for Creating MPEG-1/2 System Stream Input Streams for Multiplexing: –MPEG-1/2 Audio Streams –MPEG-1/2 Video Streams –AC3 Audio Stream Proposed Solution is full Object Oriented, Implemented in C++, and Easy to Use Fraunhofer/A

62 62/65 Business Process Matchmaking The Goal of this Project was to Develop a Matchmaking Engine, the Multi-tiered J2EE Application, that will Enable Efficient Business Process Matchmaking Business Processes were Described Using the Annotated Finite-state Automata Fraunhofer/B

63 63/65 Panthesis/A E-Learning with SWAN

64 64/65 Panthesis/B Improvements of E-Learning with SWAN

65 65/65 http://galeb.etf.bg.ac.yu/vm http://www.ipsi.co.yu/ e-mail: vm@etf.bg.ac.yu office@ipsi.co.yu


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