1. Digitaalsüsteemide verifitseerimise kursus1 Digitaalsüsteemide verifitseerimine IAF0620, 5.0 AP, E http://ati.ttu.ee/~jaan/verification Jaan Raik IT-208, 620 2257, 55 13141 jaan@pld.ttu.ee

2. Digitaalsüsteemide verifitseerimise kursus2 Digitaalsüsteemide verifitseerimine Õppematerjal: Hardware Design Verification: Simulation and Formal Method-Based Approaches William K. Lam, Sun Microsystems............................................... Publisher: Prentice Hall PTR Pub Date: March 03, 2005 ISBN: 0-13-143347-4 Pages: 624

3. Digitaalsüsteemide verifitseerimise kursus3

4. 1.1 Definition Definition for: embedded system A combination of hardware and software which together form a component of a larger machine. An example of an embedded system is a microprocessor that controls an automobile engine. An embedded system is designed to run on its own without human intervention, and may be required to respond to events in real time. Source: www.computeruser.com/resources/dictionary

5. The first bug found Harvard Mark II system, 1945 5

6. When things go wrong... 1985-1987 - Therac-25 medical accelerator. At least 5 patients die. 1993 - Intel Pentium floating point divide. Costs te company $475 million. June 4, 1996 - Ariane 5 Flight 501. Rocket disintegrates 40 seconds after launch. February 2010 - Toyota Prius failure. Toyota loses its market share. 6

7. Digital systems verification course7 Digital systems verification Course book: Hardware Design Verification: Simulation and Formal Method-Based Approaches William K. Lam, Sun Microsystems............................................... Publisher: Prentice Hall PTR Pub Date: March 03, 2005 ISBN: 0-13-143347-4 Pages: 624

8. Digital systems verification course8 Digital systems verification Course outline 1. Introduction, verification methods.(1.1-1.5) 2. Decision diagrams and equivalence. (8.1) 3. SAT, symbolic simulation. (8.4-8.5) 4. Assertions and verification coverage (5.4-5.6) 5. Model-checking (9) 6. Automated debug (bug localization + correction) 7. Verification and HDL (1.6, 2-4) Exercise 1 Exercise 2

9. Digital systems verification course9 Verification versus test The goal of verification is to check if a system is designed correctly. Validation is similar to verification but we check on a prototype device, not a model. By (manufacturing) Test we understand checking every instance of a produced chip against manufacruring defects.

10. Digital systems verification course10 Types of verification Mixed-signal, analog, RF,... We consider only digital Functional, timing, layout, electrical etc. verification Here, we consider functional only

11. Digital systems verification course11 Why is verification important Some figures: 2-4 verification engineers per designer Verification takes 70-85 % of total cost of chip design Why has verification become that important?

12. Digital systems verification course12

13. Digital systems verification course13 jne… ??? 32. position ~ 4 billion grains 64. position ~10 19 grains

14. Digital systems verification course14 Moore’s law (1965) “Essential parameters of digital devices double each 18 months.”

15. Digital systems verification course15 Year of Introduction Transistors 4004 1971 2,250 8008 1972 2,500 8080 1974 5,000 8086 1978 29,000 286 1982 120,000 Intel386™ processor 1985 275,000 Intel486™ processor 1989 1,180,000 Intel® Pentium® processor 1993 3,100,000 Intel® Pentium® II processor 1997 7,500,000 Intel® Pentium® III processor 1999 24,000,000 Intel® Pentium® 4 processor 2000 42,000,000 Intel® Itanium® processor 2002 220,000,000 Intel® Itanium® 2 processor 2003 410,000,000 Moore’s law (1965)

16. Digital systems verification course16 Rapid growth of digital technology 25-30 % annually decreasing cost per function 15 percent annual growth of the market for integrated circuits But …  The cost of developing a digital chip keeps on growing. In 1981, development of a leading-edge CPU cost 1 M$ …today it costs more than 300 M$ !!! Why do costs increase ???

17. Digital systems verification course17 Design automation productivity gap –58% versus 21% annually transistors on the die Tehnology’s capabilities Designer’s productivity today time 406070 30402 30 2 3 2 System design Logic design Physical design Simulation Schematic entry Placement & routing Hierarchy, generators Logic synthesis High-level synthesis / System-level synthesis Specialized high-level synthesis < 1979 ~ 1983 1986 1988-92 1992-95 ~1996-... Person months / 20 000 logic gates 10 2 30502

18. Digital systems verification course18 Design abstraction levels and verification

19. Digital systems verification course19 Verification flow

20. Digital systems verification course20

21. Digital systems verification course21 Problems during verification Errors in spec, implementation, language No way to detect bugs in the spec, because reference object is missing. Thus: verification by redundancy. Problem: How to measure verification quality i.e. coverage? (except in equivalence checking)

22. Digital systems verification course22 Simulation-based verification

23. Digital systems verification course23 Terminology Linter is a program, that checks for syntax errors in HDL Directed tests = deterministic tests

24. Digital systems verification course24 Formal verification

25. Digital systems verification course25 Equivalence checking It is necessary to match the variable names of the designs under comparison! We implement canonical forms...... or look for an input vector that would distinguish the output responses of two designs. SAT methods. Similar to test pattern generation.

26. Digital systems verification course26 Equivalence checking Comparison of pre- and post-scan schematics Comparison of RTL versus transistor layout Verification of minor changes in the design

27. Digital systems verification course27 Model-checking The goal is to find an input assignment violating the assumed property. If such an assignment (counter-example!) exists then we can simulate it to obtain signal waveforms for debugging. If there exists no counter-example then we have proven that the implementation matches the property.

28. Digital systems verification course28 Model-checking Problems: How to extract only this portion of the design that is related to the property to be checked. Currently done manually... Selection of the properties to be checked is tricky... Bugs may occur in the implementation, in properties or in configuration (i.e. environment). Roughly 70 % of total effort for setting up the configuration.

29. Digital systems verification course29 Model-checking Theorem provers Not too much automated but...... can handle larger designs, require less memory. Use higher order logic. Thus, can check more complex properties.

30. Digital systems verification course30 Simulation-based vs formal

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