1. ECE2030 Introduction to Computer Engineering Lecture 1: Overview
Prof. Hsien-Hsin Sean Lee
School of Electrical and Computer Engineering
Georgia Tech

2. ECE2030 Syllabus Instructor: Prof. Hsien-Hsin “Sean” Lee
Course web:
My office: Klaus 2318
Teaching Materials:
Morris Mano and Charles Kime, “Logic and Computer Design Fundamentals,” the 4th edition
Course notes and handouts (check out course web)
TA: to be announced later
Attending classes is important !!

3. ECE2030 Syllabus Grading policy
3 Homework assignment: 5% each
1 Programming assignment: 10%
3 in-class exams: 15% each
1 final exam: 30%
[100,90]=A; (90,80]=B; (80,70]=C,(70,55]=D,(55,0]=F
Will scale…
All homework: turn-in in the first 5 minutes “in class” of the due day
All exams: closed books, closed notes, no calculator
Honor code
Use T-Square ( for your homework and exam grades

4. Objective: Digital Design Principle
Number systems
Boolean algebra
Switch and CMOS design
Combinational logic
Logic gates
Building blocks: de/mux, de/encoder, shifters, adder/subtractor, multiplier
Logic minimization
Mixed logic
Sequential logic
Latches, Flip-flops
Counters
State machines: Mealy/Moore machines

5. Objective: Digital Design Principle
Memory and Programmable Devices
Register, RAM, ROM, PLA, PAL
Architectural concept
Instruction set architecture (ISA)
Stored-Program Computer and Sequential Control (von Neumann architecture)
Datapath
Branches
Processor and Software Convention
MIPS ISA
Procedural calls: Stack

6. Hierarchy of Computation
Programming in
High-Level Language
Compiler/Assembler/
Linker
Problem
Algorithms
Instruction Set Architecture (ISA)
Binary
System architecture
Target Machine
(one implementation)
Micro-architecture
Functional units/
Building blocks
Gates Level
Design
Transistors
Manufacturing

7. Hierarchy of Computation
Programming in
High-Level Language
Compiler/Assembler/
Linker
Problem
Algorithms
Instruction Set Architecture (ISA)
Binary
Target Machine
(one implementation)
System architecture
Micro-architecture
Functional units/
Building blocks
Human Level
System Level
RTL Level
Gates Level
Design
Logic Level
Circuit Level
Silicon Level
Transistors
Manufacturing

8. Hierarchy of Computation
Programming in
High-Level Language
Compiler/Assembler/
Linker
Problem
Algorithms
Instruction Set Architecture (ISA)
Binary
System architecture
Target Machine
(one implementation)
Micro-architecture
Functional units/
Building blocks
Human Level
System Level
Our Focus in 2030
RTL Level
Gates Level
Design
Logic Level
Circuit Level
Silicon Level
Transistors
Manufacturing

9. Zoom-in a System Component

10. Switch G D S
John Bardeen
William Shockley
Walter Brattain
Circa. 1947, Bell Labs
Nobel Prize in Physics 1956

11. “The Tyranny of Numbers” Challenge
Inventors of Integrated Circuits
“The Tyranny of Numbers” Challenge
Robert Noyce
Jack Kilby
Nobel Prize in Physics 2000

12. Fairchild Traitorous 8
Gordon E. Moore circa. 1965

13. Moore’s Law 1.7 billions Montecito 42millions Exponential growth 2,250
90 nm
596 mm2
Moore’s Law
2,250
10 μm
13.5mm2
42millions
Exponential growth
Transistor count will be doubled every 18 months
 Gordon Moore, Intel co-founder

14. A Generic Intel-based PC System
Your CPU here

15. Dual-Core Itanium 2 (Montecito)

16. Integrated Circuit Complexity
Source: Intel

17. Minimum Feature Size
We are currently at 0.065µm (65nm) and moving towards 0.045µm

18. Average Transistor Price per year
Source: Dataquest

19. Processor Market Segmentation
High Performance
(e.g., Intel 32/64, AMD, Itanium, IBM POWER, BlueGene, Sun T1, etc)
Embedded / low-power
(e.g., ARM, MIPS, Xscale)
Special purpose
(e.g., DSP, NVidia)

20. Analog Signal vs. Digital
So, why Digital?

21. Binary Signals
So, why Binary?

22. Voltage Range of Binary Signals
5.0 Volts
HIGH (1)
HIGH (1)
4.0 Volts
3.0 Volts
2.0 Volts
1.0 Volts
LOW (0)
LOW (0)
0.0 Volts
INPUT
OUTPUT