1. 12.08.2013Embedded SystemsPage 1 C166-Core Port 5 Port 3 CPU Dual Port RAM 2 KByte Interrupt Controller Watchdog Peripheral Data External Instr./Data Instr./Data USART ASC BRG GPT1 16 32 PEC 64 K ROM (C164 CI-8RM) or OTP (C164CI-8EM) Interrupt Bus Data Port 8 BRG SSC Sync. Channel (SPI) PLL- Oscillator prog. Multiplier : 0.5; 1; 1.5; 2; 2.5; 3; 4; 5 XBUS (16-bit NON MUX Data / Addresses) T2 T4 T3 13 ext. IR Full -CAN Interface V2.0B active RTC 10-Bit ADC Timer 7 Timer 8 Port 1 Timer 13 1 Comp. Channel 3/6 CAPCOM Channels CAPCOM6 Unit for PWM Generation 89 4 16 6 Port 4 8-Channels External Bus 8/16 bit MUX only & XBUS Control CAPCOM 2 8-Channel C164CI Block Diagram P4.6/ CAN TxD P4.5/ CAN RxD Port 0

2. 12.08.2013Embedded SystemsPage 2 On-Chip (EP)ROM SP STK OV STK UV CPU – Block Diagram CPU MDL MDH Barrel-Shifter ALU 16-bit Mul./Div.-HW Bit-Mask Gen. Code Seg.Ptr On-Chip Static RAM R15 R0 STK OV STK UV 4-Stage Pipeline 32 16 Exec. Unit Instr. Ptr. Instr. Reg. SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Context Ptr. Data Page Pointer SFR PSW General R15 R0 Purpose Registers

3. 12.08.2013Embedded SystemsPage 3 Fetch Decode Execute Write Back 1. Instr.2. Instr.3. Instr.4. Instr. Time 1 Machine Cycle = 100 ns at 20 MHz CPU clock Four stage instruction-pipeline  100ns effective execution time (20 MHz f CPU )  Three Pre-Fetch-Steps in word size (Bus Controller) for supporting of the Pipeline  Optimized execution of jumps –For jump instructions (Jump, Cond. Jump, Call, Return,...) usually only one additional machine cycle is necessary, to fetch the instruction at the destination address  Jump Cache –For the execution of loops no additional machine cycle is necessary

4. 12.08.2013Embedded SystemsPage 4 Arithmetic Logic Unit ALU AB Z C in op C out flags Arithmetic Operations: Logic Operations: Shift / Rotate: addsub incdec neg andnand ornor exorexnor not sllsrl slasra rolror s/ro : shift/rotate l/r : left/right l/a : logic (unsigned)/arithmetic (signed)

5. 12.08.2013Embedded SystemsPage 5 Barrel Shifter

6. 12.089.2013Embedded SystemsPage 6 General Purpose Register (GPR)  16 GPRs form a register bank which consits of maximize –8 Word-Registers and –8 Word-Registers with byte access to the least significant and most significant byte  The GPRs are bit-addressable  the register banks can be arranged in the internal RAM in any order  The mapping of the active register bank is determined by the Context Pointer (CP)  CP can easily changed to choose an other register bank - “Switch Context”-instruction.

7. 12.08.2013Embedded SystemsPage 7 0F600 R8 R9 R10 R11 R12 R13 R14 R15 RH0 RH1 RH2 RH3 RH4 RH5 RH6 RH7 RL0 RL1 RL2 RL3 RL4 RL5 RL6 RL7 Context pointer 0FDFE 2KBytes internal RAM R6 R0 R1 R2 R3 R4 R5 R7 STKOV STKUV R15 R0 0FC00 Stackpointer Underflow Stackpointer Stackpointer Overflow STKUV STKOV 2 kByte internal RAM – mapping of the register banks and the stack SP

8. 12.08.2013Embedded SystemsPage 8  Complete address space: –64 kByte non-segmented address space –Up to 4 MBytes segmented address spaces: 64 kByte Code-Segments and 16 kBytes Data-Pages –“von Neumann”-Architecture, which is internally equipped with Multi- BUS-Structures to avoid BUS-Bottlenecks  Internal Address Space –2 KByte RAM –64 KBytes Flash/OTP ROM (One Time Programmable ROM) (C164CI-8FM)  Flexible external BUS-Configurations –Up to 22-Bit Address-BUS / 8-Bit Data-BUS (multiplexed) –Up to 22-Bit Address -BUS / 16- Bit Data-BUS (multiplexed) –5 completely independent configuration-registers –4 programmable “Chip Selects” and programmable BUS-control signals help to avoid external logic. Address Space

9. 25.9.2013Embedded SystemsPage 9 Internal and external address mapping of the C164CI

10. 12.8.2013Embedded SystemsPage 10 The programming language C for the C164 C166 is the realisation of ANSI-C for the microcontroller-family C166. The C166-Compiler provides a number of extensions of the ANSI-C Standard. Ispecially such, that directly support the C 166-architecture: C166-denotation commentary memory typesAs completition to the „storage class" to every definition of a variable a „memory type " can be specified. This allows a from the actual „memory model" independent addressing of variables in different address spaces of the 166-systems. Following typs are defined: near, idata, bdata, sdata, far, huge, xhuge. sfrIs used as declaration of "Special-Function-Register" (SFR) of the 166-family sbitDeclaration of Bits within SFR's. bitData type bit. Return values and passing parameters of functions can be of type bit. bit-addressableVariables in bit addressable space can be defined as memory type by means of bdata.

11. 12.08.2013Embedded SystemsPage 11 The programming language C for the microcontroller C164 C166-denotation commentary register bank (using) Each function can contain a declaration, in which the register bank to be used can be set. interruptFunctions can declared als Interrupt-Service-Routines by indication of the interrupt names respectively – vectors. register maskThe C166-Compiler generates for each C-function a register- mask, in which the registers used by the function are listed. Those can be used as funktion prototype, due to optimize the usage of the registers. RTX166 tasksBy the keyword _task_ the functions is specified as a task of the operating system RTX166. New Keywords (summarisation): Memory types:near, idata, bdata, sdata, far, huge, xhuge Data types:bit, sfr, sbit Functions:interrupt, _task_, using

12. 12.08.2013Embedded SystemsPage 12 Memory Types TypeAddress space near 16-Bit addresses up to 64 kBytes idata On-chip RAM (fastest access) bdata Bit-addressable On-chip-RAM sdata System Page (0xC000-0xFFFF) inclusive SFR‘s far 32-Bit Pointer with 16-Bit address calculation, the size of the object is 16 kByte. huge 32-Bit Pointer with 16-Bit, address calculation, the size of the object is 32 kByte. xhuge 32-Bit Pointer with 32-Bit address calculation, the size of the object is 16 MByte. The programming language C for the microcontroller C164

13. 12.08.2013Embedded SystemsPage 13  According to the memory types memory models can be predeterminded as presettings, which always will be used, when no memory type is explicitly specified by the variable – or function  This is done by the preprocessor directive: # pragma storage model The programming language C for the microcontroller C164 Storage model VariablefunctionsSegmentationCode size TINYnearnearno64k SMALLnearnearyes64k COMPACTfarnearyes 64k HCOMPACT hugenearyes 64k MEDIUMnearfaryes unlimited LARGEfarfaryes unlimited HLARGEhugefaryesunlimited

14. 12.08.2013Embedded SystemsPage 14 Data types: : size of memory and range of values Datentyp size of memory range of values bit #1 Bit0 or 1 signed char1 Byte-128 to +127 unsigned char1 Byte0 to 255 signed int2 Bytes-32768 to + 32767 unsigned int2 Bytes0 to 65535 signed long4 Bytes-2147483648 to +2147483642 unsigned long4 Bytes0 to 4294967295 float4 Bytes  1.176E-38 to  3.40E+38 double8 Bytes  1.7E-308 to  1.7E+308 pointer2/4 BytesAddress of the object The programming language C for the microcontroller C164 Datatypes for the access to Special Function Registers (SFR) sbit #1 Bit0 or 1 sfr #2 Bytes0 to 65535 # special data types in C166, which are not defined in ANSI-C.

15. 12.08.2013Embedded SystemsPage 15 Integrated Development Environment C- Library ANSI C Compiler Macro- Assembler – Debugger – Simulator Emulator & PROM Programmer RTX Tiny Real Time Operating System – µVision2 Editor / Project Management Library Manager Linker / Locater CPU & Simulator Monitor Target Debugging Peripheral Start of lab practical

16. 12.08.2013Embedded SystemsPage 16 Code-addressing using segmentation in the 4 MByte address space Code Segment Pointer (CSP) for Code-Addressing 22-Bit physical Code-Addresse (C164) 6-Bit Segment- number 16-Bit 0 1314 16-Bit Instr. Pointer 15 7 8 0 131415 Code Seg. Pointer 7 65 8 The Instruction Pointer (IP) is incremented after each instruction fetch phase The Code Segment Pointer (CSP) is only changed by absolute jumps, respectively indirect y in case of the return from a subroutine by the stack

17. 25.9.2009Embedded SystemsPage 17 Addressing of data by paging within the 4 MByte Address space Data addressing via the Data Page Pointer (DPP) 14-bit 0 13 16-bit Adresse 1415 Selection of a Data Page Pointer 10-bit Page- number DPP3 DPP2 DPP1 DPP0 Physical 24-Bit Data-Address (up to 22 external available for C164) SFR

18. 12.08.2013Embedded SystemsPage 18 External Bus Controller  Allows variable timing of CPU-controlling signals by software  Realizes up to 4 Chip-Select-Signals  Selection of 4 address ranges possible Special Function Register BUSCON0..4 Programmable timings Determinition of CS# - signals Selection of the bandwith of the Data-BUS 8 / 16 Bit Special Function Register ADDRSEL1..4 Programmable ranges of the address space for the access to external components with the properties of the assigned BUSCONx- registers.

19. 12.08.2013Embedded SystemsPage 19 Multiplexed Address- and Data-BUS Address Data A16..A21 ALE CS# A0..A15 D0..D15 (7) RD# A0..15 D0..15 (7) WR# Extension of the Address- Setups Memory- Access Time Tri-State - Time WR-Delay RD-Delay SFR

20. 12.08.2013Embedded SystemsPage 20 Integrated Chip Select - Signals The base address is always a multiple of the address space. (i.e. the Chip Select with an adress range of 128kByte starts at a 128kByte boundary) A21 A20 A19 CS3# CS2# CS1# CBAGCBAG CS11 CS10 CS9 CS8 CS7 CS6 CS5 CS4 74ACT138 C164 0xB80000 0xB00000 0xA80000 0xA00000 0x980000 0x900000 0x880000 0x800000 Extra Memory-Mapped Chip-Selects P3.9 P3.8 P3.6 CS3# CS2# CS1# CBAGCBAG CS11 CS10 CS9 CS8 CS7 CS6 CS5 CS4 74ACT138 C164 0xF00000 0xE00000 0xD00000 0xC00000 0xB00000 0xA00000 0x900000 0x800000 Extra IO-Mapped Chip-Selects All with equal Bus-Mode, Waitstates, et al. CS0#P6.0BUSCON0 CS1#P6.1BUSCON1ADDRSEL1 CS2#P6.2BUSCON2ADDRSEL2 CS3#P6.3BUSCON3ADDRSEL3 Active for those address space, which is not covered by CS1#..CS3#

21. 12.08.2013Embedded SystemsPage 21 Connection of external memory chips with 8 Bit - organisation C164 [20 MHz] WE# OE# CS# CE# D0-7 A0-16 A0-18 MT5LC128K8D4 AM27C040 RAM ROM MT5LC128K8D4 Fa. Micron SRAM 128k x 8 access time 25 ns ADDRSEL1 = 0x0406 BUSCON1 = 0x04CF AM27C040 Fa. AMD Eprom 512k x 8 access time 120 ns BUSCON0 = 0x04CE A1-15 15-Bit D-Latch EN WRL# WRH# RD# D0-15 A16-19 CS1# CS0# ALE

22. 12.08.2013Embedded SystemsPage 22 BHE# OE# CS# CE# D0-15 A0-15 A0-16 IDT71016 M27C202 RAM ROM IDT71016 Co. IDT (Integrated Device Technology) SRAM 64k x 16 Access time 20 ns ADDRSEL1 = 0x0405 BUSCON1 = 0x04CF M27C202 Co. ST Microelectronics ST Eprom 128k x 16 Access time 100 ns BUSCON0 = 0x04CE BLE# WE# C164 [20 MHz] A1-15 16-Bit D-Latch EN WR# BHE# RD# D0-15 A16-17 CS1# CS0# ALE A0 Connection of external memory chips with 16 Bit- organisation

23. 12.08.2013Embedded SystemsPage 23 Overlapping Address Ranges XBCON0 BUSCON2 BUSCON4 BUSCON1BUSCON3 BUSCON0 0x000000 0xFFFFFF Inactive range Active range Highest Priority Overlapping not allowed

24. 12.08.2013Embedded SystemsPage 24 Interrupt System  Interrupt Controller –Short interrupt-reaction times: Min. 250ns, typical 400ns (@20 MHz) –Low overhead for ISR’s –Powerful priorisation in 15 priority levels, each in 4 groups –Hardware Traps detects run time error –Software Traps  Peripheral Events Controller (PEC) –Releases the CPU from simple and frequently arising ISR’s –Interrupt controlled “DMA-simular” data transfer with CPU- participation –Reaction times: Min. 150ns, typical 300ns with a CPU-load of 100ns (@20 MHz)

25. 12.08.2013Embedded SystemsPage 25 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Group L e v e l 1 64 Level 15 group 1 group 0 group 2 group 3 Level 14 group 1 group 0 group 2 group 3 PEC 0 PEC 6 PEC 5 PEC 4 PEC 3 PEC 2 PEC 1 PEC 7 Level 1-13 group 1 group 0 group 2 group 3 (Level 0) group 1 group 0 group 2 group 3 Interrupts und PEC - Priorisation

26. 07.02.2015Embedded SystemsPage 26 Interrupt Processing INTR Flag is set Periph. Interrupt External Interrupt* Priority-Check Comparision of the interrupt priority with the run-time-priority of the CPU 16 Priority-Levels if higher priority Interrupt Control Register of the triggering peripheral-elements INTR Service: Rescuing: PSW, CSP, IP New CPU-Prio. in PSW. CSP and IP from peripherie-vector or trap-number PEC Service * External Interrupts are possible e.g. instead of the “Capture” Inputs 13 ext. Interrupts (+ NMI) including 4 “fast” interrupts 32 Peripheral Interrupts 4 Groups Group Check Clear INTR Flag Periph. Interrupt Dave SFRI-Vektor-TabelleµV-v1_isrDave v1_isr

27. 12.08.2013Embedded SystemsPage 27 Interrupt has passed priority- and group-check Interrupt Priority < 14 Interrupt Priority 14 or 15 and Data Counter > 0 Interrupt Priority 14 or 15 and Data Counter > 0 Interrupt ServicePEC Service 8 PEC Channels Data Counter SRC Pointer DEST Pointer Contr. Reg. Memory Segment 0 0xFFFF 0x0000 Byte bzw. Word Transfer INTR Service: Rescuing: PSW, CSP, IP New CPU-Prio. in PSW. CSP and IP from peripheral-vector or Trap-Number Interrupt if Data Counter = 0 Prioritäts- & Group Check Peripheral Events Controller (PEC) Peripheral Events Contoller SFR Demo v1a_isr_pec