1. Development of CCDs and Relevant Electronics for the X-ray CCD camera of the MAXI Experiment onboard the International Space Station Osaka University E. Miyata, C. Natsukari, T. Kamazuka, H. Kouno, H. Tsunemi NASDA (National Space Agency of Japan) M. Matsuoka, H. Tomida, S. Ueno, K. Hamaguchi Graduate University for Advanced Studies I. Tanaka OUTLINE International Space Station MAXI : Monitor of All-sky X-ray Image X-ray CCD Camera onboard MAXI --- SSC Engineering Models of SSC components Development of Electronics for SSC Summary

2. International Space Station is now constructing mainly by USA, Russia, ESA, Japan, Canada will be completed in 2006 go around the Earth in 90 min International Space Station (ISS) ©NASA/NASDA

3. MAXI : Monitor of All-Sky X-ray Image mission to monitor the all- sky in X-ray wave length from ISS selected as an early payload of the JEM Exposed Facility will be launched in 2005 by HIIA rocket carry two sensors –Gas Slit Camera (GSC)  poster 4497-18 –Solid-state Slit Camera (SSC) mission life ~ 2yr Grapple Fixture for a robot arm Radiator for X-ray CCDs Optical Star Sensor Solid-state Slit Cameras (SSC) = X-ray CCD cameras cameras Gas Slit Cameras (GSC) = X-ray gas counter cameras Electronics 180cm 80cm 100cm Total weight: 500 kg

4. SSC Solid-state Slit Camera No of chip 16chips/SSC Energy band 0.5-10 keV Sensitivity 5.6mCrab/day Effective area 100cm 2 /SSC FOV 1  x90  360  x90  (1 orbit) Pointing accuracy 0.1  x0.1  Clocking Parallel-summing (Fast@ASCA)

5. R3081

6. Cooling System for SSC Two passive radiators Loop heat pipe is attached –function as a heat switch Operating temperature of CCD: –—100~ — 70 o C at BOL –—85~ — 50 o C at EOL (Peltier cooler is also used)

7. EM of AE for SSC There are several techniques to process the CCD video signal We have developed –correlated double sampling –delay circuit (used in ASCA/SIS) –integration circuit (used in Chandra/ACIS, HETE2/SXC, Astro-E/XIS) We selected the integration circuit for the flight model

8. EM of SSC Camera

9. EM of CCD fabricated by Hamamatsu Photonics K.K. 1024x1024 pixels of 24 µm two phase gate structure 3-side buttable single stage Peltier cooler –same size as the CCD –reduce the shock stress coated by 2000Å Al fabricated sample chips both from –high-resistivity epitaxial wafer –bulk wafer (+ n + layer) To improve the radiation hardness –using Si 3 N 4 gate –having notch structure –having charge injection gate

10. Radiation Damage Test with Proton We are now performing the radiation damage test using the Van-de-Graaff accelerator in our faculty We will verify our improvements and test the charge injection method to recover 100 keV 2MeV 4MeV

11. To Evaluate & Maximize the CCD Performance We need to optimize clocking pattern and clocking voltages (high energy resolution, high Q.E. etc.) clocking pattern to recover the performance for a degraded chip due to radiation damage (charge injection method etc.)  We need highly flexible CCD driver system !

12. Previous Driver System D I/O Analog Switch CCD Use DAC to determine high & low levels for each clock Use analog switch to select the voltage levels DAC Analog Switch Analog Switch Analog Switch OP amp OP amp OP amp OP amp X Low flexibility Δ Relatively complex circuit O Small number of digital I/O pins high low

13. Analog Switch New Concept: Fast DAC & Fast FPGA o High flexibilities o Relatively simple circuit x Large number of digital I/O pins CCD 512 Kbyte Sram FPGA DAC OP amp

14. New Generation Driver System E. Miyata et al. NIM (2001)

15. Sample Waveform

16. E-NA System with SSCE Integration Board

17. 55 Fe Spectrum (ASCA grades 02346) Energy [keV] Counts readout noise 3e - rms

18. 55 Fe Spectrum (Log Scaled) Energy [keV] Counts

19. Summary of EM CCDs Achieve 40 µ m for epitaxial CCD and bulk CCDs in low dark current mode (voltage of vertical transfer gate is 4 V) To achieve thick depletion layer and good energy resolution, epitaxial4 or bulk3 chips will be selected for flight devices Q.E. (grade02346) @5.9 keV [%] Depletion Layer [µm] ΔE (grade 02346) [eV] @5.9keV epitaxial112±0.74142±5.8 epitaxial237±0.814152±3.1 epitaxial356±1.025143±2.2 epitaxial473±1.542149±1.9 bulk179±1.648208±4.7 bulk257±1.227143±3.2 bulk371±1.540162±2.5

20. Summary We have developed the engineering models for –SSC CCDs –SSC analog electronics –SSC digital electronics –SSC cooling system All components function well. We are now ready to construct the flight models. We have developed the DAQ system with low-noise, high flexible, high speed –achieve 3e - rms readout noise including CCD –achieve ~40 µm depletion layer in low dark mode

21. Near Future Plan Radiation damage test is now performing Flight design will be fixed in this summer Thermal and mechanical test will be performed in the end of this year

22. SSC… First X-ray CCD Camera All Fabricated in Japan We, the Japanese X-ray CCD team, have developed (just started to construct) X-ray CCD camera onboard –ASCA (SIS) –((( Astro-E ))) ((((( XIS ))))) –Astro-E II ( XIS II ) We developed neither CCD chip nor analog electronics We like and need to develop all for X-ray CCD for the future mission (carry CCD, I do hope !) This is the first time to develop all for X-ray CCD camera For success of our mission, we need to develop CCDs having high Q.E. and high E/  E AE having low noise capability AE to maximize the CCD performance

23. E-NA System and SSC Integration Circuit Readout noise of our system is < 3e - rms

24. Requirements for Driver System to output any kinds of clocking pattern to control clocking voltages dynamically to develop clocking pattern easily and download it by request/command to have a readout speed > 1MHz to output clocking voltage with ranges of –30 to +30V to control voltage level within 0.1~0.2V

25. Future Plan Experiments –further optimize clock voltage as well as clocking pattern –optimize many chips and find global tendency –calibration with optimized voltages and pattern –reflect our results to flight design –perform radiation damage experiments and develop clocking pattern to recover the performance Development –Clock Driver not to use VME develop standalone FPGA board (now constructing) –Analog board integrated correlated double sampling fast ADC with FPGA and IEEE1394 (firewire) –Event selection can be done –Drive CCDs developed by other companies (EEV, SITe…)