1. ABSTRACT Introduction NEW Recursive DFT/IDFT architecture Low computation cycle  1/2: Chebyshev polynomial  2/N: Folded architecture High speed  Register-splitting and computation-sharing scheme New Recursive Formula For DFT/IDFT Challenges: High-Performance and Area-Save References [1] R. D. J. van Nee and R. Prasad, OFDM for wireless multimedia communications. Norwood, MA: Artch House, 2000. [2] K. Maharatna, E. Grass, and U. Jagdhold, “A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM,” IEEE Trans. of Solid-State Circuits, vol. 39, no. 3, pp. 484-493, Mar. 2004. [3] M. D. Felder, J. C. Mason, and B. L. Evans, “Efficient dual-tone multifrequency detection using the nonuniform discrete Fourier transform,” IEEE Signal Processing Lett., vol. 5, pp. 160-163, Jul. 1998. [4] G. Goertzel, “An algorithm for the evaluation of finite trigonometric series,” American Math. Monthly, vol. 65, pp. 34-35, Jan. 1958. [5] V. V. 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Signal Processing, vol. 52, pp. 2665-2669, Sep. 2004. The Proposed folded type DFT/IDFT Architecture Lan-Da Van, Yuan-Chu Yu*, Chun-Ming Huang, and Chin-Teng Lin* National Chip Implementation Center (CIC), No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. Dept. of Electrical and Control Engineering, National Chiao-Tung University, Hsinchu, 300, Taiwan, R.O.C. Cost & Speed Achieve T m +2T a a high-performance( T m +2T a ) and area-save (save the Real Multipliers to 6 ) The Proposed recursive Processing Element(PE) Architecture Regularity construct by the N/2 PEs in parallel No intermediate register bank needed Further reduce the computation cycle to N N = (N 2 /2) / (N/2) Processor latency: 64 clock (Computation cycles) Critical Path: T m +2T a Conclusion A new recursive DFT/IDFT architecture based on the hybrid of Chebyshev polynomial and register-splitting scheme is proposed. The proposed VLSI algorithms lead to the fewest computation cycle and higher speed than others. The proposed folding recursive architecture with regular organization is certainly amenable to VLSI implementation. Chip Characteristics of the Proposed Recursive PE Proposed two design Core Type: N 2 /2 Folded Architecture: N  OFDM-based WLAN application. Comparisons Results In this paper, we propose two low-computation cycle and high-speed recursive discrete DFT/IDFT architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half computation-cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of computation cycles, based on the new core-type design, we develop the folded recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT/IDFT can be performed with the same structure under different configurations. The Core-Type DFT Architecture Computation Sharing  Common multiplier usage for cos θ K Register Splitting  Reduce critical path  Notations 0 and 1: delay elements  With the minimum critical path: 10  With the fewest registers: 10  : one-bit left shit  : the forward pipeline register Com.00011011 Period 2T m +3T a T m +2T a # of Reg.2222 Opt.NoNoYesYes,where For the DCT, and replace “n” with “N/2 – 1 – n” Take Z-transform, to get DCT/DST transformation of the DFT/IDFT by the similar methodology And apply the Chebyshev polynomials: The Proposed Recursive DFT formula: The Proposed Recursive IDFT formula: The Core-Type IDFT Architecture Data Buffer  64 16-bit word length complex data storage Control Unit  Clock Gated Control  Sequence Controller  Parameter Controller 32 PEs32 PEs  Pre-processing for S k and r k  TWO PEs for DST and DCT DFT Length(N) 64 points 64 points Input Word Length 16 bits 16 bits Critical Delay Time 11.47 ns(Over 80 MHz) 11.47 ns(Over 80 MHz) Active Chip Area 318 um x 414 um 318 um x 414 um Process Technology TSMC 0.18 um CMOS TSMC 0.18 um CMOS Recursive PE layout for DFT/IDFT architecture  For IEEE 802.11a standard: 3.2 μs ParametersSecond Order DFT/IDFT V-Y’s Structure [7] (Core Type) Y-C’s Structure [8] (FFR-DFT) Proposed Work1 (Core Type) Proposed Work2 (Folded Type) # of Computation Cycles for Each y[k] or x[n] NNNN/2 # of Computation Cycles for N-Point DFT/IDFT N2N2 N2N2 N2N2 N 2 /2N Critical PeriodT m +3T a T m +2T a 2T m +5T a T m +2T a # of Real Multipliers64663N3N Simulation Results Lower round of error due to the fewest computation cycle Full 12 band signal averages AWGN Channel Assume 6 Real Multipliers Critical Period: T m + 2T a 6 Real Multipliers Critical Period: T m + 2T a