1. Total Ionizing Dose Effects in 130-nm Commercial CMOS Technologies for HEP experiments L. Gonella, M. Silvestri, S. Gerardin on behalf of the DACEL – CERN collaboration

2. Perugia, 26/9/2006S. Gerardin Outline Introduction & DACEL Experimental and Devices TID irradiation (X-rays): –Core transistors: Worst-case bias conditions –NMOSFETs –PMOSFETs Impact of bias Different foundries –I/O transistors: Worst-case bias conditions –NMOSFETs –PMOSFETs Impact of bias and foundry Conclusions

3. Perugia, 26/9/2006S. Gerardin DACEL D esign A nd C haracterization of deep submicron EL ectronic devices for future particle detectors Born in 2004 Participating Institutions –INFN sections: Bari Bologna Firenze Padova Torino In collaboration with CERN-MIC group

4. Perugia, 26/9/2006S. Gerardin Introduction Super LHC radiation environment –Expected up to 100 Mrad in 10 years’ time Purpose of this work: –Assess the suitability of commercial deep-submicron/ decananometer CMOS technologies for use in future HEP experiments

5. Perugia, 26/9/2006S. Gerardin Devices MOSFETs manufactured in commercial 130-nm CMOS technologies: –Core transistors: t ox =2.2nm Different aspect ratio (W\L) Enclosed Layout Transistors (ELT) –I/O transistors: t ox = 5.2nm Different aspect ratio Enclosed Layout Transistors (ELT) Three different suppliers called in the following: A, B, and C

6. Perugia, 26/9/2006S. Gerardin Experimental CERN X-ray probe station –X SEIFERT RP149 60-KV maximum voltage, tungsten target –Dose rate: ~ 25 krad/s –HP4145B parameter analyzer –Thermal chuck (+5°C to +200°C) –Custom probe card –Switching matrix –LabVIEW software –Fully automated!

7. Perugia, 26/9/2006S. Gerardin Core Transistors: Worst Case Bias Conditions

8. Perugia, 26/9/2006S. Gerardin Minimum Size NMOSFETs Increase in off-current (I leak ) up to 3 orders of magnitude Large negative shift in the V th TID rebound in V th and I leak degradation Supplier A Core NMOSFET (linear) W/L= 0.16/0.12µm Source Drain Gate

9. Perugia, 26/9/2006S. Gerardin Large-width NMOSFETs Increase in off-current (Ileak) No shift in the threshold voltage TID rebound in the I leak degradation between 5 and 27 Mrad Supplier A Core NMOSFET (linear) W/L= 2/0.12µm

10. Perugia, 26/9/2006S. Gerardin Enclosed Layout NMOSFETs Negligible TID effects on Enclosed Layout Transistors Very hard gate oxide! (up to 190 Mrad) Supplier A Core ELT NMOSFET (enclosed) W min, L=0.12µm Source Drain Gate

11. Perugia, 26/9/2006S. Gerardin NMOSFETs:  V th vs dose Negligible TID effects in large-width and enclosed layout NMOSFETs Up to -150mV shift in minimum size NMOSFETs (0.16/0.12  m) TID rebound in the V th between 1 and 10Mrad Supplier A Linear Core NMOSFETs

12. Perugia, 26/9/2006S. Gerardin NMOSFETs: I leak vs dose No change in ELTs Up to 3 orders of magnitude increase for all W/L (non-ELT) TID rebound in the degradation between 1 and 10 Mrad Supplier A Core NMOSFETs

13. Perugia, 26/9/2006S. Gerardin Minimum Size PMOSFETs Less severe degradation compared to NMOSFETs Negative V th shift Negligible changes in I leak Supplier A Core PMOSFET W/L= 0.16/0.12µm V ds =1.5 V

14. Perugia, 26/9/2006S. Gerardin PMOSFETs:  V th vs dose Negligible effects in large-width and enclosed layout NMOSFETs Up to 50mV shift in minimum size MOSFETs (0.16/0.12  m) Supplier A Core PMOSFETs

15. Perugia, 26/9/2006S. Gerardin + STI: Achilles’ heel ELTs almost immune => Very hard gate oxide due to scaling Increase in I leak in Large-Width and Minimum-Size NMOSFETs => positive charge trapped in STI  V th larger in narrow channel transistors (Radiation Induced Narrow Channel Effect) TID rebound due to charge trapping/interface generation kinetics: maximum degradation between 1 and 10 Mrad W STI Parasitic Channels + + + + Main Channel poly gate positive trapped charge Interface states + + + +

16. Perugia, 26/9/2006S. Gerardin Core Transistors: Impact of Bias Conditions

17. Perugia, 26/9/2006S. Gerardin Bias Dependence:  V th Minimum-Size NMOSFETs Worst condition: – V gs = V dd –  V th,max =-150 mV Intermediate condition – V gs = V dd /2 –  V th.max =-120 mV Best condition – V gs = 0 V –  V th,max =-60mV Supplier A Core NMOSFETs W/L=0.16/0.12µm

18. Perugia, 26/9/2006S. Gerardin Bias Dependence: I leak Supplier A Core NMOSFETs W/L=0.16/0.12µm Minimum-Size NMOSFETs Worst condition: – V gs = V dd – I leak,max ↑ = 10 3 x Intermediate condition –V gs = V dd /2 – I leak,max ↑ = 10 2 x Best condition –V gs = 0 V –I leak,max ↑ = 10x

19. Perugia, 26/9/2006S. Gerardin Core Transistors: Different Foundries

20. Perugia, 26/9/2006S. Gerardin Different foundries: NMOSFETs  V th Qualitatively, the same effects Quantitatively, softer and harder technologies TID rebound occurs at different total doses Maximum  V th in minimum size NMOSFETs from 50 mV to 150 mV Suppliers A,B,C Core NMOSFETs W/L=0.16/0.12-0.13µm

21. Perugia, 26/9/2006S. Gerardin Different foundries: NMOSFETs I leak Qualitatively, the same effects Quantitatively, softer and harder technologies TID rebound occurs at different total doses Maximum I leak in minimum size NMOSFETs from 10x to 10 4 x Suppliers A,B,C Core NMOSFETs W/L=0.16/0.12-0.13µm

22. Perugia, 26/9/2006S. Gerardin I/O Transistors: Worst Case Bias Conditions

23. Perugia, 26/9/2006S. Gerardin Minimum Size NMOSFETs Supplier A I/O MOSFETs W/L= 0.36/0.24µm NMOSFET PMOSFET More severe degradation compared to core devices for NMOSFETs and PMOSFETs in terms of  V th and I leak  V th and I leak in NMOSFETs  V th in PMOSFETs

24. Perugia, 26/9/2006S. Gerardin Enclosed Layout ELTs degrade as well Gate oxide still an issue Increase in subthreshold swing: interface traps Supplier A I/O ELT NMOSFET W min, L=0.12µm

25. Perugia, 26/9/2006S. Gerardin NMOSFETs:  V th vs dose Supplier A I/O NMOSFETs  V th up to -400 mV in minimum-size devices TID rebound in narrow devices Monotonic increase in large-width and ELTs

26. Perugia, 26/9/2006S. Gerardin NMOSFETs:  I leak vs dose No change in ELTs Up to 5 orders of magnitude increase for all W/L (non-ELTs) TID rebound in the degradation between 1 and 10Mrad Supplier A I/O NMOSFETs

27. Perugia, 26/9/2006S. Gerardin PMOSFETs:  V th vs dose  V th up to 350 mV in minimum-size devices Smaller dependence on geometry than NMOSFETs Monotonic increase Supplier A I/O PMOSFETs

28. Perugia, 26/9/2006S. Gerardin Impact of Bias and Foundry Bias: dependence similar to that of core transistors –  V th.max (MS NMOSFETs) from -50 mV to -250 mV –I leak,max (NMOSFETs) ↑ from 10x to 10 5 x Foundry: variability similar to that of core transistors –  V th,max (NMOSFETs) from -400 mV to -60 mV –I leak,max (NMOSFETs) ↑ from 10 2 x to 10 8 x

29. Perugia, 26/9/2006S. Gerardin Conclusions TID effects on Core Transistors –Narrow and short devices most affected –Very hard gate oxide, less hard STI –Large impact of bias conditions during operation –Large foundry to foundry variability TID effects on I/O Transistors –Same effects as on Core Transistors + gate oxide still an issue 130-nm CMOS is harder than older technologies, and may be up to the challenge of future HEP experiments even without ELTs, but, in this case, needs constant monitoring due to variability from foundry to foundry

30. Perugia, 26/9/2006S. Gerardin Open Issues Batch to batch variability (encouraging preliminary results) Annealing and dose rate vs rebound Effects of different radiation sources (protons) Impact on flicker noise Long-term effects on the gate oxide reliability