1. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 1 Part V: A NOC Design Methodology Juha-Pekka Soininen VTT Electronics Oulu, Finland NOCARC project

2. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 2 Background of the presentation Mission: –How to develop a system that uses 1 billion transistor capacity effectively in 2007-2010 Maturity of design methodology: –2nd guess on how NOC based systems should be developed Related methodologies: –distributed systems –parallel processing systems –systems on chip and ASIC design

3. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 3 Outline Existing design flows NOC concept –Capacity considerations –Application characteristics NOC design challenges NOC design methodology –NOC layers –Development flow –System services –Architecture design problems –Application development problems Conclusions

4. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 4 Resource development Function development System exists monitoring estimation cosimulation benchmarking performance analysis simulationemulation prototyping profiling performance simulation mappability estimation synthesis design capacity estimation modelling mathematical analyses workload analysis complexity analysis System does not exist Design Flow Space

5. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 5 Extremely short introduction to existing design flows Algorithm on Chip (AoC) –ASIC design flow –FPGA design flow System on Chip (SoC) –Codesign flow –IP based design flow –Platform based design flow (Resources on Chip, RoC) Configuration design flow Software design flow

6. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 6 Resource development Function development Chip exists simulationemulationprofilingsynthesis HW design modelling mathematical analyses complexity analysis System does not exist AoC Design Flow Algorithms exists Algorithm design feasibility studies changes into functionality

7. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 7 Resource development Function development System exists monitoring cosimulation simulationemulation prototyping profiling mappability estimation synthesis modelling mathematical analyses workload analysis System does not exist CoDesign Flow SW/HW partitioning capacity estimation

8. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 8 Resource development Function development System exists monitoring cosimulation emulation prototyping mappability estimation modelling mathematical analyses workload analysis System does not exist IP Based Design Architecture template estimation IP block integration capacity estimation

9. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 9 Resource development Function development System exists SW design modelling System does not exist Software Design Computer exists monitoring estimation benchmarking prototyping performance simulation Computer design performance analysis RTOS services

10. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 10 10 computers Capacity of Network on Chip Average SoC design  1 million gates 1 billion transistors  250 million gates 1 NoC > 200 SoCs 1 GHz clock with RISC computer  1000 MIPS performance 1 NOC capacity  100-10000 GIPS Applicability of capacity is limited by communication

11. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 11 “Applications” for NOC Multistandard terminal Next generation base station Simulation of human brain Virtual reality creation Telepresence Holodeck (Star Trek) Purpose of Life (Hitch Hikers Guide to Galaxy) Simulation of universe Commercial operating system :-) Piece of cake Realistic applications Maybe not even for NOC Real challenges for every archtitecture

12. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 12 Application characteristics NOC capacity will be shared by several simultaneous applications NOC must be adaptable to different workload patterns Different applications have very different requirement profile Stream-based processing Parallel processing tntn t n+ p Real-time processing

13. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 13 Network on Chip alternatives NOC = Network of computation and storage resources NOC parameters: Number of resources Types of resources GPU DSP Memory Configurable HW Coprocessors Any combination Communication capability

14. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 14 Network on Chip alternatives Regions are used to encapsulate application requirements Parallel high-performance datapaths WCDMA bit-stream processing OFDM bit-stream processing Data compression, encryption, decompression, decryption

15. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 15 Network on Chip alternatives Memory area Memory management Applications DATABASE NOC

16. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 16 Network on Chip alternatives Parallel processing engine IO

17. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 17 NoCSoC NOC design challenges Physical limits -> Architecture basics -> GALS -> Communication principles Application requirements -> Region concepts -> Heterogenuous resources types -> Multilanguage and method design flows Overall complexity -> Architecture reuse -> Platform type of design flow Overall complexity -> Basic control principles -> System services Manufacturability problems -> Structured approach

18. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 18 Performance CostVariability System Quality Capacity Energy consumption Implementation Development Modifiability Volume Flexibility Complexity Functionality Modularity Cohesion Coupling Configurability Programmability Applicability Structural Functional Control Lifetime Manufacturability Usability Effort Time Risk Materials Licencing Production Computation Storage Communication Fault tolerance Result quality (accuracy) Responsiveness Scalability Efficiency Utilisation Figure of Merit for NOC based systems

19. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 19 Basic requirements for NOC design methodology Reuse –of intellectual property blocks best performance/energy ratio best mapping to application characteristics Reuse –of hardware (and architecture) best complexity/cost and performance/cost ratio only way to even dream of achieving time-to-profit requirements Reuse –of design methods and tools only way to deal with heterogenuous application set

20. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 20 NOC Design Methodology Generic backbone NoC system Optimised Virtual Components Definition of NOC platform Optimised Intellectual Property Features Applications Algorithms Cores Memories Accelerators Instantiation of NoC platform Code and configuration “Application area specific IPR” Product area specific platform “Product specific IPR” Communication structure Processors and hardware

21. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 21 Communication Structural layers of NOC Regions Resources Hardware units Executables Functions Applications Configuration Product Channels and protocols Processors, memorires, configurable HW, logic System control, product behaviour Resource types, buses, IO Region types, switches, network interfaces RTOS, code, HW configurations Resource management,diagnostics, applications Execution control, functions Network management, allocation, operation modes

22. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 22 Logical layers of NOC Backbone –Communication resources –Basic set of system services –Architecture design methods and tools Platform –Computation and storage resources –System services –Application design methods and tools System –Functionality of computation(code, configuration) –Control (OS, NetOS) –Validation and verification support Communication Regions Resources Hardware units Executables Functions Applications Configuration Product

23. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 23 Development of NOC based systems BACKBONE PLATFORMS SYSTEMS Baseband platform Database platform Multimedia platform High-perforrmance communication systems High-capacity communication systems Virtual reality games Entertainment devices Personal assistant Data collection systems

24. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 24 Resource development Function development NOC System System does not exist Using Design Space for NOC Platform Backbone Architecture design Application mapping System Services Operation principles Communication channels Non-configurable hardware Product differentiation Product area specialisation

25. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 25 System Services Purpose to hide implementation details from application developer –Execution services Communication, resource allocation and conversion services –Control services Power management, reconfiguration, load migration, fault detection and recovery, data collection and analysis –Development support services Language interfacing, compilers, libraries, optimisations, debugging, testing, validation, etc. System services are part of backbone and platform NOC Platform Chip System Services Applications Thickness of service layers Performance ASIC SW

26. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 26 NOC Platform development Scaling problem –How big NOC is needed? What are the application area requirements? Region definition problem –What kind of regions are needed? What kind of interfaces between regions? What are the capacity requirements for the regions? Resource design problem –What is needed inside resources? Internal computation type and internal communication? Application mapping flow problem –What kind of languages, models and tools must be supported? How to validate and test the final products?

27. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 27 NOC Application Development Mapping problem –How to partition applications for NOC resources? How to allocate functionality effectively? Is the performance adequate? Is the resource usage in balance? Optimisation problem –How to perform global optimisation of heterogenuous applications? How to define right optimisation targets? How to utilise application/resource type specific tools? Validation problem –Are the contraints met? Are the communication bottlenecks or power consumption hot spots? How to simulate 10000 GIPS system? How to test all applications?

28. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 28 Methods & Tools Analysis of applications (characterisation) –analysis of complexity, computation type, communication requirement, storage, etc. –for scaling, region and resource type selection, and application mapping –Different abstraction levels: workload model, application model, execution model Validation of decisions –network simulations at various abstraction levels (effects of mapping) Estimation of quality characteristics –global vs. local optimisation of the system –SW architecture vs. HW architecture –computation vs. engine Development support –virtual execution platforms for application developers –integration of existing design tools for resource level design

29. Juha-Pekka Soininen Systems on Chip Workshop Villach, Austria, 17.9.2001 29 Conclusions Development of NOC systems will be a huge effort –reuse in all levels is a must reuse of architecture, hardware and software in product reuse of different languages, methods, tools and practices during development Backbone, platform, system based design methodology apporach – provides variability and performance Analysis, decision, estimation and validation methods are the cornerstones of NOC development –complexity, functionality, workload vs. capacity, performance, efficiency