1. AHCAL Electronics. Status and Outlook Mathias Reinecke AHCAL main Meeting D ESY Hamburg, Dec. 16th, 2014

2. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 2 Outline Detector Layers at CERN Testbeam 2014 > CERN testbeam 2014  Setup  Old Problems > New DAQ Interface modules > HBU3 (DESY) and SM_HBU3 (Mainz-DESY)

3. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 3 CERN testbeam 2014 - Setup > 11 single-HBU layers, including 3 ScECAL and 1 SM_HBU layers. > 4 big 2x2-HBU layers. > More than 3800 detector channels. > Very stable operation (DAQ talks).

4. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 4 Old Problems > Arbitrary operating conditions: Stuck TDC, spontaneous noisy channels, > SPIROC re-programming/reset does not help, only re-powering helped. > Big 2x2 layers concerned more often. > Corrected switch-on procedure did not help as in the past.

5. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 5 One Approach to find the Reason > Problem still seems to be related to switch-on => Test of supply voltages: > VDDA and VDDD switch-on time different – but no spikes. > Cable diameter between MPOD and modules must not be too small!! Currently too high voltage drop. VDDA VDDD regulator- input (+6V) Single HBU 2x2 HBUs, worst case VDDA VDDD regulator- input (+6V) 400µs2ms

6. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 6 Old problems – status > Assumption: SPIROCs in undefined state after power-up. Only re-powering changes situation. > Situation could not be reproduced in Hamburg with 1x2 HBU setup. > Situation not stable at CERN: Problems could be solved at first (termination of the open-collector signals on DIF), but then situation got worse continuously for big layers (hints: could be temperature-related). > Needs testing with setup in Hamburg.

7. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 7 Redesign DAQ Interface modules > (Not only) for 2015 testbeams, new DAQ Interface modules (DIF, CALIB, POWER, CIB) are needed. > Redesigns will address:  Power pulsing (adaptation blocking capacitors, reduce voltage drop on slab).  Better switch-on procedure (to be discussed with Omega).  Software controlled SiPM bias voltage. > Redesigned modules compatible to current HBUs/Flexleads. > DIF needs biggest change: FPGA is outdated => XILINX Zynq from LDA. > Completion (hard- and software) till May 2015 is a risk! > Schedule for SPIROC3? This needs a change of the DAQ modules as well.

8. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 8 HBU3 and SM_HBU3 > 2 new members in the HBU family: HBU3 and SM_HBU3. > HBU3: improved LED system and special features for power pulsing. > SM_HBU3: Based on HBU3 design, cooperation Uni Mainz / DESY. > SM_HBU3 uses Hamamtsu surface mounted SiPMs on the HBU’s backside: > See details and results in Phi’s talk tomorrow. SM_HBU3 backside with SMD SiPM pad

9. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 9 Conclusions / Questions > HBU2 and HBU3 work fine, both boards are in operation. > Switch-on behavior needs understanding. > Testbeam Setup will be operated in Hall West for tests. > New productions (inner- and outer detector) ahead. W/O redesign? > Slab-Test in FE-lab needed: Conclusions from last slab test are in HBU3, but could not be tested so far!

10. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 10 Backup Backup Slides

11. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 11 DAQ Interface Boards – Redesign Plans > Open-collector termination voltage (1.1V) switchable by software (switch-on procedure). > LVDS inputs ac-coupled with initial state definition. > New FPGA (Zynq? Spartan6?). Cost… > Regulator enable signals (power_group_enable 1,2) from DIF to POWER (switch-on procedure). > Enable signals for LVDS outputs (to SPIROCs) with pulldown. > Use 0603 components, more test points. DIF changes:

12. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 12 DAQ Interface Boards – Redesign Plans > Blinking LED to be switched off (only software change). > Output (Lemo or jumper) for Trig_Ext (charge-injection tests) > Enable signals for LVDS outputs. > Unused input pins to jumper. CALIB changes: > Software controlled bias voltage adaptation with linear characteristic. > Automatic temperature compensation (Prague)? > Cooling setup for VDDA. > Unused spare input pins to jumper. POWER changes:

13. Mathias Reinecke | AHCAL main meeting | Dec. 16th, 2014 | Page 13 DAQ Interface Boards – Redesign Plans > Landing fields for VDDA/GND as on HBU3. > Regulator enable signals (power_group_enable 1,2) from DIF to POWER. > Enable signals for LVDS outputs. > Room for cooling pipes? > Mini-HDMI connector? > Wire unused traces DIF/POWER/CALIB (spare lines for later functions). CIB changes: