1. TFT LCD AIM SPICE
P / 梁亦中
P / 方貴弘

2. Past History of SPICE
SPICE : Simulation Program with Integrated Circuit Emphasis
1968 : Ron Rohrer Berkeley,Larry Nagel CANCER
1970 : SPICE1(Fortran)
1975 : SPICE2(Fortran)
1980 : SPICE3(C Language)
1980~Now :
HSPICE
PSPICE
AIM-SPICE (AIM)
Smart-SPICE (Silvaco)
Eldo (Mentor)
Spectre (Cadence)
HSPICE
PSPICE
AIM-SPICE
Smart
SPICE
Eldo
Spectre
Kernel
Berkeley
SPICE
Shell

3. SPICE Algorithms Principle : Kirchhoff’s Law node
Numerical analysis : Newton Method

4. Analog Circuit Design Flow
Schematic edit
Circuit simulation
SPICE
Schematic driven layout
Layout
-Laker
Device model extraction
1. TEG data analysis
2. Curve fitting
3. Process characterization
DRC/LVS
-Calibre No
Yes
Parasitic R/C Extractor
-Calibre RCX
Post simulation
SPICE
GDS II / Mask

5. AIM SPICE Parameter Extract_1
TFT LCD Test Mask IV Curve
IdVd Curve
Vg = 5V,10V,15V,20V,30V
IdVg Curve
Vd = 1V,4V,7V,10V,13V
Modeled
Measured

6. AIM SPICE Parameter Extract_2
Hole-Induced
Leakage Current
Above Threshold
Below Threshold
Extract
Parameter

7. AIM SPICE Parameter Extract_3

8. Pixel Equal Circuit & RC Calculation
Cgate =((Cst*Clc)/(Cst + Clc) + Cgs + Cgs_coup + Cdg cross + Cgate_com)*1280*3
Rgate =(ρ * L1/W1)*1280*3
Cdata =Cgd + Cdg cross + Cdata_com + Cpixel_data_coup)*1024
Rdata=(ρ * L2/W2)*1024
Cpixel = Cgs + Cgs_coup + Clc + Cst + Cpixel_data_coup 1 2 3 4 5 6 7 9 8 10 L1 W1 L2 W2
Data Line
the N-1th
Data Line
the N th
Gate Line
the (N-1)th 2
C lc
C st(on gate) 1
C pixel_data
coup(own) 9 6
C data_com
( lc ) 10
C pixel_data
coup(next)
Gate Line
the Nth 8
C gs_coup
C gs
C gd 3 4
C gate_com 5 7
C dg cross

9. Using Pi(π) Model to Simulated
We using 4 π Model to simulated one gate line and data line R C
One πmodel

10. Panel Equal Circuit of Simulation1 6 7 8 2
If Resolution = 1280*1024
Node 3 = Sub_pixel (0,512)
Node 4 = Sub_pixel (1920,512)
Node 5 = Sub_pixel (3840,512)
Signal in 1 14 V
Driving Direction
Gate n-1 Pulse 2 10 11 V 12 23 26
Gate n Pulse 3 4 5 V 17 20 6 7 8 9 9 9

11. SPICE Program Description 1 - Basic Definition
(Device+Name) Node Value / Parameter
Device:
D: Diode
C: Capacitance
I: Independent
Current Source
J: JFET
M: MOS
Q: BJT
R: Resister
V: Independent
ex: Rgate k
Cgate p
Vgate V
M1 2(D) 3(G) 6(S) 0(GND) Model()

12. SPICE Program Description 2 - Basic Definition
Dot Command
Format => command
.DC 直流掃描
.END 檔案結束
.IC 設定起始電壓電流
.MODEL MODEL宣告
.PLOT 輸出圖形
.PRINT 輸出數值
.TRAN 暫態分析

13. SPICE Program Description 3 – Power definition
VGATE PWL 0u vgl 25u vgl 25.01u vgh 35.31u vgh 35.32u vgl 150u vgl
VSIG1 2 0 PULSE (vdl vdh u 1n 1n u u)
V1 V2 start rise fall pulse width period
VCOM V V DC voltage source V2 V1

14. SPICE Program Description 4 - Example 1
*** Simulation of One Gate Delay by AIM-Spice ***
.param vgh=27V vgl=-6V vgc=-6V
.param gpi_r=1.176k gpi_c=24.27p
.param gpx_r=0.3k
.param length=9u width=18u
VGATE PWL 0u vgl 25u vgl 25.01u vgh
+35.31u vgh 35.32u vgl 150u vgl
.IC V(10)=vgl V(3)=vgl
***GATE DELAY *** Drive IC
RGATE gpx_r
CGATE p
CGATE p
***GATE DELAY *** PI-g1
RGATE gpi_r
RGATE gpi_r
CGATE gpi_c
CGATE gpi_c*2
CGATE gpi_c
***GATE DELAY *** PI-g2
RGATE gpi_r
RGATE gpi_r
CGATE gpi_c
CGATE gpi_c*2
CGATE gpi_c
.TRAN e u
.PLOT TRAN V(3) V(4) V(5)
.END 3 4 5 6 7

15. SPICE Program Description 5 - Model - 1
General form:
MXXXXXXX ND NG NS NB MNAME <L=VALUE> <W=VALUE> <AD=VALUE>
+ <AS=VALUE> <PD=VALUE> <PS=VALUE> <NRD=VALUE>
+ <NRS=VALUE> <OFF> <IC=VDS,VGS,VBS> <TEMP=T>
a-Si TFT in SMART SPICE
.MODEL  TFT  NTFT (LEVEL = 35, ******* )
a-Si TFT in AIM SPICE
.MODEL  TFT  NMOS (LEVEL = 15, ******* )

16. SPICE Program Description 6 - Model - 2
Example of a-Si TFT Description by AIM Spice
M TFT L=length W=width
.MODEL TFT NMOS ( LEVEL = TOX = 3.5E-7
+TNOM = VTO = 1.6
+ALPHASAT= DEFO = DELTA = 9.2
+EL = EMU = EPS = 11
+EPSI = GAMMA = GMIN = E22
+IOL = E KASAT = 1E KVT =
+LAMBDA = M = MUBAND = 1E-3
+SIGMAO = E VO = VAA = E4
+VDSL = VFB = VGSL = 100
+VMIN = CGDO = 0.6n CGSO = 0.6n )

17. SPICE Program Description 7 - Example 2
*** Simulation of One Pixel By AIM-Spice ***
.param vgh=27V vgl=-6V
.param vdl=1V vdh=10V
.param gpx_r=0.3k
.param lcc=0.179p csc=0.164p cgsc=0.0078p
.param length=9u width=18u
VGATE PWL 0u vgl 25u vgl 25.01u vgh 35.31u
+ vgh 35.32u vgl 150u vgl
VGATE vgl
VSIG1 2 0 PULSE (vdh vdl 12.5u 1n 1n u 25u)
VCOM V
.IC V(10)=vgl V(3)=vgl V(9)=5V
.IC V(2)=vdh
.IC V(6)=vdl
RGATE gpx_r
RGATE gpx_r
CGATE p
CGATE p
CLC lcc
Cs csc
CGS cgsc
***TFT***
M TFT L=length W=width
* SiOx thickness 3500A
.model TFT NMOS(level=15 alphasat=0.715 defo=0.6 delta=5 emu=0.02
+ el=0.1 eps=11 epsi=4.7 gamma=0.535 gmin=1e+023 iol=2.8e-012
+ kvt=-0.01 lambda=0.001 m=1.2 muband=0.001 rd= rs=220000
+ sigmao=5e-014 tnom=27 tox=3.5e-007 vaa=2400 vdsl=30 vfb=-5.38
+ vgsl=50 vmin=0.3 vo=0.29 vto=1.8 )
.TRAN e u
.PLOT TRAN V(2) V(3) V(6)
.END

18. SPICE Output Node Waveform
What can we gain from this Waveform Chart?
Gate Delay
Charging Capability
Feedthrough Voltage

19. Gate Delay Simulation Data
17” Gate Delay at charge time 10.3us
Gray level = L0 (black)
Gate Delay(at Vg=0V)
Measured=1.2us
Simulated=1.2us

20. Other Case about SPICE Simulation_1
19” Gate Pulse Cut (Cs on Com)

21. Other Case about SPICE Simulation_2-1
dVcom = (dVp_P + dVp_N)/2

22. Other Case about SPICE Simulation_2-2
 Modify = Simulation * inch

23. Other Case about SPICE Simulation_3
Cpd Coupling Effect Simulation

24. LCD Circuit for Smart Spice ( Orcad )

25. LCD Pixel Circuit for Smart Spice
Pixel Capacitance
Clc=0.139pF
Cst=0.229pF
Cgs=0.011pF
Cpd_L=0.012pF
Cpd_R=0.010pF
Rlc=10E12ohm
Other Capacitance
Cgc=0.009pF
Cdc=0.022pF
Cgd=0.056pF

26. The End