1. Spring 2006 1 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Advanced Computer Architecture Lecture 8 Project 3: memory agent Programmed I/O Direct memory access

2. Spring 2006 2 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Project 3 system schematic

3. Spring 2006 3 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Project 3 requirements Goal: memory bus agent Requirements –ROM: 0x00 – 0x1f –RAM: 0x20 – 0xff Fully decode: address and control buses Assume one master Must generate ACK (tri-state)

4. Spring 2006 4 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Project 3 traces read ROM

5. Spring 2006 5 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Project 3 traces, continued. write RAM

6. Spring 2006 6 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Project 3 traces, continued. read RAM

7. Spring 2006 7 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering I/O design Separate I/O address space –Instructions for I/O operations: in, out –Address often referred to as a Port One address space –Known as “memory-mapped I/O” –All memory reference instructions may operate on I/O data

8. Spring 2006 8 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Memory mapped I/O example I/O device: USART Receiver –Control register: 0xffff 0000 –Data register: 0xffff 0004 Transmitter –Control register: 0xffff 0008 –Data register: 0xffff 000c

9. Spring 2006 9 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering C8251 block diagram

10. Spring 2006 10 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Assembly code Definitions for memory-mapped devices

11. Spring 2006 11 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Assembly code, continued. Subroutines to read and write a byte

12. Spring 2006 12 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Find flowchart for rcvbyte?

13. Spring 2006 13 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Wait loop Programming technique –CPU continuously reads control register until non-zero (ready bit set) –CPU reads/writes data to port Results in poor system utilization: both memory-mapped or separate I/O addresses Known as programmed I/O

14. Spring 2006 14 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Disadvantages of programmed I/O? 1.Wasted cycles CPU 2.Not writing to bus if reading it 3.No work done on bus 4.

15. Spring 2006 15 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Direct memory access Objective: avoid the disadvantages of programmed I/O (eliminate the busy loop) Technique –CPU writes to special controller (word count and memory address) –CPU tells controller to start data transfers –CPU continues with other computing –CPU responds to interrupt from controller: ISR

16. Spring 2006 16 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Role of DMA controller Accept initialization data from CPU Access I/O device and drive bus (master) –Input: read I/O device and write data to memory –Output: read memory data and write to I/O device Interrupt CPU when transfer complete

17. Spring 2006 17 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Programmed I/O Programmed I/O ties up CPU Read I/O Write memory

18. Spring 2006 18 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering DMA I/O DMA requires little CPU overhead Initialize Multiple transfers

19. Spring 2006 19 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering DMA time line ISR Interrupt CPU and I/O concurrent in time

20. Spring 2006 20 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering DMA hardware view n words adr X adr X+(n-1) Memory I/O device buffer System busadr 0 adr n-1

21. Spring 2006 21 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering DMA initialization instructions? 1.Memory/destination address 2. How long, or how many 3. Tell it to start

22. Spring 2006 22 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering DMA controller architecture Counts up from zero Counts down to zero Preset counter Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr

23. Spring 2006 23 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering

24. Spring 2006 24 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Find flowchart for rcvbyte? Push $ra Get rcv status Char ready? Read and echo char Pop $ra yes no

25. Spring 2006 25 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Disadvantages of programmed I/O? 1.CPU cycles result in little computing 2.Memory continuously accessed, possible contention with another CPU 3.One I/O access at a time 4.Bus heavily requested

26. Spring 2006 26 EE 437 Lillevik 437s06-l8 University of Portland School of Engineering DMA initialization instructions? 1.Write start address 2.Write word count (or end address) 3.Write “go” command Each write is to a specific DMA controller port address