1. ULTIMATE Design Review Outline  STAR Pixel Sensor Evolution  MIMOSA-26 Design  ULTIMATE Design & Optimisation  Pixel, Discriminator, Auxilliary Functional Blocks  Analog Characterization  Summary Designers : G. Bertolone, C. Colledani, A. Dorokhov, W. Dulinski, G.Dozière, A. Himmi, Ch. Hu-Guo, F. Morel, H. Pham, I. Valin, J. Wang Test engineers : G. Claus, M. Gelin, M. Goffe, K. Jaaskelainen, M. Specht

2. STAR IPHC isabelle.valin@ires.in2p3.fr 2 06/12/2010 Design Review STAR PIXEL Detector A 3 (+ 1) steps evolution:  2007: A 3 plans telescope has been constructed Sensor: MimoSTAR-2, 5x5 mm 2, analogue output Submitted Q2 2005  2012: A engineering prototype detector with limited coverage will be installed Sensor: PHASE-1: 2x2 cm 2, binary output, NO Zero suppression Submitted Q3 2008 + V2 in Q3 2009  2010: EUDET Telescope Delivery Sensor: Mimosa26: 1x2 cm 2, binary output, Zero suppression Submitted: Q4 2008 + HRes Q4 2009  Toward ULTIMATE  2013: The pixel detector composed with 2 layers will be installed Sensor: ULTIMATE: 2x2 cm 2, binary output, Zero suppression

3. STAR IPHC isabelle.valin@ires.in2p3.fr 3 06/12/2010 Design Review MIMOSA-26: Sensor for EUDET Beam Telescope Main characteristics of MIMOSA26 sensor:  Column // architecture with in-pixel Amp & CDS and end-of-col. discrimination, followed by Ø  Active area: 21.2×10.6 mm²,1152 x 576 pixels, pitch: 18.4 µm   sp. < ~ 4 µm  Read out time < ~100 µs (10 4 frames/s)  suited for ~ 5 10 5 particles/cm²/s  Yield ~ 90% (75% fully functional sensors thinned to 120 µm + 15% (showing one bad row or column))  Thinning yield to 50 µm ~ 90% Collaboration with IRFU/Saclay

4. STAR IPHC isabelle.valin@ires.in2p3.fr 4 06/12/2010 Design Review ULTIMATE based on MIMOSA-26 sensor Half reticle 1152 x 576 pixel matrix  Integration time ~ 100 µs Pixel Pitch: 18.4 µm Temperature ~ 20 °C Light power consumption constrains: power consumption ~ 270 mW/cm 2 Space resolution < ~ 4 µm No constrains on radiation tolerance Full reticle 960 x 928 pixel matrix  Longer integration time ~ 200 µs Pixel pitch: 20.7 µm Temperature: 30 - 35 °C Power consumption: target ~ 100 mW/cm² Space resolution < 10 µm 150 kRad / yr & few 10 12 N eq /cm² /yr  Optimisation 20240 µm 22710 µm 3280 µm 21560 µm 13780 µm MIMOSA26 ULTIMATE

5. STAR IPHC isabelle.valin@ires.in2p3.fr 5 06/12/2010 Design Review ULTIMATE Design and Optimization (1) Reduction of power dissipation  Optimisation of pixel pitch v.s. non ionising radiation tolerance Larger pitch: 18.4 µm  20.7 µm  Shorter integration time: 185.6 µs  Validated by the small prototype MIMOSA-22AHR  Optimisation of power consumption  Power supply voltage reduced from 3.3 to 3 V in ULTIMATE simulation  Design of pixel tested at 3V (in MIMOSA-22TER) with adjusted Vcl= 1.9 V:  7% increased ENC, 15% decreased gain  Estimated simulation power consumption ~ 150 mW/cm² (at 3.3 V ) 135 mW/cm 2 (at 3 V) Pixel improvement: charge collection, radiation tolerance  High resistivity EPI substrate and radiation tolerance design  Validated by the small prototype MIMOSA-22AHR Discriminator timing diagram optimization  Threshold non-uniformity reduction On-chip voltage regulator design for pixel clamping voltage  Interferences minimisation on critical nodes Zero suppression circuit (SuZe) adapted to STAR condition  Higher hit density  larger memories  Higher output frequency (80  160 MHz) Enhanced testability MIMOSA-22AHR

6. STAR IPHC isabelle.valin@ires.in2p3.fr 6 06/12/2010 Design Review ULTIMATE Design and Optimization (2) Functional block diagram Pixel array: 928 rows x 960 columns 20.7 µm square pixels Pre-amplification and CDS inside each pixel Column-level offset compensated discriminators Zero-suppression circuit Two output memories  Provided by the AMS foundry Frequency distribution:  Input LVDS clock at 160 MHz  All column are readout in parallel at 5 MHz 200 ns /row  (16 x 80 MHz)  Two LVDS sparsified data out at 160 MHz On-chip programmable bias-DACs via a JTAG controller Optional blocks (individuals test blocks)  Internal PLL at 10 MHz  On-chip voltage regulator for analogue power supply

7. STAR IPHC isabelle.valin@ires.in2p3.fr 7 06/12/2010 Design Review ULTIMATE Optimization of Pixel (1) Pixel Design  For binary readout, it is extremely important to have a correlated double sampling (CDS) and amplification inside pixel Reduced discriminators threshold variation Noise contribution from clamping voltage  Only NMOS transistors can be used in Pixel Any additional NWELL used to fabricate PMOS transistor would compete with sensing diode for charge collection  One need to obtain higher amplifier gain Maximized signal-to-noise ratio For standard common source amplifier, special biasing with transistor M3 for the load transistor M2  increased AC gain by about ~ 2  Adaptive feedback can be used to stabilize the operating point of the amplifier Working conditions garanteed for every pixel in changing temperatue, irradiation… Smaller variation of pedestals caused by the CMOS process parameters variation See Ref. A. Dorokhov et al., ULTIMATE Design Review Documentation, Part I, “Optimisation of Pixel Amplifier Design” 4 digital control signals per row: PWR_On, Slct_Row, Slct_Gr, Clamp  Slct_Row (16CK), PWR_On (2x16CK), Slct_Gr (16x16CK): power activate signals  Clamp: signal for CDS (3CK) 1 column split into 58 groups of 16 pixels  Reduced SW capacitances Current consumption: < ~ 60 µA/pixel N_Well Diode amplifier CDS Output Buffer

8. STAR IPHC isabelle.valin@ires.in2p3.fr 8 06/12/2010 Design Review ULTIMATE Optimization of Pixel (2) Pixel Optimization  Different pixel amplifiers and sensing diodes were implemented in MIMOSA-22AHR  The pixel layout is optimized to have better radiation tolerance The feedback transistor (M4) is replaced by its ELT variant Common source amplifierCascode amplifier Two stage amplifier Biasing via diode Two stage amplifier Biasing via transistor Amplifiers implemented in MIMOSA-22AHR (clamping not shown)

9. STAR IPHC isabelle.valin@ires.in2p3.fr 9 06/12/2010 Design Review ULTIMATE Optimization of Pixel (3) Different classes of amplifiers: 1.Cascode 2.Common source 3.two stage (source follower AC coupled to cascode) 4.amplifiers with load in source (without feedback) Geometry variation: 1.Nwell diode 2.Pitch 3.Length of transistors' gate 4.ELT transistors MIMOSA-22AHR contains: Different substrates: - epi layer of 14 µm and low resistivity (< 20 Ω.cm) - epi layer of 10, 15 and 20 µm and high resistivity (< 400 Ω.cm)

10. STAR IPHC isabelle.valin@ires.in2p3.fr 10 06/12/2010 Design Review ULTIMATE Optimization of Pixel (4) Calibration peak for different chips, implemented in different substrate, measured at different clock frequencies, temperatures and irradiation  S7 (blue line, common source) has quite small gain variation for all measurements compared to green line (cascode)

11. STAR IPHC isabelle.valin@ires.in2p3.fr 11 06/12/2010 Design Review Track reconstruction efficiency as function of fake hit rate, measured at 20C and 100 MHz Track reconstruction efficiency as function of fake hit rate, measured at 30C and 100 MHz Beam test results Optimized layout:  reduced parasitics and cross-talk MIMOSA-26 layout ULTIMATE Optimization of Pixel (5) Pixel schematic S7 has been chosen for ULTIMATE

12. STAR IPHC isabelle.valin@ires.in2p3.fr 12 06/12/2010 Design Review ULTIMATE Optimization of Discriminator (1) Discriminator design  Small input signal  Offset compensated amplifier stages  A/D conversion time = row readout time (200 ns)  Low current consumption ~ 70 µA/discri See Ref. Y. Degerli et al, IEEE, Trans. Nucl. Sci. vol.52, No. 6, pp. 3186-3193, Dec. 2005 During the RD phase: Sample the pixel signal (V RD ) and its offset voltage Sample the threshold voltage (VRef1) Sample the offset voltage of the gain stages A2 and A3 (both input offset and output offset storage) During the CALIB phase: Sample the pixel voltage (V CALIB ) and correct its offset Sample the common-mode voltage of the threshold voltage (VRef2) Amplify the signal (V RD -V CALIB ) and the threshold voltage (VRef1-VRef2) and feed to the latch During the LATCH phase: Compare the pixel signal (V RD -V CALIB ) to the threshold voltage (VRef1- VRef2), then give a logic level RD Vclp_d LATCH RD CALIB VRef1 VRef2 To Pixel Vclp_d RD LATCH Q Q A1A2A3 Column-level Double Sampling (DS)  reduce pixel to pixel dispersion (FPN) Pixel readout sequence

13. STAR IPHC isabelle.valin@ires.in2p3.fr 13 06/12/2010 Design Review ULTIMATE Optimization of Discriminator (2) discriminator 960 discriminators Pixel Array ~2 cm buffers Reference voltages (threshold) and clamping voltage are applied to 960 discriminators (~ 2 cm long)  Have to consider RC distribution line + successive charge rejections  Even an ideal source cannot provide stable references Need stable voltages during “RD“ and “CALIB” periods (~ 30 ns)   The discriminator row is divided into 4 groups  4 bias DACs to compensate process dispersions of discriminators See Ref. I.Valin et al., ULTIMATE Design Review Documentation, Part II, “Optimisation of Discriminator Design”

14. STAR IPHC isabelle.valin@ires.in2p3.fr 14 06/12/2010 Design Review ULTIMATE Optimization of Discriminator (3) Discriminator timing diagram optimisation  Threshold non-uniformity reduction Obtained timing diagram due to long track: - Mimosa26 test results: Threshold dispersion of 1152 discriminators (divided in 4 groups) - It doesn't disturb chip operation if threshold is set to be higher than the dispersion Due to the delay, ex. charge injections by S3, S4 cannot be compensated by the auto 0 phase No. of discriminators Ideal timing diagram: Optimised timing diagram: (validated by a proto) Sub-array/ Freq.=80 MHz TN (µV)FPN (µV) A422140 B401323 C398723 D404535

15. STAR IPHC isabelle.valin@ires.in2p3.fr 15 06/12/2010 Design Review ULTIMATE Optimization of Discriminator (4) Optimized discriminator timing diagram  Validated in the small prototype MIMOSA-22AHR 128 discriminators Additional functionality  RD signal is delayed of 3 ns compared to RD signal  No delay Threshold dispersion as a function of the discriminator number for three different pixel rows When RD signal is delayed compared to RD signal, the threshold dispersion can be reproduced in the small prototype In Ultimate sensor, the RD signal will be delayed compared to the RD signal to remove the systematic threshold dispersion

16. STAR IPHC isabelle.valin@ires.in2p3.fr 16 06/12/2010 Design Review ULTIMATE Auxilliary Functional Blocks (1) Bias synthetic block diagram On-chip programmable bias-DACs via a JTAG controller 8 bit current DAC  Range: 0 - 255 µA, Step= 1 µA  Good linearity Current Reference  IRef = 1 µA  PSRR VDDA < - 50 dB, Power consumption ~ 300 µA  Temp. variation = 7.3 nA/°C Reference voltages circuit for the discriminator  VRef2 DAC range: 0.5 V – 1.5 V, Step = 10 mV  VRef1 DAC range: -32 mV / +32 mV, Step = 250 µV On-chip voltage regulator for pixel clamping  Adjustable output voltage by an internal 4 bit DAC  No external compensation scheme LVDS Pads  LVDS transmitter Can be set at high impedance by JTAG access The current can be adjusted by DAC  LVDS receiver Can be disable by JTAG access The current can be adjusted by DAC Most of these blocks have already been implemented and tested in many successive chips as PHASE1, MIMOSA-26… See ULTIMATE Design Review Documentation, Part III, “Auxilliary Functional blocks”

17. STAR IPHC isabelle.valin@ires.in2p3.fr 17 06/12/2010 Design Review ULTIMATE Auxilliary Functional Blocks (2) Reference voltages circuit The VRef1 voltage is built from the VRef2 voltage  Reduced process dispersions Monte-Carlo simulation  Sigma of the threshold voltage (VRef1- VRef2) ~ 4 mV  Sigma of the threshold voltage after buffer ~ 7 mV  Near 100% of the chips could be adjustable by the DAC

18. STAR IPHC isabelle.valin@ires.in2p3.fr 18 06/12/2010 Design Review ULTIMATE Auxilliary Functional Blocks (3) Schematic of regulator INT_LN : Low Dropout (Vin = 3 - 3.3 V) Characteristics: Dropout voltage: ~ 0.3V, PSRR: ~ 40 dB, Noise: < 1 µV/sqrt(Hz) (at 10 KHz), Power consumption: <~ 1mW Absolute noise contribution from buffer as a function of pixel noise with external Vcl The voltage Vcl can be supplied externally (EXT) or generated in the chip On-chip voltage regulators for pixel clamping have been implemented in MIMOSA22-AHR  Two different versions of circuits have been tested: INT and INT_LN  The contribution if noise from internal buffer has small value (<10%) and can be reduced using filter capacitance of few nF (estimated parasitic capacitance on the Vcl line) ENC for different amplifier structures (S#)

19. STAR IPHC isabelle.valin@ires.in2p3.fr 19 06/12/2010 Design Review ULTIMATE Analog Characterization Mode 1: Analog readout of entire matrix at low frequency (20 MHz)  The matrix is divided in stripes of 8 columns and fully scanned at each frame, then swapped with the next block of 8 columns at right and so on until all the columns are analyzed. Mode 2: Analog readout of 8 pre- selected columns at nominal speed (80 MHz)  8 pre-selected columns are chosen in the middle of the chip and connected directly to the 8 output pads. 8 output pads

20. STAR IPHC isabelle.valin@ires.in2p3.fr 20 06/12/2010 Design Review Summary The design of ULTIMATE has been optimized:  Pixel design (schematic + layout): cross-talk, parasitic capacitances, radiation tolerance beam-test and lab test to choose the optimal version  Discriminator timing diagram: Reduced threshold dispersion  Digital control circuit: power consumption speed Design Status:  Simulation of all blocks performed and functionalities verified  Schematic and Layout: DRC and LVS passed  Mixed-Simulation to verify whole chip (Analogue + Digital Part)  Layout parasitic extraction to estimate possible degradation in worst case due to under estimated parasitic interconnects between blocks In case of not sufficient performance, interconnect will be easily optimized to finalize the chip  Preliminary verification (DRC and Size for fabrication) made by CMP Submission Plan:  The 9 th of December: Modifications following the common design review recommandations  Until the 17th of December: Verification at IPHC and at CMP  From 18th of December to 3nd of January: Laboratory is officially closed  Until the 14th of January: Verification  The 17th of January: Submission

21. STAR IPHC isabelle.valin@ires.in2p3.fr 21 06/12/2010 Design Review BACKUP

22. STAR IPHC isabelle.valin@ires.in2p3.fr 22 06/12/2010 Design Review Actual Status Functional verification full chip Analog block

23. STAR IPHC isabelle.valin@ires.in2p3.fr 23 06/12/2010 Design Review Power Dissipation M26Current A170 mA D60 mA LVDS20 mA Pixel pitch (µm) PixelsDiscrisBuffer Ref. DACDigitalLVDSTotalPower (mW/cm 2 ) 20.7 (960 col.) At 3 V 57.6 mA67.2 mA18 mA7 mA50 mA20 mA 170 mW200 mW50 mW20 mW150 mW60 mW*650140 Chip area: 4.6 cm 2 *4 transmitters, 1 receiver ULTIMATECurrent A142 mA D50 mA LVDS20 mA Total current: 212 mA 152 mW/cm 2 at 3.3 V 138 mW/cm 2 at 3.0 V

24. STAR IPHC isabelle.valin@ires.in2p3.fr 24 06/12/2010 Design Review MIMOSA-22AHR

25. STAR IPHC isabelle.valin@ires.in2p3.fr 25 06/12/2010 Design Review Discriminator

26. STAR IPHC isabelle.valin@ires.in2p3.fr 26 06/12/2010 Design Review Discriminator Moderate gain ~ 4 Well defined output common-mode non linear gain Dynamic latch No static power consumption Good speed, switching time ~ 2ns Dedicated lines and pads for the supply and ground voltages

27. STAR IPHC isabelle.valin@ires.in2p3.fr 27 06/12/2010 Design Review Current Reference

28. STAR IPHC isabelle.valin@ires.in2p3.fr 28 06/12/2010 Design Review Reference Voltages Circuit

29. STAR IPHC isabelle.valin@ires.in2p3.fr 29 06/12/2010 Design Review LVDS Transmitter

30. STAR IPHC isabelle.valin@ires.in2p3.fr 30 06/12/2010 Design Review LVDS Transmitter Processtmwswp Delay (ns)1.451.871.10 Duty cycle (%)49.8/50.249.5/50.549.9/50.1 Current consumption (mA)4.645.9 Common-mode voltage(V)1.1841.1821.1715 Differential swing (mV)+/- 300+/- 265+/- 400 Main characteristic in nominal condition T= 30°C, VDD = 3V, ilvds_tx= 40 µA, Cload = 10 pF)

31. STAR IPHC isabelle.valin@ires.in2p3.fr 31 06/12/2010 Design Review Nominal condition, T= 30°C, VDD=3V, tm, Vdiffpp = 200 mV, vcm = 1.2 V T= 125°C, VDD = 2.7 V, Vdiffpp = 200 mV Nominal condition30 °C, 3V, tm Ilvds_rx (#UDAC) (µA)32 Rise time (ns)0.89 Fall time (ns)0.60 Delay (ns)2.5 Duty-cycle (%)52-48 Vhyst (mV)29.4 processtmwswp Ilvds_rx (#UDAC) (µA)222122 Vhyst (mV)32.83729.2 Duty-cycle (%)46-5449-5150-50 Delay (ns)3.454.322.4 Range of vcm (V)0.5-2.20.85-1.90.25-2.4 LVDS Receiver