1. Introduction ENGIN 341 – Advanced Digital Design
University of Massachusetts Boston
Department of Engineering
Dr. Filip Cuckov

2. Overview
Administrative
Objectives
Grading
Schedule

3. 1. Administrative Professor Catalog Description:
Dr. Filip Čučkov (Dr. Phillip CHOOCH-kohv, OR Dr. C)
Office: Science Center, 3rd floor, room 111
Office Hours: Regular weekly and by appointment
Phone: (617)
Catalog Description:
The course will cover topics including tools and methodologies for top-down design of complex digital systems. Important topics include minimization, mixed logic, algorithmic state machines, microprogrammed controllers, creating and using a gold model, data and control path design, and data movement and routing via buses. Design methodologies covered include managing the design process from concept to implementation, gold model validation, and introduction to design flow. A hardware description language is used extensively to demonstrate models and methodologies, and is also used in design exercises and projects.

4. 1. Administrative Prerequisites: ENGIN 241 – Digital Systems with Lab
Textbooks:
Charles H. Roth Jr. and Lizzy K. John, Digital Systems Design Using VHDL, 2008
ISBN-13: (Publisher Link) (Amazon)
Reference:
B. Mealy, F. Tappero, Free Range VDHL, freerangefactory.org, 2013
Complementary download at
Website(s):
(BlackBoard)

5. 1. Administrative - Honor Code
All work is individual.
Give credit where credit is due.
Cheating will not be tolerated.
There will be no second chances.
I pledge to uphold the governing principles of the Code of Student Conduct of the University of Massachusetts Boston. I will refrain from any form of academic dishonesty or deception, cheating, and plagiarism. I pledge that all the work submitted here is my own, and that I have clearly acknowledged and referenced other people’s work. I am aware that it is my responsibility to turn in other students who have committed an act of academic dishonesty; and if I do not, then I am in violation of the Code. I will report to formal proceedings if summoned.

6. 2. Objectives Course Learning Objectives:
Develop proficiency in modeling and digital systems with VHDL
Understand mixed logic design, flip-flop design, SOP and POS forms, and state minimization
Design using algorithmic state machine methods
Controller design using structured design approaches including one-hot and microcoded controllers
Modeling datapath components including registers, counters, ALUs
Create datapath to model complex digital systems
Control path design
Introduction to FPGA design flow
Introduction to system modeling flow and tools

7. 2. Objectives - Topics Covered
Review of Logic Design Fundamentals
Introduction to VHDL
Introduction to Programmable Logic Devices
Design Examples
State Machine Charts and Microprogramming
Designing with FPGAs
Floating-Point Arithmetic
Additional Topics in VHDL
Design of a RISC Microprocessor

8. 3. Grading 10 % Homework Assignments 90 % Labs
2 Homeworks
Each worth 5%
90 % Labs
Labs 1-7
Each worth 10%
Labs 8 and 9
Worth 20% but require only one lab report
Demo required during final exam time
Each lab graded on the following scale:
60% Lab Completion
May include preliminary work or demonstration
40% Lab Report
Must follow required format

9. 4. Schedule Date Class Lecture Assignment Due Reading Assigned Lab
Concepts Practiced
Exercise
9/8/2015 1
Introduction and Digital Systems Design Overview
RJ: (3,6), 2.3, 2.4
FR: 2, 3
FPGA Design Flow
L0 - Design Flow
9/15/2015 2
VHDL - Dataflow and Structural Modeling, Testbenches
HW 1
RJ ,
VHDL Structural Modeling and Functional Simulation
L1 - Modular Design and Testbenches
9/22/2015 3
VHDL - Processes, Data Types and Operators, Synthesis
L1 Report
RJ 2.8, 2.9,
Simple combinational circuit design
L2 - ALU Design
9/29/2015 4
VHDL - Behavioral Modeling and Registered Elements
L2 Report
RJ 1.9, 5
Simple sequential circuit design
L3 - Hexadecimal Counter
10/6/2015 5
ASM Charts, Minimization and Microporgramming
L3 Report
RJ 7
Algorithmic State Machines
L4 - Traffic Light Controller
10/13/2015 6
Floating Point Arithmetic
L4 Report
RJ 11.3
10/20/2015 7
Standard System Interfacing and Comm. Protocols
HW 2
RJ 8
Datapath/Controller Design and SPI Communication
L5 - Standard Peripheral Interfacing
10/27/2015 8
VHDL - Functions, Procedures and Libraries
RJ 11.2
11/3/2015 9
VHDL - System and Memory Modeling
L5 Report
Using Block RAM in FPGAs
L6 - Stack Calculator
11/10/2015 10
VHDL - Advanced Tesbenches
RJ 10
11/17/2015 11
Hardware Testing and Design for Testability
L6 Report
Understanding BIST and JTAG
L7 - Memory Built-In Self Test
11/24/2015 12
RISC Microprocessor Design - ISA
L7 Report
L8 - MIPS Processor 1
12/1/2015 13
RISC Microprocessor Design - Datapath and Controller
Text I/O in VHDL
12/8/2015 14
RISC Microprocessor Design - Testing and Validation
Microprocessor Design
L9 - MIPS Processor 2
Final Exam
Demonstrations of MIPS Processor
Final (L8+L9) Rep.
Map: RJ - Roth and John Textbook, FR - Free Range VHDL Textbook, (Light Reading)