1. A holistic Pre-to-Post solution for Post-Si validation of SoC’s Yael Abarbanel yael.abarbanel@intel.com yael.abarbanel@intel.com Eli Singerman eli.singerman@intel.com eli.singerman@intel.com Sean Baartmans sean.baartmans@intel.com sean.baartmans@intel.com DAC 2011 User Track

2. 2Yael Abarbanel. DAC 2011. User Track Problem Statement Post Silicon functional validation consumes an increasing share of the overall product development timeline. Post Silicon functional validation consumes an increasing share of the overall product development timeline. The problem is getting more critical in SoC designs due to requirements for diminishing time-to-market. The problem is getting more critical in SoC designs due to requirements for diminishing time-to-market. The vast majority of solutions for SoC validation focus on IP reuse in the pre-silicon stage. The vast majority of solutions for SoC validation focus on IP reuse in the pre-silicon stage. Most solutions focus only on a single aspect and do not promote leverage of pre-Si efforts by post-Si. Most solutions focus only on a single aspect and do not promote leverage of pre-Si efforts by post-Si.

3. 3Yael Abarbanel. DAC 2011. User Track Solution Direction Consider the entirety of the product development process. Consider the entirety of the product development process. Invest efforts in pre-Si to reduce post-Si schedule: Invest efforts in pre-Si to reduce post-Si schedule: –Invest in design for debug (DFx) to make important system behaviors observable. –Invest in test suites optimization to yield coverage on important system behaviors. –Utilize DFx and optimized test suite for effective post- Si debug and coverage. Observe important system behaviors in Silicon.

4. 4Yael Abarbanel. DAC 2011. User Track Pre2post Flow Transaction & Event Spec Repository Test Suite Optimization DFx Insertion Optimized Test Suite Design with DFx Instrumentation Post Silicon Coverage and Debug PrePost

5. 5Yael Abarbanel. DAC 2011. User Track Transactions/Events Repository A unified uArch spec that binds all stages. A unified uArch spec that binds all stages. Includes definitions of system events / transactions for each individual IP and for the entire SoC. Includes definitions of system events / transactions for each individual IP and for the entire SoC. Created at very early definition stages by SoC’s architects and IP providers. Created at very early definition stages by SoC’s architects and IP providers. Stored in a central repository that is visible to all. Stored in a central repository that is visible to all. These are the important system behaviors I need to observe in silicon

6. 6Yael Abarbanel. DAC 2011. User Track Transactions/Events Repository Transaction & Event Spec Events Explorer Transaction Graph

7. 7Yael Abarbanel. DAC 2011. User Track Transaction Driven Test Suite Optimization A tool that optimizes test suites to effectively exercise transactions / events (considering test duration, coverage yield, etc.) Utilizes mathematical techniques based on functional coverage yield. Utilizes mathematical techniques based on functional coverage yield. Uses emulation to prepare the optimized test suite. Uses emulation to prepare the optimized test suite. Reduce redundancy in test suites. Reduce redundancy in test suites. –Reduce debug efforts. Lower the chances to debug the same failure in different tests. Optimize my test suite to effectively exercise these events

8. 8Yael Abarbanel. DAC 2011. User Track Transaction Driven Test Suite Optimization Keep tests that uniquely cover a system behaviors Alert on un-covered system behavior

9. 9Yael Abarbanel. DAC 2011. User Track Transaction Driven DFx Insertion A tool that inserts DFx instrumentation to make transactions / events observable in Silicon. Helps the user identifying key transactions / events. Helps the user identifying key transactions / events. Optimizes DFx instrumentation making large set of transactions & events visible. Optimizes DFx instrumentation making large set of transactions & events visible. Takes into accounts the limited HW resources on Silicon. Takes into accounts the limited HW resources on Silicon. Uses a comprehensive architecture (of Intel SoCs) for modular silicon DFx features. Uses a comprehensive architecture (of Intel SoCs) for modular silicon DFx features. Insert DFx instrumentation so I can observe these transactions in silicon.

10. 10Yael Abarbanel. DAC 2011. User Track Transaction Driven DFx Insertion Transaction Graph Transaction & Events Spec Inserted DFx instrumentation for transaction observation Spec

11. 11Yael Abarbanel. DAC 2011. User Track Post-Si Debug and Coverage We reap the harvest of our investment in pre-Si stages. Utilize DFx  Effectively observe important system behaviors in Silicon Utilize DFx  Effectively observe important system behaviors in Silicon –Automatically compile transactions spec into sophisticated DFx configuration, making it observable. Utilize Test Suite  Effectively hit the desired system behaviors in Silicon Utilize Test Suite  Effectively hit the desired system behaviors in Silicon Utilize Spec  Effectively analyze Silicon traces Utilize Spec  Effectively analyze Silicon traces –Automatically abstract Silicon traces from signals level to transactions level. Increment a counter when this event occurs. Identify transactions in my Si trace. Start capture silicon trace when this event occurs.

12. 12Yael Abarbanel. DAC 2011. User Track Results The set of tools operate in the unified pre2post flow. The set of tools operate in the unified pre2post flow. Thousands of events & transactions were defined for multiple SoC’s (reusing definitions from each other). Thousands of events & transactions were defined for multiple SoC’s (reusing definitions from each other). The ‘transaction driven DFx instrumentation’ ensures observability of important system behaviors in Silicon. The ‘transaction driven DFx instrumentation’ ensures observability of important system behaviors in Silicon. –Identified missing DFx comparing to previous SoC. The test suite optimization flow reduced the original test suite by 50% between two post silicon steppings. The test suite optimization flow reduced the original test suite by 50% between two post silicon steppings. Productivity in Silicon debug & coverage improved thanks to the abstraction and automation. Productivity in Silicon debug & coverage improved thanks to the abstraction and automation. Main CPU’s (non SoC) adopted this approach. Main CPU’s (non SoC) adopted this approach.

13. 13Yael Abarbanel. DAC 2011. User Track Looking Forward EDA industry and academic researchers can play an important role in strengthening the current approach. For example: EDA industry and academic researchers can play an important role in strengthening the current approach. For example: –Suggest advanced techniques for test suite optimization. –Propose architectures for (configurable) DFx structures that optimize HW resource utilization and maximize the observability of system events & transactions. We plan to deploy the events/transactions approach in pre-Si activities as well. We plan to deploy the events/transactions approach in pre-Si activities as well.

14. 14Yael Abarbanel. DAC 2011. User Track Summary A central transactions & events spec serves as a common theme across pre-Si and post-Si activities. A central transactions & events spec serves as a common theme across pre-Si and post-Si activities. The spec guides DFx instrumentation and test suite preparation in Pre-Si to make Post-Si validation effective. The spec guides DFx instrumentation and test suite preparation in Pre-Si to make Post-Si validation effective. Post-Si debug & coverage becomes ‘abstract’: Post-Si debug & coverage becomes ‘abstract’: –Productive, manageable, reusable, readable, and less error prone. Transaction & Event Spec Test Suite Optimization DFx Instrumentation Post Silicon Coverage and Debug