1. The FVTX Technology Outline Overall Picture Silicon Detector
Geometry, Layout, Process
Readout Chip
FNAL Chips, New Chip PHX
Detector Module
Wedges, Lampshades
Data Path
FPGA Interface Board
Concept, Potential Implementation
Overview on R&D Issues
Summary
Gerd J. Kunde - LANL

2. FVTX Tracker Executive Summary
Four lampshade stations on each side
Mini-strips of 50 micron radial pitch: mm
Readout via new PHX chip from Fermi Nat’l Lab
Total strip count: ~ 2 * 860,000 strips (zero suppressed)
Total chip count: ~ 2 * 1680 chips
Total silicon area: ~ 2 *3350 cm2
Gerd J. Kunde - LANL

3. The Inner Volume of Phenix
78 cm
66 cm
45 cm
Mechanical Design for VTX and FVTX by LANL & Hytec
Gerd J. Kunde - LANL

4. Current VTX & FVTX Specifications
Barrel Section
i-radius
length
strips/pixel
layer 1
2.5 cm
21.8 cm
pixel
layer 2
5 cm
layer 3
10 cm
31.8 cm
strip
layer 4
14 cm
38.2 cm
1.2%
2.0%
ministrip
18 cm
38 cm
station 4
32 cm
station 3
10.6cm
26 cm
station 2
6.6 cm
20 cm
station 1
tilt = 22 deg
o-radius
z-start(+-)
Endcap (north and south)
Rad.
Length
1 %
Gerd J. Kunde - LANL

5. FVTX Part of VERTEX Spreadsheet
Gerd J. Kunde - LANL

6. Silicon Detector Technical Overview
200 micron thickness
50 micron radial pitch (z reconstruction)
curved or straight strips ? (R&D)
1280,2048,2816 “mini-strips”
3.5 cm < r < 18 cm
< 1.5 % occupancy (central AA)
48 “double towers” in phi
mini-strips from
13.0 mm
to 2.2 mm
readout via PHX 5,8,11 chip row
r = 18.0 cm
2816
2048
1280
r = 3.5 cm 1
PHX derived from FNAL chips
Gerd J. Kunde - LANL

7. Only “2 ½” Silicon Detector types
50 micron strips (collaboration with Prague groups)
Outside Detector (II)
Inside Detector (I)
Outside Detector (III)
5 chips= 1280 * 2 strips
706.2 mm^2
6 chips= 1536 * 2 strips
mm^2
3 chips= 768 * 2 strips
752.0 mm^2
Gerd J. Kunde - LANL

8. Two Silicon Wafer Layout Concepts
n+ pixels on n substrate using “moderated p-spray” as the n-isolation technology
Proven ATLAS/BTev technology with existing qualified vendors
We assume 4 inch um wafers, the layout is matching the need of inner and outer detectors:
Inner: 77 wafers + contingency
Outer: 96 wafers + contingency
Gerd J. Kunde - LANL

9. Silicon Sensor Schedule
Gerd J. Kunde - LANL

10. Existing FNAL Chip: FPIX2.1 Features
Advanced mixed analog/digital design
128 rows x 22 columns (2816 channels)
50 µm x 400 µm pixels
High speed readout intended for use in Level 1 trigger. Up to 840 Mbits/sec data output.
Very low noise, excellent threshold matching
DC coupled input
Fully programmable device
Output directly drives long cable (10 m, 30 feet)
90 mirco watt/pixel
(~0.25 watt/chip)
Rad hard to 50 Mrads
Change geometry for PHX-chip and
adjust analog front end to mini-strips capacity
Gerd J. Kunde - LANL

11. FPIX 2.1 Pixel Circuit (50 x 400 µm)
FPIX2: 60 e-rms measured c=0 pf
3 bit
ADC
Signal/Noise ~ 50/1
Threshold/Noise ~ 10/1
for mini-strips on 200 um Si
PHX Simulation
2 mm to 10 mm strip length
Gerd J. Kunde - LANL

12. FPIX 2 Module: “Real” Threshold and Noise
CHIP 4
CHIP 4
These are typical distribution curves for threshold and noise for a real chip on an 8 chip HDI.
(A mip gives 16,000 electrons in 200 micron)
Gerd J. Kunde - LANL

13. Measured FPIX 2 Power Consumption
The power consumption of the 8 chip module is:
for (VD=VA=2.5V)
1.86W Module idle.
2.26W Module collecting data.*  100 micro watt/channel
for (VD=VA=2.2V)
1.51W Module idle.
1.83W Module collecting data.*  80 micro watt/channel
* 8 chip module collecting data at 300Mbps.
The power consumption variation due temperature change (delta=100ºC) was less than 0.05 W.
Gerd J. Kunde - LANL

14. 512 bumps plus inter-chip bumps ~ 15 wafers needed
signals & power
FNAL Collaboration
Ray Yarema’s group
Bump bonds
Programming interface
Discriminator
Pipeline
Digital interface
PHX Chip Layout:
2 columns
256 channels/column
3.8 mm x 13 mm = 49.4 mm2
Thinned to 150 to 200 um
Bump bonds on 200 um pitch
50 µm dia solder bumps
512 bumps plus inter-chip bumps
~ 15 wafers needed
Keep all digital backend the same ! Adjust only input and geometry, optimize the row/column structure for readout speed and add pulser.
Bus on chip ?
Gerd J. Kunde - LANL

15. PHX Bus R&D FNAL Proposal: Power & Data Bus on Chip PHX PHX
Kapton
FNAL Proposal: Power & Data Bus on Chip
Kapton
PHX
PHX
200 um Silicon Detector
Preliminary calculations by R.Yarema show that the I-R loss is acceptable, need optimize number of signal lines per chip
R&D necessary …. fallback solution is
Flex Cable with Wire Bonding
Gerd J. Kunde - LANL

16. ~3400 chips but only 80 Watts per Endcap
FVTX Power
Numbers added for both sides !
~3400 chips but only 80 Watts per Endcap
Gerd J. Kunde - LANL

17. PHX Chip Development Schedule
Gerd J. Kunde - LANL

18. FVTX Wedge Assembly 2 silicons in front
3 mm carbon wedge for assembly and cooling
2 silicons in back
Eliminate dead silicon areas by overlapping 1 mm along edges ….
Carbon Fiber Support and Cooling
Gerd J. Kunde - LANL

19. From Wedges to Lampshades
X 24
Total strip count: ~ 2 * 860,000 strips
Total chip count: ~ 2 * chips
Total silicon area: ~ 2 * cm2
Gerd J. Kunde - LANL

20. FVTX Connections Copper Flex (Fiber)
5 x 512 channels
Fiber 4 Gbit/s
Slow Control ~100 Hz
Serializer
Optical Driver
48 per station
48 per station
Copper Cables
Copper Bus
61 LVDS Pairs
LVDS 4
x MBit
Hit: 9 bit address ,3 bit adc, 4 bit chip-id, tag 8bit => 24 bits
6 x 512 channels
5 x 512 channels
R&D Project: Flex Cables or Fiber to the ‘outside world’ ?
Space Constraints (see W.Sondheim)
Costs/Complexity/Reliability
Serializer/Fiber Collaboration ?
Gerd J. Kunde - LANL

21. FVTX Copper Connection Wire Count
D.Christian Slide
FVTX Copper Connection Wire Count
Per wedge: 6x2=12 wires
BCO clock
Shift In
Shift Out
Shift Control
Reset MC
Per chip:
Data out (x1,2,4,6)
DLCLK
11 chips/wedge… assume we use DLCLK:
1 serial pair/chip: 6 pairs+11x2 pairs = 28 pairs
2 serial pairs/chip: 6 pairs + 11x3 pairs = 39 pairs
4 serial pairs/chip: 6 pairs + 11x5 pairs = 61 pairs
Power and Bias
‘Round Cable’ ala CDF/D0
Gerd J. Kunde - LANL

22. Board(green) and fiber optic connector(orange)
FVTX Connections III
Board(green) and fiber optic connector(orange)
12 fibers per connector
160 mm
30mm
24 Fiber MPO Connector (x8)
Samtech QSS-RA mm pitch Connector (7mmx54mm)
R&D Project: Flex Cables or Fibers the ‘outside world’ ?
Space Constraints (see W.Sondheim)
Gerd J. Kunde - LANL

23. Electronics Readout Concept
Event Tag
chip download
Driver
(buffer)
FPGA
PHENIX DCM
Copper
~140 Mbits/s
Data out
<1.5 % Occupancy in AA central
Level 1 possible
fiber
copper
Level 1 Accept
PHX/FPIX2 is zero suppressed !!!
To Level 1 trigger
processor
T&FC
Fvtx Interface Board
Slow
controls
In Detector
In Counting House
Gerd J. Kunde - LANL

24. R&D on Data Acquisition
(Number of Readout Lines, Clock Speed & FPGA Memory)
Layers Ganged
channels/chip
chips/ board
channels/ board
Occupancy
Interactions/ 64 clocks
Real Hits/ 64 Clocks
Real data size/64 clocks (kbits)
Noise
Clocks
Noise Hits/ 64 Clocks
Noise data size/64 clocks (kbits)
Buffer needed for 64 clocks (kbits)
Number of Readout Lines
Readout Time/data word (nsec)
Readout Latency (beam clocks)
Noise Hits/chip needed to Fall Behind
Noise Rate/chip
Readout Clock Speed (Mbps) 1
512 11
5632
0.015
84.48
2.03
0.001 64
360.4
8.7
10.7
212.4
17.4
0.5
113 4 44
22528
337.92
8.11
1441.8
34.6
42.7 2
106.2
0.9
35.3
2.9
2.8
169.8 6
35.4
R & D has started under LANL DR grant
First FVTX readout meeting (Columbia/ISU/LANL) held 12/5/2005 at BNL
Gerd J. Kunde - LANL

25. FVTX DAQ INTERFACE BOARD Conventional Copper Cable
Serial download to chips
Pass beam clock
Initialize/Reset
Arcnet (FPGA program., chip download)
T+FC
On Silicon
11?, 41?/FPGA
Trigger?
Near Silicon
Outside IR
Conventional Copper Cable
or Serializer/Optical Driver
Data Buffer, FPGA
Time to process=?
DCM
2.5 Gb/s
PHX
1,2,4,(6) lines/chip
Stream of 24-bit data words with:
Location
(3 bit ADC)
Beam Clock Counter
140Mbps readout lines can drive 10 m
Uses custom or commercial driver
Buffers Data
Upon lvl1 grab relevant data
Build packet
DataDCM/Lvl1
Pass beam clock
Initialize chips
PHENIX Standard
ISU Level 1 Board (SBIR)
New development of FIB and firmware (Columbia/LANL)
Gerd J. Kunde - LANL

26. The FIB Concept (FVTX Interface Board) (with input from Chi,FNAL + Columbia)
Gerd J. Kunde - LANL

27. FVTX Research & Development
Silicon Detector
Adapt/modify existing design
Straight or curved strips
PHX Chip
Low risk modification of existing design
Analog input, row/column structure, pulser
New development
Bus on chip
Interfacing
Flex copper cables or Fibers
R&D
Transition Board
FVTX Interface Board (FIB) and firmware
DAQ/Slow Control
Mechanics/Cooling integrated in VTX solution
See W. Sondheim’s presentation
Gerd J. Kunde - LANL

28. FVTX Summary
North and South: 4 Station Precision Silicon Tracker for the Muon Arms
BTeV (ATLAS) Technology for Detector and Readout Chip
R&D Schedule (needs to start now)
FVTX (DAQ) Interface Board with FPGA and Firmware
R &D started under LANL grant
Collaboration with Columbia/ISU
Mechanics covered in next talk
Detailed Schedule in Dave’s talk
Gerd J. Kunde - LANL

29. BACKUP Slides on the FVTX
Gerd J. Kunde - LANL

30. FNAL Chip Comparison Chip All 50 µm spacing Noise Threshold σ
Ministrip
Readout type
speed
Trigger possible
Power
per chan
Geometry r-phi
SVX4
128 ch
S/N -12/1
yes
Pipeline
53 MHz no
2mW
FSSR
250 e
440 e
Data push
840 Mb
3 mW
Yes
FPIX3
2816 ch
220 e
125 e
Data Push
90 µW
PHX
512 ch
125e
Signal e for 300 µm Si Sensor, thinning desirable for small material budget
Gerd J. Kunde - LANL

31. FPIX2.1 Pixel Cells 50 x 400 um Preamp 2nd stage +disc Kill/ inject
R.Yarema Slide
FPIX2.1 Pixel Cells 50 x 400 um
12 µm bump pads
Preamp
2nd stage
+disc
Kill/
inject
ADC
encoder
Digital interface
ADC
Gerd J. Kunde - LANL

32. Power Considerations Must minimize IR drops
R.Yarema Slide
Power Considerations
Must minimize IR drops
Reduce number of chips on bus
Design full custom low power analog and digital sections
Maximize power bus size on chip
Use back side contact
Possibly use cooling structure for ground return
Gerd J. Kunde - LANL

33. Voltage Drop Estimation
R.Yarema Slide
Voltage Drop Estimation
Units are connected as shown
Each unit consumes current
What is the IR drop at the output of the last unit?
n identical units
Gerd J. Kunde - LANL

34. Runit Estimation (one chip is a unit)
R.Yarema Slide
Runit Estimation (one chip is a unit)
Gerd J. Kunde - LANL

35. FPIX2 uses 60mA of Analog Current and 60mA of Digital Current.
R.Yarema Slide
Iunit Estimation
FPIX2 uses 60mA of Analog Current and 60mA of Digital Current.
It is fairly accurate to use the FPIX2 Analog Current as an estimation of the Phoenix Mini Strip Analog Current.
It is conservative to use the FPIX2 Digital Current as an estimation of the Phoenix Mini Strip Digital Current
Phenix Mini Strip will not read out at 840MBits/sec
Phenix Mini Strip will not have as many inputs and outputs
Gerd J. Kunde - LANL

36. R.Yarema Slide
Iunit Estimation
Gerd J. Kunde - LANL

37. ΔV Estimation Full Tower -OR- Split Tower Inner Segment Outer Segment
R.Yarema Slide
ΔV Estimation
Full Tower
-OR-
Split Tower
Inner Segment
Outer Segment
Gerd J. Kunde - LANL

38. Noise Performance of FPIX2 at Higher Detector Capacitance
R.Yarema Slide
Noise Performance of FPIX2 at Higher Detector Capacitance
Gerd J. Kunde - LANL

39. Phenix Chip Analog Input Simulations
R.Yarema Slide
Phenix Chip Analog Input Simulations
Simulated
FPIX2 first and second stage response for detector capacitances
from 0 to 2 pF in 0.25 pF steps
First stage
Second stage
Gerd J. Kunde - LANL

40. Phenix Chip Analog Simulations
R.Yarema Slide
Phenix Chip Analog Simulations
Simulated 1st and 2 nd stage
risetime (10-90%) with
different detector capacitance
First stage
Second stage
Gerd J. Kunde - LANL

41. Phenix Chip I/O Ideas R.Yarema Slide
Separate analog and digital power buses
Should operate over wide power supply range (due to IR drops)
Common backside ground
Clocks
Input clock – 100 ns
Separate readout clock?
Serial programming interface input
Serial data output
Chip ID
Cell number?
Channel ID
Trigger input
Control line(s)
Gerd J. Kunde - LANL

42. FPIX2 noise at C = 0 is about 60 erms
FPIX2 Threshold Cin= 0 pf is 125 erms
R.Yarema Slide
FPIX2 on the Bench Measurements
FPIX2 noise at C = 0 is about 60 erms
Gerd J. Kunde - LANL

43. Pixel/Strip Sizes and Capacity
R.Yarema Slide
Pixel/Strip Sizes and Capacity
FPIX 50 x 400 um Cin = .25 pF
Phenix 50 x 2000 to um Cin = pF
SVX 50 x 105 to 3x105 um Cin = pF
Design for Phenix should be optimized for
correct detector capacitance
Gerd J. Kunde - LANL

44. First Simulations for PHX Chip at FNAL
R.Yarema Slide
First Simulations for PHX Chip at FNAL
First stage
Second stage
Simulated
FPIX2 first and second stage response for detector capacitances
from 0 to 2 pF in 0.25 pF steps
Gerd J. Kunde - LANL

45. Possible Layout Diagram for PHX Chip
R.Yarema Slide
Possible Layout Diagram for PHX Chip
Bump bonds
Programming interface
1st and 2nd stage and discriminator
Pipeline
Digital interface
Gerd J. Kunde - LANL

46. BACKUP Slides on the iFVTX
Gerd J. Kunde - LANL

47. The Inclusive (Measurement ) FVTX aka iFVTX
sponsored by LANL-DR in FY ‘06-08
Inclusive Heavy Quark Measurement in A-A
4 planes
Existing Chips FPIX 2.1
Existing 8 Chip Modules
Prototype FPGA Readout
Gerd J. Kunde - LANL

48. Aligned with Sweet Spot of Muon Half-Octant
iFVTX
Aligned with Sweet Spot of Muon Half-Octant
Constraints by barrel
Same Volume as FVTX
Enclosure
Half-Octant
Gerd J. Kunde - LANL

49. BTeV-Sensors at FNAL Each wafer contains: 1 “4-chip” module
G.Cardoso Slide
BTeV-Sensors at FNAL
Individual pixels are identical to ATLAS sensors.
Number of rows & columns and overall size customized for BTeV.
Oxygenated “moderated p-spray”
n+-in-n sensors made by TESLA
Each wafer contains:
1 “4-chip” module
3 “6-chip” modules
3 “5-chip” modules
2 “8-chip” modules
These are the modules used in the baseline design; number on wafer chosen to reflect usage.
5 “1-chip” sensors
Gerd J. Kunde - LANL

50. 8 Chip Module HDI designed by Fermilab/CD made by Dyconex:
G.Cardoso Slide
8 Chip Module
HDI designed by Fermilab/CD made by Dyconex:
Dimensions: 111.0mm x 11.1mm + 2x 10.0mm x 11.1 mm tabs
Line width: 50m
Line to line clearance: 50m
Metal layer thickness: 12m
Number of layers: 4
Via pad/hole: 150/70m
Lamination: 25m epoxy
Film thickness (polymide): 50m
HDI CAD top layer.
HDI + 8 bare die chips.
HDI + 8 chips with detector.
(SINTEF PSPRAY)
Gerd J. Kunde - LANL

51. G.Cardoso Slide
LANL R&D Collaboration with FNAL to get Multichip Modules in January 2006
This is a photograph !
HDI TEST CARD
1 Silicon with 8 readout chips on HDI Silicon from TESLA (Czech Republic)
Gerd J. Kunde - LANL

52. HDI to PIFC wire-bonding
G.Cardoso Slide
HDI to PIFC wire-bonding …
11.1mm
8.53mm
200um
1.47mm
1mm
Data and control LV
HV pad
DVDD&GND
AVDD&GND
Power PIFC
Data PIFC
Gerd J. Kunde - LANL

53. BTeV Pixel - Flex Cross Section
G.Cardoso Slide
BTeV Pixel - Flex Cross Section
4 Layer Flex Circuit Cross Section
Silicon Sensor
Adhesive
Layer 3
Layer 2
Bias Window
Gold Epoxy
Metal Layer 4
Metal Layer 3
Metal Layer 2
Metal Layer 1
Analog
Digital
Digital lines
Ground
High Voltage
Flex Circuit
Analog lines
Layer 1
Bias Pad (1mm 2 )
Gerd J. Kunde - LANL

54. Pixel Multichip Module – Baseline Design
G.Cardoso Slide
Pixel Multichip Module – Baseline Design
Gerd J. Kunde - LANL

55. Prototype pixel module
G.Cardoso Slide
Prototype pixel module
FPIX2
Silicon Sensor
HDI
Support Structure
Wire bonds
NOT TO SCALE
Gerd J. Kunde - LANL

56. G.Cardoso Slide
MODULE UNDER TEST
Gerd J. Kunde - LANL

57. iFVTX plane with Twelve 8-Chip Modules
12/2005
iFVTX plane with Twelve 8-Chip Modules
Cooling
PCB
VHDMSignals
Power
TPG
FPIX on HDI
Wire Bonds
HV Bias
Pulser
Wire Bonded Flex Cable go to Pole Face Board
Gerd J. Kunde - LANL

58. iFVTX Two Type of Planes
12 8-chip modules
8 8-chip modules
Gerd J. Kunde - LANL

59. iFVTX 3-d Layout (concept)
Gerd J. Kunde - LANL

60. iFVTX Transition to the Outside World The Pole Face Board
Printed Circuit Board
Feed through via multilayer board
Flex Wire Bond Area
Outside connectors
Cables come for iFVTX planes to inside connectors
Gerd J. Kunde - LANL

61. Test Setup at LANL we are working with a FNAL chip since July 2005
Chip Response
LA Display
Logic Analyzer
DVM
DAQ
Low Voltage
Invisible: Clean Power and Scope and Pulser
Test Board
Gerd J. Kunde - LANL

62. BACKUP Slides on the FSSR Hybrid
Gerd J. Kunde - LANL

63. Hybrid FSSR 40mm Pigtail solder pads Decoupling capacitors
G.Cardoso Slide
Hybrid
Prototype
4 layer FR4 board, ~ 1mm thick.
Copper traces, 17um thick.
75um traces/spacing.
Production
4 layer BeO board, ~ 500um thick.
Gold traces, 10um thick.
75um traces/spacing.
FSSR
40mm
Pigtail solder pads
Decoupling
capacitors
Termination resistors
75mm
Gerd J. Kunde - LANL

64. Pigtail Connector Pigtail Pigtail Hybrid G.Cardoso Slide 3cm
Soldered to hybrid.
Connects hybrid to flex cable.
Avoids having a connector on hybrid.
2 layer, 100um traces/spacing, broadside coupled differential lines (LVDS).
Pigtail
Connector
Pigtail
Hybrid
3cm
Gerd J. Kunde - LANL

65. Flex Cable ... 50cm G.Cardoso Slide Connects pigtail to Junction Card.
Length depends on station position.
2 layer, 100um traces/spacing, broadside coupled differential lines (LVDS).
50cm HV
HV GND
AGND
DGND
DVDD
AVDD
...
Differential pairs and sense wires
NOT TO SCALE
1cm
2.5cm
0.5cm
Gerd J. Kunde - LANL

66. G.Cardoso Slide
Pitch Adapter
Gerd J. Kunde - LANL