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CSE 242A Integrated Circuit Layout Automation Lecture: Partitioning Winter 2009 Chung-Kuan Cheng.

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Presentation on theme: "CSE 242A Integrated Circuit Layout Automation Lecture: Partitioning Winter 2009 Chung-Kuan Cheng."— Presentation transcript:

1 CSE 242A Integrated Circuit Layout Automation Lecture: Partitioning Winter 2009 Chung-Kuan Cheng

2 Outlines Motivations Formulations 2-way partitioning, multi-way partitioning, multilevel partitioning, replication cut, clustering. Net Modeling Algorithms Optimal Methods: Special cases, branch and bound, Heuristic Methods: group migration, network flow, clustering, simulated annealing, genetic approaches

3 Motivation Huge designs 100 Millions Trans Design Analysis Engineering Change Orders Good partitioning makes difference on design quality

4 Motivation: Applications Physical Hierarchy Divide and Conquer Project decomposition Complexity reduction of each level Emulation Hardware & Software codesign Management design resource

5 Formulations: Two Way Partitioning Random two-way partition N-pin net to be cut a a a a b b b b

6 Min-Cut s t Theorem: There exists an optimal linear placement s.t. X and are separated. Trend:

7 Min-Cut Opt->Linear Placement Trend: X=V S S

8 Bisection

9 Ratio Cut

10 Multi-Way Partitioning K-Way Partitioning X1X1 X2X2 XkXk

11 Cluster Ratio Cut

12 Multi-Level Partitioning K-Level Partitioning L i <= X i <= U i Min Connection Cost E(T i ) <= C i External connection cost <= threshold at level i

13 Generic Binary Tree L <= X i <=U Level of Node = longest path to leaves Connection cost of node i at level L

14 Replication Cut X Y R X R R Y C(X,Y)+C(Y,X)+C(Y,R)+C(X,R)

15 Performance-Driven Partitioning Need an incremental timing analysis to reflect the performance fast Replication helps

16 Retiming (Pipelined process) Allocate one clock cycle for interpartition communication System performance is dominated by Loops:

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18 Clustering K-Way Partitioning K>>10 Obj strongly depends on applications Performance driven Obj min max # cuts between registers Complexity reduction E i external connection I i internal connection

19 Net Modeling Shifting: For each shift, we update k, n-k. The cost of the net changes only when k = 0, 1 or n- k =0, 1 Two pin net clique 2/k total weight k-1 1/(k-1) S.K.

20 Net Modeling: Loop Model Suppose relative positions of pins are given, we can use a loop model The model remains correct if any two adjacent (in order) pins swap

21 Net Modeling: Hypernet Model (Flow Approach)

22 Optimal Methods: Branch & Bound Prune the branches when size constraint is violated Partial cost >= existing cost For U=L=|V|/2 # combinations = |V| ! / (|V/2)! (|V|/2)! With an elegant implementation |V| <= 60 is feasible

23 Optimal Methods: Serial & Parallel Graph Dynamic Programming on Series-Parallel graph G(V, E, s, t) C(a, i, j) a: s, t on different sides C(b, i, j) b: s, t on the left side, left side has i nodes, right side has j nodes

24 Optimal Methods: Serial & Parallel Graph (Cont) Dynamic Programming on Series-Parallel graph G(V, E, s, t) C(a, i, j) a: s, t on different sides C(b, i, j) b: s, t on the left side, left side has i nodes, right side has j nodes

25 Heuristic Methods Group Migration Kernighan & Lin Fiducccia-Matheyses Programming Network Flow Replication Cut Clustering

26 Group Migration Kermighan & Lin Bisection Cost Ci: change of #cuts by moving node i to the other side Heapsort nodes in each partition according to Ci Repeat Choose among the top k the best pair to swap Update the cost, lock the moved nodes Until all nodes are locked Find the best sequence to swap Until no more improvement

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28 Group Migration Hill climbing to jump over local optimal solutions. Locking mechanism to avoid repeated moves.

29 Fiduccia-Mattheyses No swapping, move a single node each time Replace the heap with an array

30 High Order Gains

31 Probabilistic Model

32 Move all nodes according to a single net Adv: move more nodes a the same operation. Good for multi-way, hierarchical where cost function dominated by the way to handle the nets Dis: Complicate

33 Simulated Annealing

34 s, nexts: configurations, T: real, count: integer Begin S= random initial configuration T=T 0 Repeat  Count= 0  Repeat  Count= count+1  Nexts= generate(s)  If c(nexts) random(0,1)  Then s= nexts  Until equilibrium(count,s,T) T= update(T) Unitl frozen(T) End

35 Programming

36 Improving the lower bound

37 Network Flow Approaches

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39 Multiple Commodity Flow

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41 B constraints can be used to replace A

42 Weighted Cluster Ratio Cut

43 Replication Cut

44 R ST RR ST S T

45 Replication Graph

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50 Heuristic Flow Approaches

51 Cluster Ratio

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53 Clustering (Performance- Driven) Cap <= 4 (1)Min delay (2)Min #clusters (3)Min #clusters, T>=delay (4)Min delay #clusters <= C (5)Min max #inputs, #cluster<= C (6)Min #clusters, #inputs <= K

54 Clustering Heuristics Cluster during target operation Recursive partitioning (ratio cut) to find clusters. Then treat each cluster as a single node to perform partitioning.

55 Linear Placement Iteration Do linear placement Cluster adjacent nodes Treat each cluster as a single node repeat linear placement Adv: Work on the right target Dis: Need an efficient & effective target operation

56 Max Pair Given pairing cost, find the best pair to cluster Treat each cluster as a single node. Repeat the process The cost function does not encourage the largest node pair with other nodes continuously.

57 Max Matching Match the n/2 pairs simultaneously Adv: max matching can be solved in polynomial operation optimally Dis: enforce unnatural pair to merge C and f are merged because their choices are taken by others

58 Variations of cost function Similarity of signatures (Data Path) Bit #, pin sequence Control signal, function of gate

59 The conductivity between nodes i & j

60 K th -connectivity

61 Research Directions Logic Hierarchy Layout Hierarchy (1)Obj: min distortion, max performance (2)Linkage between two: eg ECO revision (3)Improvement of operations by exploring the given hierarchy


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