1. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information EngineeringNational Cheng Kung University Experiment on Digital System Advanced Practice 2014-12-24/25

2. Reference Links Altera Quartus II Handbook Altera Quartus II Web Edition - Free (Create a user account) 北瀚科技股份有限公司 SMIMS北瀚科技股份有限公司 SMIMS – FPGA Board 數位 IC 設計入門 -Verilog ，滄海書局， 2008 (ISBN 978-986-6889-90-5)(ISBN 978-986-6889-90-5) 2

3. Outline Traffic Light System Snake Scrolling Text LFSR 3

4. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information EngineeringNational Cheng Kung University Traffic Light System

5. Please use the following components:  3 LEDs (green, yellow, and red)  2 Seven-Segment Display  1 LED Dot Matrix Display  1 button The layout: 5

6. Traffic Light System LEDs :  10 seconds for green light, then 3 seconds for yellow, then 10 seconds for red light, and then back to green light. Seven-Segment Display :  Count down from 13 to 1 when the LED is green or yellow, then count down from 7 to 1 when the LED is red. LED Dot Matrix Display :  Show img.1 when the LED is green or yellow  Show img.2 when the LED is red Button :  Reset the system – LED green, Seven-Segment Display13, and show img.2 6 img.2img.1

7. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information EngineeringNational Cheng Kung University Snake

8. Please use 4 Seven-Segment Displays, 1 switch, and 1 reset button. The layout is as follow: 8

9. Snake The positive (switch = 0)movement of the snake is: a0a1a2 → a1a2a3 → a2a3b3 → a3b3g3 → b3g3g2 → g3g2g1 → g2g1g0 → g1g0e0 → g0e0d0 → e0d0d1 → …….. The negative (switch = 1)movement is the reverse direction. When reset is pressed, the snake bake to the initial state. 9 Reset state

10. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information EngineeringNational Cheng Kung University Scrolling Text

11. Please use 3 LED Dot Matrix Displays, 1 switch, and 1 reset button. The layout is as follow: 11

12. Scrolling Text The text pattern are : The text scrolls to left when switch is 0, and scrolls to right when switch is 1. When reset is pressed, the test bake to the initial state. 12 Reset state

13. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information EngineeringNational Cheng Kung University LFSR

14. LFSR (Linear-feedback Shift Register) can be used as a random integer generator in hardware design. The architecture of LFSR could be described as shift registers, and there exists an extra feedback wire. 14

15. LFSR In this exercise, the feedback is Q[0] xor Q[3], and the initial state of the registers are all 1. Please complete a random generator based on the architecture above. 15

16. LFSR Please use 2 Seven-Segment Displays, and 2 buttons (one for reset and another for generating a number). The layout is as follow: When reset is pressed, show 00 and assign 1 to the all registers. When generate is pressed, show the random number. 16

17. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information EngineeringNational Cheng Kung University Appendix

18. Dot Matrix The dot matrix is controlled by 8 column lines and 8 row lines. When the column line and the row line are both 1, the dot will be turned on. 18 0 0 0 0 0000000000000000 0 0 1 0 0 0 0 0 0001000000010000

19. Dot Matrix Scan the rows frequently, and control the column lines, the image could be showed by Persistence of vision. 19 0 0 0 1 1 0 0 0 1000000010000000 0 0 1 0 0 1 0 0 0100000001000000 0 1 0 0 0 0 1 0 0010000000100000 1 0 0 0 0 0 0 1 0001000000010000 →→→→ … =>

20. Notice wire and reg type define  always begin … 裡面變數 … end ，宣告 reg type  always begin …… end 外面變數，宣告 wire type 需搭配 assign 使用 reg == register  在組合電路中使用 reg type ，合成 → 線 (net)  在循序電路中使用 reg type ，合成 → Flip-flop (register) Inferred latch  在組合電路中， case 、 if…else… 若沒有寫滿，合成後會產生 latch

21. Notice 建議請勿在 C:\ 與 Desktop 建立專案  請勿命名中文資料夾或數字開頭資料夾 請確認 Device family 是否與 FPGA 晶片符合  Family: Cyclone / Device: EP1C6Q240C8 top module name & project name 需要一致 燒錄檔案至 FPGA 前， Double-check Pin Assignment  設定錯誤的 Pin ，會導致 VeriInstrument 無法執行 連接 FPGA 板後，請先確認是否可以正常燒錄與動作  VeriLite USB Driver (For all students)  USB Blaster  如果出現無法辨識硬體裝置，請先將 JTAG 拔除後，先裝 VeriLite USB Driver 後，再裝上去 JTAG ，讓電腦去辨 識 USB Blaster 裝置，接著去指定到 USB Blaster Driver 目標資料夾 C:\altera\8.0\quartus\drivers\usb-blaster

22. Number Representation May be represented using  Binary, decimal, hexadecimal, Format  ’  base_format:  b, d, h, Example  4'b1111; 16'd255  23456 (32-bit decimal # by default); 'hc3 (32 bit)  12'b1111_0000_1010