1. Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Medium Scale Integration and Programmable Logic Devices Part II

2. Review At the outset of designing a complex system, such as a modern computer or network, it is clear that design is extraordinarily difficult and computationally challenging when performed at the level of fundamental Boolean logic gates. For these reasons modern design approaches are based on hierarchical, component based methods. –Leading to simplified, localized component design, –lowering of design costs, –shifting some aspects of design to the component interface (the compatibility problem). We now continue our study of MSI circuits to better understand this process of MSI design.

3. Goals We continue our study of simple, but functional Combinational circuits: –we continue constructing a small library of useful components –through study of the solution process using Boolean algebra and Boolean calculus (simplification, etc.) we better understand the meaning of SSI design –we seek to identify these components for their re-use potential –through our study we will better understand how MSI increases the level of abstraction in solving problems - SSI design is relatively concrete.

4. Circuit # 4 : Binary Subtractor

5. Before proceeding to design a subtractor circuit, consider a few examples of the operation D = X - Y: Example 1 : X 0 0 1 1 -Y 0 0 0 1 ======= D 0 0 1 0 Considered “easy” because: 1-1 = 0 is easy 1-0 = 1 is easy 0-0 = 0 is easy But.....

6. Circuit # 4 : Binary Subtractor Example 2 : –This is not straightforward – it requires the concept of “borrowing” from the column on the left. –Use a trick – add zero! Introduce a borrow constant, B. For an L-bit representation, B = 2 L. Example 2 : B= 1 0 0 0 0 X 0 0 1 1 -Y 0 1 0 1 ======= D 1 1 1 0 This is not a mathematical zero. Rather, it is a practical zero since we only use the low-order 4 bits.

7. Circuit # 4 : Binary Subtractor Example 2 : –This is not straightforward – it requires the concept of “borrowing” from the column on the left. –Use a trick – add zero! Introduce a borrow constant, B. For an L-bit representation, B = 2 L. Example 2 : B= 1 0 0 0 0 X 0 0 1 1 -Y 0 1 0 1 ======= D 1 1 1 0 Instead of X K – Y K, we have recast this in the form B K + X K – Y K. NOTE: By borrowing from the left, each successive borrow digit becomes a 1 until the column which forces the first borrow. This specific borrow digit has the value 2 (binary 10). B= 0 1 2 0 0

8. Circuit # 4 : Binary Subtractor Example 2 : –This is not straightforward – it requires the concept of “borrowing” from the column on the left. –Use a trick – add zero! Introduce a borrow constant, B. For an L-bit representation, B = 2 L. Example 2 : B= 1 0 0 0 0 X 0 0 1 1 -Y 0 1 0 1 ======= D 1 1 1 0 Now we note that we have already borrowed from this column (in the next-to-right column). But we also had to borrow from the next-to-left column. Hence, we borrow a ‘2’ from the left, then borrow ‘1’ from this ‘2’ to the right, the net result is to add ‘1’ to the current column. The rest of the subtraction (+2-1+0-0)=1 is easy. B= 0 1 2 0 0

9. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 X K and Y K are the inputs for (X K -Y K ) and D K is the difference (within the K’th column) B K refers to the amount of borrowing already performed (in order to carry out a subtraction in the next-to-right column) B K+1 refers to the amount of borrowing that must be done from the next-to-left column (in order to carry out a subtraction in the current K’th column) NOTE: It is understood that a ‘1’ denotes a borrow of ‘2’ in the current K’th column.

10. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 X K minuend - 0 Y K subtrahend 0 D K difference

11. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 There is no need to perform a “borrow” operation. 0 X K minuend - 0 Y K subtrahend 0 D K difference

12. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 0 0 X K minuend - 0 Y K subtrahend - 1 B K prior borrow 1 D K difference 1 B K+1 next borrow

13. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 0 0 X K minuend - 0 Y K subtrahend - 1 B K prior borrow 1 D K difference 1 B K+1 next borrow Assume that a “borrow” was required in a previous column subtraction - then we must subtract 1 from the minuend in this column.

14. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 X K minuend - 0 Y K subtrahend - 1 B K prior borrow 1 D K difference 1 B K+1 next borrow If the subtraction cannot be performed, then we must “borrow” from the next column. We note this borrow as B K+1, and then use the value 2 (!) for the minuend, X K. 2

15. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 X K minuend - 1 Y K subtrahend 1 D K difference 1 B K+1 next borrow

16. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 X K minuend - 1 Y K subtrahend 1 D K difference 1 B K+1 next borrow If the subtraction cannot be performed, then we must “borrow” from the next column. We note this borrow as B K+1, and then use the value 2 (!) for the minuend, X K. 2

17. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 0 X K minuend - 1 Y K subtrahend - 1 B K prior borrow 0 D K difference 1 B K+1 next borrow

18. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 0 X K minuend - 1 Y K subtrahend - 1 B K prior borrow 0 D K difference 1 B K+1 next borrow If the subtraction cannot be performed, then we must “borrow” from the next column. We note this borrow as B K+1, and then use the value 2 (!) for the minuend, X K. 2

19. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 X K minuend - 0 Y K subtrahend - 0 B K prior borrow 1 D K difference 0 B K+1 next borrow There is no need to perform a “borrow” operation.

20. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 X K minuend - 0 Y K subtrahend - 1 B K prior borrow 0 D K difference 0 B K+1 next borrow There is no need to perform a “borrow” operation.

21. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 X K minuend - 1 Y K subtrahend - 0 B K prior borrow 0 D K difference 0 B K+1 next borrow There is no need to perform a “borrow” operation.

22. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 1 X K minuend - 1 Y K subtrahend - 1 B K prior borrow 1 D K difference 1 B K+1 next borrow If the subtraction cannot be performed, then we must “borrow” from the next column. We note this borrow as B K+1, and then use the value 2 (!) for the minuend, X K. 2

23. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 The circuit expressions for the outputs are derived:

24. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 The circuit expressions for the outputs are derived: D K = X K ’Y K ’B K + X K ’Y K B K ’ + X K Y K ’B K ’ + X K Y K B K

25. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 The circuit expressions for the outputs are derived: D K = X K ’Y K ’B K + X K ’Y K B K ’ + X K Y K ’B K ’ + X K Y K B K = B K xor X K xor Y K

26. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 D K = B K xor X K xor Y K 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 The circuit expressions for the outputs are derived:

27. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 D K = B K xor X K xor Y K 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 The circuit expressions for the outputs are derived: B K+1 = X K ’Y K ’B K + X K ’Y K B K ’ + X K ’Y K B K + X K Y K B K

28. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 D K = B K xor X K xor Y K 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 The circuit expressions for the outputs are derived: B K+1 = X K ’Y K ’B K + X K ’Y K B K ’ + X K ’Y K B K + X K Y K B K = X K ’Y K (B K + B K ’) + X K ’(Y K + Y K ’ ) B K + ( X K + X K ’)Y K B K

29. Circuit # 4 : Binary Subtractor We begin the design by constructing a 3-input/2-output truth table: X K Y K B K D K B K+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 D K = B K xor X K xor Y K 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 B K+1 = X K ’Y K + X K ’B K + Y K B K 1 1 0 0 0 1 1 1 1 1 The circuit expressions for the outputs are derived: B K+1 = X K ’Y K ’B K + X K ’Y K B K ’ + X K ’Y K B K + X K Y K B K = X K ’Y K (B K + B K ’) + X K ’(Y K + Y K ’ ) B K + ( X K + X K ’)Y K B K

30. Circuit # 4 : Binary Subtractor This leads to the expressions: D K = B K xor X K xor Y K B K+1 = X K ’Y K + X K ’B K + Y K B K These have the logic gate realizations:

31. Circuit # 4 : Binary Subtractor This leads to the expressions: D K = B K xor X K xor Y K B K+1 = X K ’Y K + X K ’B K + Y K B K These have the logic gate realizations: BKXKYKBKXKYK D K B K+1 FS

32. Circuit # 4 : Binary Subtractor This leads to the expressions: D K = B K xor X K xor Y K B K+1 = X K ’Y K + X K ’B K + Y K B K These have the logic gate realizations: BKXKYKBKXKYK D K B K+1 FS Full Subtractor Binary Full Subtractor BKXKYKBKXKYK D K B K+1 FS

33. Circuit # 4 : Binary Subtractor We can now employ the 1-bit Full Subtractor to construct a multi- bit subtractor –we use a FS with B 0 = 0 for the first bit. –this can be replaced with a specialized Half-Subtractor circuit. BKXKYKBKXKYK D K B K+1 FS

34. Circuit # 4 : Binary Subtractor We can now employ the 1-bit Full Subtractor to construct a multi- bit subtractor –we use a FS with B 0 = 0 for the first bit. (This can be replaced with a specialized Half-Subtractor circuit). Y X B in B out S Y X B in B out S Y X B in B out S Y X B in B out S Y 0 X 0 Y 1 X 1 Y 2 X 2 Y 3 X 3 S0S0 S1S1 S3S3 S2S2 B out 0 4-bit MSI: Ripple Subtractor

35. Circuit # 4 : Binary Subtractor We can now employ the 1-bit Full Subtractor to construct a multi- bit subtractor –we use a FS with B 0 = 0 for the first bit. This can be replaced with a specialized Half-Subtractor circuit. Y X B in B out D Y X B in B out D Y X B in B out D Y X B in B out D Y 0 X 0 Y 1 X 1 Y 2 X 2 Y 3 X 3 D0D0 D1D1 D3D3 D2D2 B out 0 4-bit MSI: Ripple Subtractor Y 3 Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0 B out B in D 3 D 2 D 1 D 0 4-bit MSI: Full Ripple Subtractor

36. Circuit # 4 : Binary Subtractor Note that the Full Adder and Full Subtractor are identical, except for a single inverter applied to the first input (A or X): BKXKYKBKXKYK D K B K+1 FS Full Subtractor Binary Full Subtractor BKXKYKBKXKYK D K B K+1 FS C in A B S C out FA Binary Full Adder CKXKYKCKXKYK D K C K+1 FA

37. Circuit # 4 : Binary Subtractor There are alternative methods to performing subtraction, based on 1’s and 2’s complement representations.

38. Circuit # 4 : Binary Subtractor There are alternative methods to performing subtraction, based on 1’s and 2’s complement representations. Since (X - Y) is the same as (X+Y’+1) using 2’s complement arithmetic, we can use the adder to perform subtraction by adding inverters to the Y inputs and setting the input carry bit to 1.

39. Circuit # 4 : Binary Subtractor There are alternative methods to performing subtraction, based on 1’s and 2’s complement representations. Since (X - Y) is the same as (X+Y’+1) using 2’s complement arithmetic, we can use the adder to perform subtraction by adding inverters to the Y inputs and setting the input carry bit to 1. Y 3 Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0 C out C in S 3 S 2 S 1 S 0 4-bit MSI Full Ripple Adder 1

40. Circuit # 5 : Binary Adder/Subtractor

41. Finally, we note the following facts about the xor gate:

42. Circuit # 5 : Binary Adder/Subtractor Finally, we note the following facts about the xor gate: A xor 1 = A’

43. Circuit # 5 : Binary Adder/Subtractor Finally, we note the following facts about the xor gate: A xor 1 = A’Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’

44. Circuit # 5 : Binary Adder/Subtractor Finally, we note the following facts about the xor gate: A xor 1 = A’Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’ A xor 0 = A

45. Circuit # 5 : Binary Adder/Subtractor Finally, we note the following facts about the xor gate: A xor 1 = A’Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’ A xor 0 = AProof: 0 xor 0 = 0 1 xor 0 = 1

46. Circuit # 5 : Binary Adder/Subtractor Finally, we note the following facts about the xor gate: A xor 1 = A’Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’ A xor 0 = AProof: 0 xor 0 = 0 1 xor 0 = 1 These properties of the xor gate allow us to construct a circuit that can perform either addition or subtraction:

47. Circuit # 5 : Binary Adder/Subtractor Finally, we note the following facts about the xor gate: A xor 1 = A’Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’ A xor 0 = AProof: 0 xor 0 = 0 1 xor 0 = 1 These properties of the xor gate allow us to construct a circuit that can perform either addition or subtraction: S 3 S 2 S 1 S 0 4-bit MSI Full Ripple Adder/Subtractor Add(0)/ Sub(1) Y 3 Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0

48. Circuit # 5 : Binary Adder/Subtractor Finally, we note the following facts about the xor gate: A xor 1 = A’Proof: 0 xor 1 = 1 = 0’ 1 xor 1 = 0 = 1’ A xor 0 = AProof: 0 xor 0 = 0 1 xor 0 = 1 These properties of the xor gate allow us to construct a circuit that can perform either addition or subtraction: S 3 S 2 S 1 S 0 4-bit MSI Full Ripple Adder/Subtractor Add(0)/ Sub(1) Y 3 Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0 The input carry bit is used as a toggle to control the choice of addition or subtraction. +/- +/-

49. Circuit # 5 : Binary Adder/Subtractor Now that it has been demonstrated that subtraction can be carried out using addition circuits, we may henceforth treat only addition cases, without any loss of generality. S 3 S 2 S 1 S 0 4-bit MSI Full Ripple Adder/Subtractor Add(0)/ Sub(1) Y 3 Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0 +/- +/-

50. Circuit # 6 : Carry Lookahead Adder

51. The representation of the Carry-out circuit for the full adder is: C K+1 = X K Y K + C K X K + C K Y K = X K Y K + C K (X K + Y K )

52. Circuit # 6 : Carry Lookahead Adder The representation of the Carry-out circuit for the full adder is: C K+1 = X K Y K + C K X K + C K Y K = X K Y K + C K (X K + Y K ) Define terms: g K = X K Y K and, p K = (X K + Y K ) We may now write: C K+1 = g K + C K p K

53. Circuit # 6 : Carry Lookahead Adder The representation of the Carry-out circuit for the full adder is: C K+1 = X K Y K + C K X K + C K Y K = X K Y K + C K (X K + Y K ) Define terms: g K = X K Y K and, p K = (X K + Y K ) We may now write: C K+1 = g K + C K p K Also, recall that the sum bit is generated using the expression: S K = C K xor A K xor B K

54. Circuit # 6 : Carry Lookahead Adder Using the expressions: C K+1 = g K + C K p K S K = C K xor A K xor B K We define the Sigma-block circuit: X K Y K C K PKGKPKGK SKSK

55. Circuit # 6 : Carry Lookahead Adder Using the expressions: C K+1 = g K + C K p K S K = C K xor A K xor B K We define the Sigma-block circuit: This may be abbreviated as the MSI component: X K Y K C K PKGKPKGK SKSK PKGKPKGK SKSK SIG

56. Circuit # 6 : Carry Lookahead Adder Using the expressions: C K+1 = g K + C K p K S K = C K r A K r B K We define the Sigma-block circuit: This may be abbreviated as the MSI component: X K Y K C K PKGKPKGK SKSK PKGKPKGK SKSK Note that both P and G only require evaluation of one logic gate. SIG

57. Circuit # 6 : Carry Lookahead Adder These results suggest that the previous ripple-adder circuit may be replaced by the following circuit, using Sigma-blocks: P0G0P0G0 S0S0 X 0 Y 0 C 0 P1G1P1G1 S1S1 X 1 Y 1 C 1 P3G3P3G3 S3S3 X 3 Y 3 C 3 P2G2P2G2 S2S2 X 2 Y 2 C 2 Carry lookahead network C4C4 C0C0 SIG

58. Circuit # 6 : Carry Lookahead Adder Expanding the carry terms for a 4-bit adder: C 1 = g 0 + C 0 p 0 C 2 = g 1 + C 1 p 1 = g 1 + (g 0 + C 0 p 0 )p 1 = g 1 + g 0 p 1 + C 0 p 0 p 1 C 3 = g 2 + C 2 p 2 = g 2 + g 1 p 2 + g 0 p 1 p 2 + C 0 p 0 p 1 p 2 C 4 = g 3 + C 3 p 3 = g 3 + g 2 p 3 + g 1 p 2 p 3 + g 0 p 1 p 2 p 3 + C 0 p 0 p 1 p 2 p 3

59. Circuit # 6 : Carry Lookahead Adder Expanding the carry terms for a 4-bit adder: C 1 = g 0 + C 0 p 0 C 2 = g 1 + C 1 p 1 = g 1 + (g 0 + C 0 p 0 )p 1 = g 1 + g 0 p 1 + C 0 p 0 p 1 C 3 = g 2 + C 2 p 2 = g 2 + g 1 p 2 + g 0 p 1 p 2 + C 0 p 0 p 1 p 2 C 4 = g 3 + C 3 p 3 = g 3 + g 2 p 3 + g 1 p 2 p 3 + g 0 p 1 p 2 p 3 + C 0 p 0 p 1 p 2 p 3 Note that all the carry expressions require only two evaluation stages (one for the and, the other for the or).

60. Circuit # 6 : Carry Lookahead Adder These results can now be used to complete the Carry lookahead network portion of the 4-bit adder: P0G0P0G0 S0S0 X 0 Y 0 C 0 P1G1P1G1 S1S1 X 1 Y 1 C 1 P3G3P3G3 S3S3 X 3 Y 3 C 3 P2G2P2G2 S2S2 X 2 Y 2 C 2 Carry lookahead network C4C4 C0C0 SIG

61. Circuit # 6 : Carry Lookahead Adder These results can now be used to complete the Carry lookahead network portion of the 4-bit adder:

62. Circuit # 6 : Carry Lookahead Adder These results can now be used to complete the Carry lookahead network portion of the 4-bit adder: Now it is clear that evaluation of each carry requires, at most, 3 logic gates. Thus, each sum digit requires at most 4 logic gates.

63. Circuit # 6 : Carry Lookahead Adder This brings us back to the basic, 4-bit MSI Adder/Subtractor, which may now be assumed to be optimized with carry lookahead circuits. These may be used, in turn, to develop more powerful multi-bit adder/subtractors. C out C in S 3 S 2 S 1 S 0 4-bit MSI Full Adder/Subtractor Add(0)/ Sub(1) Y 3 Y 2 Y 1 Y 0 X 3 X 2 X 1 X 0

64. Circuit # 7 : Decimal Adder

65. There are many situations where it is useful to employ decimal arithmetic on decimal representations (e.g. BCD: 8421). –BCD: 0 1 2 7 8 9 0000, 0001, 0010, …, 0111, 1000, 1001 Remind yourself that BCD uses a 4-bit representation to store the values of digits 0..9, but this leaves wastage of some bit patterns (unused patterns).

66. Circuit # 7 : Decimal Adder There are many situations where it is useful to employ decimal arithmetic on decimal representations (e.g. BCD: 8421). –BCD: 0 1 2 7 8 9 0000, 0001, 0010, …, 0111, 1000, 1001 To illustrate some of the issues we consider one example of decimal addition of single digits, leading to a full decimal adder. –This design will be based on the use of the binary adder.

67. Circuit # 7 : Decimal Adder Note that the problem of adding two decimal digits together, in general, also requires accounting for an input carry and an output carry. Minimum Sum:Maximum Sum: 0 (No carry) 1 (Carry) 0 9 + 0+ 9 0 19 (No Carry out) DECIMAL ARITHMETIC(Carry out) Note also that the maximum number of distinct sums is 20.

68. Circuit # 7 : Decimal Adder Note that the problem of adding two decimal digits together, in general, also requires accounting for an input carry and an output carry. Minimum Sum:Maximum Sum: 0 (No carry) 1 (Carry) 0 9 + 0+ 9 0 19 DECIMAL ARITHMETIC(Carry out) Note that the maximum number of distinct sums is 20. Consider the example: Carry 1110 999 + 99 ==== Sum 1998

69. Circuit # 7 : Decimal Adder We can obtain the sums in two stages.

70. Circuit # 7 : Decimal Adder We can obtain the sums in two stages. First, list all possible outputs from the direct sum of the decimal digits, then ….. K P 3 P 2 P 1 P 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 Direct sum of decimal digits, ranging from 0 to 19 10, represented in 5- bit form with high- order bit K.

71. Circuit # 7 : Decimal Adder We can obtain the sums in two stages. First, list all possible outputs from the direct sum of the decimal digits, then ….. Beside each sum place the expected values of the sum bits and the carry out bit. K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 1 0 0 0 1 00 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 10 1 0 0 1 0 1 0 1 01 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 0 11 0 1 1 1 1 0 0 1 01 1 0 0 0 1 0 0 1 1 1 1 0 0 1 Expected outputs, with sum bits S J and carry-out bit C.

72. Circuit # 7 : Decimal Adder The first-stage sums divide into two groups: –the first ten sums produce the correct final sum and carry bit patterns K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 1 0 0 0 1 00 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 10 1 0 0 1

73. Circuit # 7 : Decimal Adder The first-stage sums divide into two groups: –the first ten sums produce the correct final sum and carry bit patterns –the last ten sums are all incorrect by the same amount, they should have 6 added to them to produce the correct final bit patterns. K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 1 0 0 0 1 00 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 10 1 0 0 1 0 1 0 1 01 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 0 11 0 1 1 1 1 0 0 1 01 1 0 0 0 1 0 0 1 1 1 1 0 0 1

74. Circuit # 7 : Decimal Adder The first-stage sums divide into two groups: –the first ten sums produce the correct final sum and carry bit patterns –the last ten sums are all incorrect by the same amount, they should have 6 added to them to produce the correct final bit patterns. K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 1 0 0 0 1 00 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 10 1 0 0 1 0 1 0 1 01 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 0 11 0 1 1 1 1 0 0 1 01 1 0 0 0 1 0 0 1 1 1 1 0 0 1 + 6 =

75. Circuit # 7 : Decimal Adder The condition used to identify and control the correction process is expressed in terms of the carry-out bit, C: C = K + P 3 P 2 + P 3 P 1 K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 1 0 0 0 1 00 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 10 1 0 0 1 0 1 0 1 01 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 0 11 0 1 1 1 1 0 0 1 01 1 0 0 0 1 0 0 1 1 1 1 0 0 1

76. Circuit # 7 : Decimal Adder The condition used to identify and control the correction process is expressed in terms of the carry-out bit, C: C = K + P 3 P 2 + P 3 P 1 Thus, if C = 0 then no correction is applied. K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 1 0 0 0 1 00 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 10 1 0 0 1 0 1 0 1 01 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 0 11 0 1 1 1 1 0 0 1 01 1 0 0 0 1 0 0 1 1 1 1 0 0 1

77. Circuit # 7 : Decimal Adder The condition used to identify and control the correction process is expressed in terms of the carry-out bit, C: C = K + P 3 P 2 + P 3 P 1 Thus, if C = 0 then no correction is applied. If C = 1, then 6 is added directly to the initial sum bits P J. K P 3 P 2 P 1 P 0 C S 3 S 2 S 1 S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 1 0 0 0 1 00 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 10 1 0 0 1 0 1 0 1 01 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 0 11 0 1 1 1 1 0 0 1 01 1 0 0 0 1 0 0 1 1 1 1 0 0 1 + 6 = This is referred to as the “Excess-64” technique for BCD addition.

78. Circuit # 7 : Decimal Adder The condition used to identify and control the correction process is expressed in terms of the carry-out bit, C: C = K + P 3 P 2 + P 3 P 1 A decimal full-adder circuit follows using a two-stage 4-bit binary adder MSI circuit and Uses the carry bit value directly to generate the value 6 10, or 0110 2. S 3 S 2 S 1 S 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 C 4 4-bit binary adder C 0 s 3 s 2 s 1 s 0 P 3 P 2 P 1 P 0 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 C in K x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 C 4 4-bit binary adder C 0 s 3 s 2 s 1 s 0 C out 0 Add 6

79. Circuit # 7 : Decimal Adder This MSI circuit is used to form the basis for a multi-decade decimal adder. S 3 S 2 S 1 S 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 C 4 4-bit binary adder C 0 s 3 s 2 s 1 s 0 P 3 P 2 P 1 P 0 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 C in K x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 C 4 4-bit binary adder C 0 s 3 s 2 s 1 s 0 C out 0 Add 6 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 C 4 BCD Decade adder C 0 s 3 s 2 s 1 s 0 S 3 S 2 S 1 S 0

80. Time out for some Design Philosophy!

81. Time out for some Philosophy! In software design and construction the programmer/analyst becomes familiar with identifying different aspects of the problem in terms of abstract models. Some of these models are quite concrete (bottom-up design) while others are relatively more abstract and require gradual expression of their detail (top-down design).

82. Time out for some Philosophy! Increasingly, modern Software Design is expressed in terms of components (functions, classes/objects, templates, metaprogramming) and focuses on software component re-use. One critical problem of software re-use lies in the proper, robust, flexible and standards-based design of the component interfaces. Other issues arise in the contexts of software complexity, performance, cost and other factors.

83. Time out for some Philosophy! Differential layering of abstraction in design also has its place in hardware design. SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components These differences have been demonstrated in each of the circuits/components that we have considered so far.

84. Time out for some Philosophy! Differential layering of abstraction in design also has its place in hardware design. SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components These differences have been demonstrated in each of the circuits/components that we have considered so far. S 3 S 2 S 1 S 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 C 4 4-bit binary adder C 0 s 3 s 2 s 1 s 0 P 3 P 2 P 1 P 0 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 C in K x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 C 4 4-bit binary adder C 0 s 3 s 2 s 1 s 0 C out 0 Add 6 C in A B S C out FA Binary Full Adder

85. Circuit # 8 : Comparator

86. The comparison of two (binary) numbers is of considerable importance. –if ( A < B ) then … –while ( A > B ) do...

87. Circuit # 8 : Comparator The comparison of two (binary) numbers is of considerable importance. –if ( A < B ) then … –while ( A > B ) do... It is possible to design a comparator circuit that establishes whether two input binary strings, A and B, satisfy the conditions: A = B A > B A < B

88. Circuit # 8 : Comparator The comparison of two (binary) numbers is of considerable importance. –if ( A < B ) then … –while ( A > B ) do... It is possible to design a comparator circuit that establishes whether two input binary strings, A and B, satisfy the conditions: A = B A > B A < B These conditions may be encoded using 3 flag bits: E = 1 G = 1 L = 1

89. Circuit # 8 : Comparator One strategy is to perform the comparison bit-wise and from right to left.

90. Circuit # 8 : Comparator One strategy is to perform the comparison bit-wise and from right to left. Express the two bit strings to be compared, A and B: A N … A K A K-1 … A 1 A 0 and B N … B K B K-1 … B 1 B 0

91. Circuit # 8 : Comparator One strategy is to perform the comparison bit-wise and from right to left. Express the two bit strings to be compared, A and B: A N … A K A K-1 … A 1 A 0 and B N … B K B K-1 … B 1 B 0 Now, restrict attention to the substrings: A K A K-1 … A 1 A 0 and B K B K-1 … B 1 B 0

92. Circuit # 8 : Comparator We begin with three distinct, possible assumptions:

93. Circuit # 8 : Comparator We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 E K-1 = 1, G K-1 = 0, L K-1 = 0

94. Circuit # 8 : Comparator We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 E K-1 = 1, G K-1 = 0, L K-1 = 0 A K-1 … A 1 A 0 > B K-1 … B 1 B 0 E K-1 = 0, G K-1 = 1, L K-1 = 0

95. Circuit # 8 : Comparator We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 E K-1 = 1, G K-1 = 0, L K-1 = 0 A K-1 … A 1 A 0 > B K-1 … B 1 B 0 E K-1 = 0, G K-1 = 1, L K-1 = 0 A K-1 … A 1 A 0 < B K-1 … B 1 B 0 E K-1 = 0, G K-1 = 0, L K-1 = 1

96. Circuit # 8 : Comparator We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 E K-1 = 1, G K-1 = 0, L K-1 = 0 A K-1 … A 1 A 0 > B K-1 … B 1 B 0 E K-1 = 0, G K-1 = 1, L K-1 = 0 A K-1 … A 1 A 0 < B K-1 … B 1 B 0 E K-1 = 0, G K-1 = 0, L K-1 = 1 Note that only one of E K-1, G K-1 or L K-1 may have value 1 at a time.

97. Circuit # 8 : Comparator We begin with three distinct, possible assumptions: A K-1 … A 1 A 0 = B K-1 … B 1 B 0 E K-1 = 1, G K-1 = 0, L K-1 = 0 A K-1 … A 1 A 0 > B K-1 … B 1 B 0 E K-1 = 0, G K-1 = 1, L K-1 = 0 A K-1 … A 1 A 0 < B K-1 … B 1 B 0 E K-1 = 0, G K-1 = 0, L K-1 = 1 Note that only one of E K-1, G K-1 or L K-1 may have value 1 at a time. Our goal is to derive expressions for outputs E K, G K and L K based on the inputs A K, B K, E K-1, G K-1 and L K-1.

98. Circuit # 8 : Comparator Construct an abbreviated truth-table: A K B K E K-1 G K-1 L K-1 E K G K L K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 Note that all other (missing) rows are represented using don’t care output values.

99. Circuit # 8 : Comparator Construct an abbreviated truth-table: A K B K E K-1 G K-1 L K-1 E K G K L K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 Note that all other (missing) rows are represented using don’t care output values. Condition is not altered when A K = B K

100. Circuit # 8 : Comparator Construct an abbreviated truth-table: A K B K E K-1 G K-1 L K-1 E K G K L K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 Note that all other (missing) rows are represented using don’t care output values. Condition L K = 1 always applies when A K < B K

101. Circuit # 8 : Comparator Construct an abbreviated truth-table: A K B K E K-1 G K-1 L K-1 E K G K L K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 Note that all other (missing) rows are represented using don’t care output values. Condition G K = 1 always applies when A K > B K

102. Circuit # 8 : Comparator This leads to Boolean expressions for the outputs (using don’t cares): A K B K E K-1 G K-1 L K-1 E K G K L K 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 G K = A K B K + A K G K-1 + B K G K-1 E K = A K B K E K-1 + A K B K E K-1 L K = A K B K + A K L K-1 + B K L K-1

103. Circuit # 8 : Comparator The 1-bit comparator circuit is expressed: A K B K GKEKLKGKEKLK G K-1 E K-1 L K-1

104. Circuit # 8 : Comparator The 1- bit comparator circuit is expressed in MSI form: A K B K G K G K-1 E K E K-1 L K L K-1 1-bit C o m p a r a t o r

105. Circuit # 8 : Comparator The 1- bit comparator circuit is expressed in MSI form: As with previous circuits, the 1-bit comparator circuit can be extended to form multi-bit, MSI ripple comparators. A K B K G K G K-1 E K E K-1 L K L K-1 1-bit C o m p a r a t o r A K-1 B K-1 G K-2 E K-2 L K-2 1-bit C o m p a r a t o r

106. Summary - Part II We continue to study logic design in the contexts of Small Scale Integration (SSI) and Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD). We have studied the design of a number of specific, practical functional circuits with a view to re-using those circuits as components in MSI design. Adders Subtractors Comparator We note the differing design approaches, or emphases, effected by differential layering of abstraction. (The same design issue arises in the context of software engineering as well.) SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components