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Advanced Topics on FPGA Applications Screen B Wu, Jinyuan Fermilab IEEE NSS 2007 Refresher Course Supplemental Materials Oct, 2007.

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Presentation on theme: "Advanced Topics on FPGA Applications Screen B Wu, Jinyuan Fermilab IEEE NSS 2007 Refresher Course Supplemental Materials Oct, 2007."— Presentation transcript:

1 Advanced Topics on FPGA Applications Screen B Wu, Jinyuan Fermilab IEEE NSS 2007 Refresher Course Supplemental Materials Oct, 2007

2 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 2 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

3 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 3 y x z y1a y1b x1a x1b y2a y2b x2a x2b y3a y3b x3a x3b 2*y1 = y2 3*y1 = y3 Doublet Matching

4 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 4 Example of Evaluating the Key Number 3*y1 = y3 K= 3*y1/8 K= y3/8 *3 y1y3 K K

5 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 5 DINDOUT Index RAM Pointer RAM DATA RAM K Link List Structure of Hash Sorter

6 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 6 Histogram with Fast Reset D Q K DV RAM QD WA WE RA D Q +1 D Q 0 RAM QD WA WE RA == RC CE RESET

7 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 7 An Example of Track Recognition: Hits

8 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 8 An Example of Track Recognition: Doublets Hits are paired together as doublet. Ghost doublets may exist.

9 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 9 An Example of Track Recognition: Histogram 00 c0c0 Two track parameters can be calculated for each doublet. A 2-D histogram is booked. Doublets from same track are entered into same bin, (since they have same track parameters). Sometimes they are stored in clusters. This is a “ghost”.

10 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 10 An Example of Track Recognition: Tracks All doublets from a track are contained in a cluster.

11 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 11 Simulation Results An event with 200 tracks It still works at 1000 tracks/event

12 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 12 Example: Finding “Soft Jets” A simulated event with 200 tracks. Flat distributions. Min. R = 55 cm 16 soft tracks are added. They are grouped in 2 small initial angle regions, i.e., 2 “soft jets”. 00 00 Can you see the “soft jets”? Can you see the “soft jets” now?

13 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 13 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

14 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 14 y x z u1a u1b v1a v1b u2a u2b v2a v2b u3a u3b v3a v3b u v

15 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 15 Three data items must satisfy the condition: x A + x C = 2 x B. A total of n 3 combinations must be checked (e.g. 5x5x5=125). Three layers of loops if the process is implemented in software. Large silicon resource may be needed without careful planning: O(N 2 ) Triplet Finding Plane APlane BPlane C

16 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 16 Block Diagram, Step 1

17 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 17 Block Diagram, Step 2

18 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 18 Circular Tracks from Collision Point on Cylindrical Detectors For a given hit on layer 3, the coincident between a layer 2 and a layer 1 hit satisfying coincident map signifies a valid circular track. A track segment has 2 free parameters, i.e., a triplet. The coincident map is invariant of rotation.  1 -  3 )+64  2 -  3 )+64

19 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 19 Logarithmic Shifter S1 S2 S4 # of bits: N Shift distance: L # of stages: log 2 L Total LE usage: N*log 2 L A shift of X bit of the bit pattern is done in one clock cycle rather than X cycles. Logarithmic shifter is also known as “barrel shifter”, but the term “logarithmic” reflects nature of implementation, resource usage and propagation delay better.

20 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 20 Logic Cell Usage Both 64- and 128-bit TTF designs fit $100 FPGA comfortably. A simple 64-bit Hough transform design is shown for scale. A $1200 FPGA is shown for scale. TTF64 TTF128 $100 $1200 Hough64

21 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 21 u1 v1 u2 v2 u3 v3 u4 v4 y5 x5 Complex Triplet Finding Problems

22 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 22 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

23 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 23 FPGA Process Sequencing Options Program Type Program Length (CLK cycles) ReprogramResource Usage Finite State Machine (FSM) Fixed Wired 10HardSmall Enclosed Loop Micro- Sequencer (ELMS) Memory Stored Program 10-1000EasySmall Microprocessor (MP) Memory Stored Program >1000EasyLarge

24 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 24 The Between Counter 0,1,2,3,4,5,6,7,8,9,A 5,6,7,8,9,A SLOAD D[] SCLR N Q[] M-1 == A[] B[] T 5,6,7,8,9,A 5,6,7,8,9,A,B,C,D,E,F… PC0: instr0 PC1: instr1 PC2: instr2 PC3: instr3 PC4: instr4 PC5: instr5 PC6: instr6 PC7: instr7 PC8: instr8 PC9: instr9 PCA: instrA PCB: instrB PCC: instrC PCD: instrD T ROM Between Counter Control Signals

25 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 25 ELMS – Detailed Block Diagram User Control Signals FORBckA1 EndA1 #n LDR2, #addr_a LDR3, #addr_X LDR7, #0 BckA1LDR4, (R2) INCR2 LDR5, (R3) INCR3 MULR6, R4, R5 EndA1ADDR7, R7, R6 LDR8, R7 The Stack supports nested loops, up to 128 layers.

26 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 26 What’s Good About ELMS FOR Loops at Machine Code Level Looping sequence is known in this example before entering the loop. Regular micro-processor treat the sequence as unknown. ELMS supports FOR loops with pre-defined iterations at machine code level. Execution time is saved and micro-complexities (branch penalty, pipeline bubble, etc.) associated with conditional branches are avoided. LDR1, #n LDR2, #addr_a LDR3, #addr_X LDR7, #0 BckA1LDR4, (R2) INCR2 LDR5, (R3) INCR3 MULR6, R4, R5 EndA1ADDR7, R7, R6 DECR1 BRNZBckA1 FORBckA1 EndA1 #n LDR2, #addr_a LDR3, #addr_X LDR7, #0 BckA1LDR4, (R2) INCR2 LDR5, (R3) INCR3 MULR6, R4, R5 EndA1ADDR7, R7, R6 25% MicroprocessorThe ELMS Conditional Branch

27 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 27 Outline Digital Design with FPGAs (This 45 min. Course)  Logic Element in a Nutshell  Variations of the Registered Adders  Tricks of Using RAM  RAM based histograms  Topics on Multipliers  Curved Track Fitter Advanced Topics on FPGA Applications (Included as Supplemental Materials)  Doublet Finding, Hash Sorter  Triplet Finding, Tiny Triplet Finder (TTF)  Options of Sequence Control, Recursive Structure, etc.

28 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 28 The Problem: 3  60Hz AC Rectify noise from power supply using 3-phase 60Hz AC are picked up by the input cable laying in the accelerator tunnel. Time Domain Frequency Domain ADC 21  s/sample

29 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 29 Filtering Results Noises >360Hz, the dominating portion, are filtered out in both filter functions. CIC sum is a lot smoother than the sliding sum. But small signals are still buried under ripples of 60 and 180 Hz. Sliding Sum CIC Sum Signals

30 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 30 Recursive Implementation of CIC Sum The non-recursive implementation needs: 248 memory fetches, 248 multiplications, 248 additions and more ops for longer sum lengths. + s[n] -x[n-K] x[n] + y[n] -s[n-K] + u[n] -2x[n-K] x[n] + y[n] x[n-2K]  x[n] y[n] *h1 *h2 *h[K] The CIC sum constructed as a sliding sum of sliding sums: 2 memory fetches, 0 multiplications, 4 add/sub ops for any sum length. The re-formulated CIC sum uses the raw data buffer rather than a separate buffer. CIC Sum

31 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 31 Exponential Sequence Generator  Q SET D if (CO==1) {Q = Q - Q/32;} This is also an example of recursive structure. This is IIR but it is stable. Dropping exponential components are used to stabilize other recursive structures.

32 Oct. 2007, Wu Jinyuan, Fermilab IEEE NSS Refresher Course, Supplemental Materials 32 The End Thanks

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