1. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 LECTURE : KEEE 4425 WEEK 6/2 DESIGN RULES,LAYOUT AND STICK DIAGRAM

2. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G Review: Design Abstraction Levels

3. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Summary of VLSI Components

4. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 CMOS Mask Layers P substrate wafer n well Determine placement of layout objects Color coding specifies layers Layout objects: –Rectangles –Polygons –Arbitrary shapes Grid types –Absolute (“micron”) –Scaleable (“lambda”)

5. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Mask Generation Mask Design using Layout Editor –user specifies layout objects on different layers –output: layout file Pattern Generator –Reads layout file –Generates enlarged master image of each mask layer –Image printed on glass Step & repeat camera –Reduces & copies image onto mask –One copy for each die on wafer –Note importance of mask alignment

6. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Symbolic Mask Layers Key idea: –Reduce layers to those that describe design –Generate physical layers as needed Magic Layout Editor: "Abstract Layers” –metal1 (blue) - 1st layer metal (equiv. to physical layer) –Poly (red) - polysilicon (equivalent to physical layer) –ndiff (green) - n diffusion (combination of active, nselect) –ntranistor (green/red crosshatch) - combined poly, ndiff –pdiff (brown) - p diffusion (combination of active, pselect) –ptransistor (brown/red crosshatch) - combined poly, pdiff –contacts: combine layers, cut mask

7. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 About Magic Scalable Grid for Scalable Design Rules –Grid distance:  lambda) –Value is process-dependent:  = 0.5 X minimum transistor length Painting metaphor –Paint squares on grid for each mask layer –Layers to interact to form components (e.g. transistors)

8. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Mask Layers in Magic Poly (red) N Diffusion (green) P Diffusion (brown) Metal (blue) Metal 2 (purple) Well (cross-hatching) Contacts (X)

9. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Magic User-Interface Cursor Box Paint (poly) Paint (pdiff) Paint (ntransistor) Graphic Display Window –Cursor –Box - specifies area to paint Command window (not shown) –accepts text commands :paint poly :paint red :paint ndiff :paint green :write –prints error & status messages

10. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Layer Interaction in Magic Transistors - where poly, diffusion cross –poly crosses ndiffusion - ntransistor –poly crosses pdiffusion – ptransistor Vias - where layers connect –Metal 1 connecting to Poly - polycontact –Metal 1 connecting to P-Diffusion (normal) - pdc –Metal 1 connecting to P-Diffusion (substrate contact) - psc –Metal 1 connecting to N-Diffusion (normal) - ndc –Metal 1 connecting to N-Diffusion (substrate contact) - nsc –Metal 1 connecting to Metal 2 - via

11. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Magic Layers – Example nwell nsc psc p-transistor ntransistor metal1 poly ndc polycontact pdc

12. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Why we need design rules Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience.

13. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Manufacturing problems Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.

14. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Transistor problems Variations in threshold voltage: –oxide thickness; –ion implantation; –poly variations. Changes in source/drain diffusion overlap. Variations in substrate.

15. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Wiring problems Diffusion: changes in doping -> variations in resistance, capacitance. Poly, metal: variations in height, width -> variations in resistance, capacitance. Shorts and opens:

16. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Oxide problems Variations in height. Lack of planarity -> step coverage. metal 1 metal 2

17. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Via problems Via may not be cut all the way through. Undesize via has too much resistance. Via may be too large and create short.

18. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 MOSIS CMOS design rules Designed to scale across a wide range of technologies. Designed to support multiple vendors. Designed for educational use. Ergo, fairly conservative.

19. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 and design rules  is the size of a minimum feature. Specifying particularizes the scalable rules. Parasitics are generally not specified in  units 

20. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Design Rules Typical rules: –Minumum size –Minimum spacing –Alignment / overlap –Composition –Negative features

21. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Types of Design Rules Scalable Design Rules Based on scalable “coarse grid” - (lambda) –Idea: reduce value for each new process, but keep rules the same Key advantage: portable layout Key disadvantage: not everything scales the same –Not used in “real life” Absolute Design Rules –Based on absolute distances (e.g. 0.75µm) –Tuned to a specific process (details usually proprietary) –Complex, especially for deep submicron –Layouts not portable

22. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 CMOS Design Rule Summary Contacts (Vias) –Cut size: exactly 2l X 2l –Cut separation: minimum 2l –Overlap: min 1l in all directions –Magic approach: Symbolic contact layer min. size 4l X 4l –Contacts cannot stack (i.e., metal2/metal1/poly) Other rules –cut to poly must be 3l from other poly –cut to diff must be 3l from other diff –metal2/metal1 contact cannot be directly over poly –negative features must be at least 2l in size –CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal

23. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Design Rule Checking in Magic Design violations displayed as error paint Find which rule is violated with ":drc why” Poly must overhang transistor by at least 2 (MOSIS rule #3.3)

24. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Aside - About MOSIS MOSIS - MOS Implementation Service Rapid-prototyping for small chips –Multi-project chip idea - several designs on the same wafer –Reduced mask costs per design –Accepts layout designs via email –Brokers fabrication by foundries (e.g. AMI, Agilent, IBM, TSMC) –Packages chips & ships back to designers Our designs will use AMI 1.5µm process (more about this later)

25. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Aside - About MOSIS Some Typical MOSIS Prices (from www.mosis.org) –AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm)$1,080 –AMI 1.5µm 9.4mm X 9.7mm$17,980 –AMI 0.5µm 0-5mm2$5,900 –TSMC 0.25µm 0-10mm2$15,550 –TSMC 0.18µm 0-7mm2$24,500 –TSMC 100-159mm2 $63,250 + $900 X size MOSIS Educational Program (what we use) –AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm)FREE* –AMI 0.5mm “Tiny Chip” (1.5mm X 1.5mm)FREE*

26. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Wires 6 3 3 3 metal 3 metal 2 metal 1 pdiff/ndiff poly 2

27. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Transistors 2 3 1 3 2 5

28. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Vias 4 1 4 2 Types of via: metal1/diff, metal1/poly, metal1/metal2.

29. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Metal 3 via Type: metal3/metal2. Rules: –cut: 3 x 3 –overlap by metal2: 1 –minimum spacing: 3 –minimum spacing to via1: 2

30. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Spacings Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4

31. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Stick diagrams A stick diagram is a cartoon of a layout. Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

32. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Stick Diagrams Key idea: "Stick figure cartoon" of a layout Useful for planning layout –relative placement of transistors –assignment of signals to layers –connections between cells –cell hierarchy

33. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Stick Diagrams

34. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Example - Stick Diagrams Circuit Diagram. Pull-Down Network (The easy part!) Alternatives - Pull-up Network Complete Stick Diagram

35. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Example - Stick Diagrams

36. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Dynamic latch stick diagram VDD in VSS phi phi’ out

37. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Stick Diagram XOR Gate Examples

38. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Hierarchical Stick Diagrams Define cells by outlines & use in a hierarchy to build more complex cells

39. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Cell Connection Schemes External connection - wire cells together Abutment - design cells to connect when adjacent Reflection, mirroring - use to make abutment possible

40. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Example: 2-input multiplexer First cut:

41. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Sticks design of multiplexer Start with NAND gate:

42. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 NAND sticks VDD a VSS out b

43. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005

44. Refined one-bit Mux Design Use NAND cell as black box Arrange easy power connections Vertical connections for allow multiple bits

45. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Multiple-Bit Mux

46. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Cell Mirroring, Overlap Use mirroring, overlap to save area

47. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Example: Layout / Stick Diagram Create a layout for a NAND gate given constraints: –Use minimum-size transistors –Assume power supply lines “pass through” cell from left to right at top and bottom of cell –Assume inputs are on left side of cell –Assume output is on right side of cell –Optimize cell to minimize width –Optimize cell to minimize overall area

48. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Layout Example Circuit Diagram. Exterior of Cell

49. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Example - Magic Layout Overall Layout: 52 X 16

50. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Review - VLSI Levels of Abstraction Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Circuit transistors, parasitics, connections Layout mask layers, polygons Logic gates, flip-flops, latches, connections You are Here

51. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Levels of Abstraction - Perspective Right now, we’re focusing on the “low level”: –Circuit level - transistors, wires, parasitics –Layout level - mask objects We’ll work upward to higher levels: –Logic level - individual gates, latches, flip-flops –Register- transfer level - Verilog HDL –Behavior level - Specifications

52. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 The Challenge of Design Start: higher level (spec) Finish: lower level (implementation) Must meet design criteria and constraints –Design time - how long did it take to ship a product? –Performance - how fast is the clock? –Cost - NRE + unit cost CAD tools - essential in modern design

53. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 CAD Tool Survey: Layout Design Layout Editors Design Rule Checkers (DRC) Circuit Extractors Layout vs. Schematic (LVS) Comparators Automatic Layout Tools –Layout Generators –ASIC: Place/Route for Standard Cells, Gate Arrays

54. Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005 Automatic layout Cell generators (macrocell generators) create optimized layouts for ALUs, etc. Standard cell/sea-of-gates layout creates layout from predesigned cells + custom routing. –Sea-of-gates allows routing over the cell.