1. 1 ERD 2010 ITRS Winter Conference – Makuhari, Japan – December 3, 2010 ITRS Public Conference Emerging Research Devices Jim Hutchby – SRC December 3, 2010 2011 ERD Chapter Preparation

2. Work in Progress --- Not for Publication 2 ERD WG 12/05/10 & 12/2/10 Hiroyugi AkinagaAIST Tetsuya AsaiHokkaido U. Yuji AwanoKeio U. George BourianoffIntel Michel BrillouetCEA/LETI Joe BrewerU. Florida John CarruthersPSU Ralph CavinSRC An ChenGLFOUNDRIES U-In ChungSamsung Byung Jin ChoKAIST Sung Woong ChungHynix Luigi ColomboTI Shamik DasMitre Erik DeBenedictisSNL Simon Deleonibus LETI Bob FontanaIBM Paul FranzonNCSU Akira FujiwaraNTT Christian GamratCEA Mike GarnerIntel Dan HammerstromPSU Wilfried HaenschIBM Tsuyoshi HasegawaNIMS Shigenori HayashiMatsushita Dan HerrSRC Toshiro HiramotoU. Tokyo Matsuo HidakaISTEK Jim HutchbySRC Adrian IonescuEPFL Kiyoshi KawabataRenesas Tech Seiichiro KawamuraSelete Rick KiehlU. C. Davis Suhwan KimSeoul Nation U Hyoungjoon KimSamsung Atsuhiro KinoshitaToshiba Dae-Hong KoYonsei U. Hiroshi KotakiSharp Mark KryderINSIC Zoran KrivokapicGLOBALFOUNDRIES Kee-Won KwonSeong Kyun Kwan U. Jong-Ho LeeHanyang U. Lou LomeIDA Hiroshi MizutaU. Southampton Kwok NgSRC Fumiyuki NiheiNEC Ferdinand PeperNICT Yaw ObengNIST Dave RobertsNantero Barry SchechtmanINSIC Kaushal SinghAMAT Sadas ShankarIntel Atsushi ShiotaJSR Micro Satoshi SugaharaTokyo Tech Shin-ichi TakagiU. Tokyo Ken UchidaToshiba Thomas VogelsangRambus Yasuo WadaToyo U. Rainer WaserRWTH A Franz Widdershoven NXP Jeff WelserNRI/IBM Philip WongStanford U. Dirk Wouters IMEC Kojiro YagamiSony David YehSRC/TI Hiroaki YodaToshiba In-K YooSAIT Yuegang ZhangLLLab Victor ZhirnovSRC Emerging Research Devices Working Group

3. 3 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 year Beyond CMOS Elements Existing technologies New technologies Evolution of Extended CMOS More Than Moore ERD-WG in Japan

4. 4 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 2010-2011 ERD/ERM Workshops Co-sponsored by the National Science Foundation

5. 5 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 Changed Scope of Emerging Research Devices Chapter Scope of Emerging Research Memory Devices changed in 2011 to include: New Storage Class Memory Subsection New Memory Select Device Subsection Scope of Emerging Research Logic Transition of InGaAs & Ge alternate channel MOSFETs to PIDS & FEP. Synchronize better with the Nanoelectronics Research Initiative (NRI) New More-than-Moore Section Expanded Architecture Secton

6. 6 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 2011 ERD Chapter Emerging Memory Devices Emerging Logic Devices Emerging Architectures

7. 7 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 Resistive Memories 2009 Memory Technology Entries Redox Memory Nanoionic memory Electrochemical memory Fuse/Antifuse memory Molecular Memory Electronic Effects Memory Charge trapping Metal-Insulator Transition FE barrier effects Spin Transfer Torque MRAM Nanoelectromechanical Nanowire PCM Macromolecular (Polymer) Capacitive Memory FeFET Memory

8. 8 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 Resistive Memories 2011 Memory Technology Entries Redox Memory Nanoionic memory Electrochemical memory Fuse/Antifuse memory Molecular Memory Electronic Effects Memory Charge trapping Metal-Insulator Transition FE barrier effects Spin Transfer Torque MRAM Nanoelectromechanical Nanowire PCM Macromolecular (Polymer) Capacitive Memory FeFET Memory

9. 9 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 ERD/ERM Memory Technology Assessment Workshop Workshop (For each of eight technologies) (April 6) –Receive expert inputs (pro & con) –Clarify status, potential, and remaining challenges –Formulate discussion/decision points to be considered in the Wednesday ERD/ERM meeting ERD/ERM Working Group Meeting (April 7) –Discuss and reach approximate consensus on potential & challenges for each technology –Determine whether any of the eight candidate memory technologies is sufficiently promising and mature to benefit from accelerated development (Scale beyond the 16nm generation)

10. 10 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 ERD/ERM Memory Technology Assessment Workshop ITRS ERD/ERM identified two emerging memory technologies for accelerated research & development: 1) STT-MRAM and 2) Redox Resistive RAM Redox Memory Cell STT-Memory Cell

11. 11 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 One Diode – One Resistor (1D1R) Memory Cell H-S. P. Wong – Stanford U. Select Device = Diode

12. 12 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 12 Content changes for Emerging Research Memory Section Include Storage Class Memory Include Select Device Transfer Nanowire Phase-Change Memory to Transition Table and to PIDS and FEP Transfer Spin Transfer Torque Magnetic RAM (STT- MRAM) to Transition Table and to PIDS and FEP Reorganize emerging research memory classifications – New category named Redox RRAM.

13. 13 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 2009 ERD Chapter Emerging Memory Devices Emerging Logic Devices Emerging Architectures

14. 14 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 2009 Logic Technology Tables Table 1 – MOSFETs Extending MOSFETs to the End of the Roadmap _____________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Non-conventional Geometry Devices Table 2- Unconventional FETS, Charge-based Extended CMOS Devices _______________ Tunnel FET I-MOS Spin FET SET NEMS switch Negative Cg MOSFET Table 3 - Non-FET, Non Charge-based Beyond CMOS devices _______________ Collective Magnetic Devices Moving domain wall devices Atomic Switch Molecular Switch Pseudo-spintronic Devices Nanomagnetic (M:QCA)

15. 15 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 2011 Logic Technology Tables Table 1 – MOSFETs Extending MOSFETs to the End of the Roadmap _____________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Non-conventional Geometry Devices Table 2- Unconventional FETS, Charge-based Extended CMOS Devices _______________ Tunnel FET I-MOS Spin FET SET NEMS switch Negative Cg MOSFET Excitonic FET Mott FET Table 3 - Non-FET, Non Charge-based Beyond CMOS Devices _______________ Collective Magnetic Devices Spin Transfer Torque Logic Moving domain wall devices Pseudo-spintronic Devices Nanomagnetic (M:QCA) Molecular Switch Atomic Switch

16. 16 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 ERD/ERM Logic Technology Recommended Focus: Carbon-based Nanoelectronics – Carbon Nanotubes and Graphene Conventional Devices Cheianov et al. Science (07) Graphene Veselago lense FET Band gap engineered Graphene nanoribbons Nonconventional Devices Trauzettel et al. Nature Phys. (07) Graphene pseudospintronics Son et al. Nature (07) Graphene Spintronics Graphene quantum dot (Manchester group) P. Kim – Columbia U.

17. 17 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 17 Content changes for Emerging Research Logic Section Add a new section on More-than-More with a focus on devices for wireless applications Transfer InGaAs and Ge MOSFETs to PIDS & FEP Complete transfer of unconventional geometry MOSFETs to PIDS & FEP Transfer SET to More-than-Moore section Add spin transfer torque (STT) majority gate logic Add Mott FET device.

18. 18 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 2009 ERD Chapter Emerging Memory Devices Emerging Logic Devices Emerging Architectures

19. 19 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 Four Architectural Projections 1)Hardware Accelerators execute selected functions faster than software performing it on the CPU. 2)Alternative switches often exhibit emergent, idiosyncratic behavior. They also maybe non- volatile. We should exploit them. 3)CMOS is not going away anytime soon. 4)New switches may improve high utilization accelerators

20. 20 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 Matching Logic Functions & New Switch Behaviors Single Spin Spin Domain Tunnel-FETs NEMS MQCA Molecular Bio-inspired CMOL Excitonics ? Popular Accelerators New Switch Ideas Encrypt / Decrypt Compr / Decompr Reg. Expression Scan Discrete COS Trnsfrm Bit Serial Operations H.264 Std Filtering DSP, A/D, D/A Viterbi Algorithms Image, Graphics Example: Cryptography Hardware Acceleration Operations required:Rotate, Byte Alignment, EXORs, Multiply, Table Lookup Circuits used in Accel: Transmission Gates (T-Gates) New Switch Opportunity: A number of new switches (i.e. T-FETs) dont have thermionic barriers: wont suffer from CMOS Pass-gate V T drop, Body Effect, or Source-Follower delay. Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.

21. 21 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 Emerging Architectures Benchmarking Devices Memory Architecture for Inference (e.g. Morphic )

22. 22 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 Emerging Architectures Benchmarking Devices (moved to Critical Review) Memory Architectures (Expanded )

23. 23 ERD 2010 ITRS Winter Conference – Makuhari, Japan - Dec. 3, 2010 Preparing for re-write of 2011 ERD Chapter With ERM, conducting five FxF workshops co-sponsored by NSF Memory Technology Assessment Workshop (April 2010) Graphene-based and spin-based logic devices (Sept. 2010) Materials issues with Redox-RRAM & STT-MRAM (Nov 2010) III- V MOSFETs: Performance assessment and gating issues (Dec.2010) More than Moore Workshop (April 2011) Logic Devices Transferring InGaAs n-channel and Ge p-channel MOSFET technologies from ERD and ERM to PIDS and FEP in 2011 Transfer non-conventional geometry MOSFETs to PIDS/FEP in 2011 Memory Devices A new taxonomy for categorizing resistive memories introduced. An assessment of new memory devices was completed: STT-MRAM and Redox-RRAM identified for accelerated research and development STT-MRAM & NW PCM proposed to fully transfer to PIDS and FEP in 2011 Will expand scope of memory section to include Storage Class Memory & Select Device Adding a new section for More-than-Moore Emerging Research Technologies Architecture Expanding Architectural Section to include several new approaches Update Memory Architecture section ERD – Key Messages