1. Chapter 5 Enhanced Direct Memory Access (EDMA) DSK 1-day Workshop Student Guide DSK 1-day Workshop Student Guide TMS320C6000 PeripheralsTMS320C6000 Peripherals (207-289)

2. Chapter 5, Slide 2 Learning Objectives  The need for a DMA (EDMA).  Terms and definitions (with examples).  EDMA functionality, including:  Transfer modes and synchronisation.  EDMA interrupt.  Quick DMA (QDMA).  Programming the EDMA, including:  Using the Chip Support Library (CSL).  Example “inout” program using Ping-Pong EDMA.

3. Chapter 5, Slide 3 The Need for a DMA  There are two methods for transferring data from one part of the memory to another, these are using: (1)CPU. (2)DMA.  If a DMA is used then the CPU only needs to configure the DMA. Whilst the transfer is taking place the CPU is then free to perform other operations.

4. Chapter 5, Slide 4 DSK HWI CPU DAC How can we Improve System? McBSP CPU must:  Generate sine wave samples  Respond to McBSP interrupt  Send data to codec (via McBSP) CPU must:  Generate sine wave samples  Respond to McBSP interrupt  Send data to codec (via McBSP) How can we improve system performance?

5. Chapter 5, Slide 5 DSK CPU DAC Block Processing with EDMA McBSP Buffer EDMA CPU  Generates buffer of samples at a time EDMA  Handles McBSP interrupt, reduces CPU int. overhead  Sends data to codec CPU  Generates buffer of samples at a time EDMA  Handles McBSP interrupt, reduces CPU int. overhead  Sends data to codec If EDMA handles the McBSP event, how does the CPU know when to run?

6. Chapter 5, Slide 6 Use EDMA DSK CPU DAC McBSP0 Buffer XEVT0 event 8KHz EDMA interrupt 8KHz  buffersize EDMA  EDMA interrupt tells CPU when to run  Reduces CPU interrupts by factor of buffersize  EDMA interrupt tells CPU when to run  Reduces CPU interrupts by factor of buffersize How does the EDMA work?

7. Chapter 5, Slide 7 Introduction to the EDMA  The ‘C6416 on-chip EDMA controller allows data transfers between the level two (L2) cache memory controller and the device peripherals.  These transfers include:  Cache servicing.  Non-cacheable memory accesses.  User programmed data transfers.  Host accesses.

8. Chapter 5, Slide 8 EDMA Interface  The C621x/C671x/C641x Block diagram. The EDMA allows data transfer to/from any addressable memory spaces.

9. Chapter 5, Slide 9 EDMA Functionality  The data transfer is performed with zero overhead.  It is transparent to the CPU which means that the EDMA and CPU operations can be independent.  However, if the EDMA and CPU both try to access the same memory location arbitration will be performed by the program memory controller.

10. Chapter 5, Slide 10 EDMA Functionality What information is needed by the EDMA to perform transfers? EDMA Source Destination Xfr Count Options mem1A0 A1 A2 A3 A4 A5 mem2 A0 A1 A2 A3 A4 A5 A0A1A2A3A4A5 Source Destination

11. Chapter 5, Slide 11 EDMA Overview Options Source Destination Index Link Addr † Count Reload † 3116150 Transfer Count  16 channels  Stores parameters for 69 more transfer config’s  Per channel: high/low priority, else round-robin 15 Channel 1 Channel 2... Reload 1...... Reload 69 Channel 0 EDMA Reload 2

12. Chapter 5, Slide 12 Enhanced DMA  16 channels  Stores parameters for 69 more transfer config’s  Per channel: high/low priority, else round-robin EDMA Overview Options Source Destination Index Link Addr † Count Reload † 3116150 Transfer Count 15 Channel 1 Channel 2... Reload 1...... Reload 69 Channel 0 EDMA Reload 2 QDMAQuick-DMA  Additional DMA channel  Higher priority  Less transfer overhead  No sync capability  Can’t autoinit (no † registers)

13. Chapter 5, Slide 13 EDMA Features  The ‘C6416 on-chip EDMA controller has the following features:  16 channels.  1 auxiliary channel dedicated for the HPI (not accessible to the user).  1 Quick DMA (QDMA).

14. Chapter 5, Slide 14 EDMA Channel Priorities  The ‘C6416 EDMA channels have two programmable levels of priority (Level 0 reserved only for the L2). * Requests from CPU/L1 and L2 controller Options (PRI 31:29) Priority Level Requestors 000b001b010b011-111b Level 0: Urgent Level 1: High Level 2: Low Reserved L2 Controller * EDMA, QDMA, HPI EDMA, QDMA

15. Chapter 5, Slide 15 EDMA Performance  The ‘C6211/C6711 EDMA can perform element transfers with single-cycle throughput provided there is no conflict.  The following conditions can limit the performance:  EDMA stalls when there are multiple transfer requests on the same priority level.  EDMA accesses to L2 SRAM with lower priority than the CPU.

16. Chapter 5, Slide 16 The smallest piece of information transferred by the EDMA is called... EDMA - How much to move Element ESIZE 00: 32-bits 01: 16-bits 10: 8-bits 11: rsvd ESIZE2827 Elem 1 Elem 2 Elem N Frame........ Frame 1 Frame 2 Frame M Block........ # Elements 0151631 # Frames Options Source Destination Index Link Addr Cnt Reload 310 Transfer Count  N = Element count (ELECNT).  M = Frame count (FRMCNT).  See SPRU190 page 6-5 for more. SPRU190

17. Chapter 5, Slide 17 How the EDMA Works  Reload channel parameters. Options Source Destination Index Link Addr Count Reload 3116150 Transfer Count Channel 15 Channel 1... Channel 0 Reload 69 Reload 1... Reload 0  The EDMA has a parameter RAM composed of: Parameter RAM  Channel parameters.

18. Chapter 5, Slide 18 EDMA: Linking Transfers  Offloads CPU... can reinitialize EDMA all channel registers  Next transfer configuration specified by Link Address  Perform simple re-initialization or create linked-list of events  Useful for ping-pong buffers, data sorting, circular buffers, etc. Options Source Destination Index Link Addr Count Reload 3116150 Transfer Count 15 Channel 1 Channel 2... Reload 1...... Reload 69 Channel 0 Reload 2

19. Chapter 5, Slide 19 How the EDMA Works  The EDMA has a parameter RAM composed of:  Channel parameters.  Reload channel parameters.  The user programs both channel and reload channel parameters.  The channel parameters contain all the information needed for the EDMA in order to perform a transfer.  When a transfer is complete the channel parameters are reloaded from the corresponding reload channel.

20. Chapter 5, Slide 20 EDMA Parameters  The parameters in the parameter table need to be determined before the EDMA can be programmed. Options Source Destination Index Link Addr Count Reload 3116150 Transfer Count

21. Chapter 5, Slide 21 EDMA Parameters (Options) EDMA Channel Options Register ESIZE2DSTCCTCINTSUMPRI 31 29 2DDDUMLINKFS 28 27 26 25 24 23 22 21 20 19 16 10RSVD 15 2 Bit Field 31:2928:272625:242322:212019:1610LabelPRIESIZE2DSSUM2DDDUMTCINTTCCLINKFSDescription Priority levels for the EDMA event Element size (32/16/8-bit) Source dimension Source address update mode Destination dimension Destination address update mode Transfer complete interrupt enable Transfer complete code Link Frame synchronisation

22. Chapter 5, Slide 22 EDMA Parameters (Options)

23. Chapter 5, Slide 23 EDMA Parameters (Options)

24. Chapter 5, Slide 24 EDMA Parameters  Source: Start address of the source.  Transfer Count:  Upper 16 bits [31:16]: Frame count.  Lower 16 bits [15:0]: Element count.  Destination: Start address of the destination.

25. Chapter 5, Slide 25 EDMA Parameters  Index:  Upper 16 bits [31:16]: Frame index.  Lower 16 bits [15:0]: Element index.  Count reload: Value to be reloaded into the element count when a frame is complete (only used in 1-D mode).  Link address: Specifies the address from where the parameters are reloaded. The 16- bit value is added to 0x01A0 xxxx to form the 32-bit address.

26. Chapter 5, Slide 26 EDMA Synchronization  Two methods for initiating a transfer: This is known as unsynchronized EDMA. With this method the CPU writes to the Event Register (ER) through the Event Set Register (ESR) in order to start the EDMA transfer (this can be used to simulate an event). (1)CPU initiated.

27. Chapter 5, Slide 27 In this case the event is latched in the Event Register (ER) which then triggers the transfer. The events that can trigger a transfer are given on the following slide. EDMA Synchronization  Two methods for initiating a transfer: (2)Event triggered. (1)CPU initiated.

28. Chapter 5, Slide 28 EDMA Synchronization - CPU initiated Event Enable Register Event Set Register Event Clear Register Event Register Sync event 1 Start Channel 2 transfer

29. Chapter 5, Slide 29 EDMA Synchronization - Event triggered Event Enable Register Event Set Register Event Clear Register Event Register Sync event 1 Enable Channel 2 Enable Channel 2 1 Start Channel 2 transfer

30. Chapter 5, Slide 30 EDMA Synchronization - Event trigger Disable Event Enable Register Event Set Register Event Clear Register Event Register Sync event 10 Disable Channel 2 Disable Channel 2 0 No transfer Clear event bit 1

31. Chapter 5, Slide 31 EDMA Events  An event can be cleared using the CPU by writing to the Event Clear Register (ECR). Channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event DSPINT TINT0 TINT1 SD_INT EXT_INT4 EXT_INT5 EXT_INT6 EXT_INT7 EDMA_TCC8 EDMA_TCC9 EDMA_TCC10 EMDA_TCC11 XEVT0 REVT0 XEVT1 REVT1 Event Description Host port host to DSP interrupt Timer 0 interrupt Timer 1 interrupt EMIF SDRAM timer interrupt External interrupt pin 4 External interrupt pin 5 External interrupt pin 6 External interrupt pin 7 EDMA transfer complete code 1000b interrupt EDMA TCC 1001b interrupt EDMA TCC 1010b interrupt EDMA TCC 1011b interrupt McBSP0 transmit event McBSP0 receive event McBSP1 transmit event McBSP1 receive event

32. Chapter 5, Slide 32 Transfer Synchronization  The synchronization mode depends on whether or not the transfer is two dimensional.  Therefore first specify that the transfer is either 1-D or 2-D.  0b = 1 dimensional  1b = 2 dimensional 2DS 2DD Options Register 2DS 2DD Options Register 26 23 26 23 Destination dimension Source dimension

33. Chapter 5, Slide 33 1-D Synchronisation  There are two modes of synchronisation in the 1-D transfer mode.  These are:  Element synchronized: each event causes one element to be transferred.  Frame synchronized: each event causes a whole frame to be transferred.  The FS bit is used to specify the synchronization mode.

34. Chapter 5, Slide 34 1-D Transfer Synchronization  Element synchronized (FS=0):  In this case the EDMA transfers each element after receiving the synchronization event until the whole frame is transferred.  The element count is then reloaded and the frame count decremented.  The frame index is then added to the last element address to calculate the next frame start address.  If the link is enabled (LINK=1b) then the transfer parameters are reloaded. FS Options Register FS Options Register 0

35. Chapter 5, Slide 35 Example: 1-D Transfer with FS=0  ESIZE = 10b  ELECNT = 4  FRMCNT = 0  SUM = 01b DST: 8 bits 8 9 10 11 8-bit Pixels 123456 712 131415161718 192021222324 252627282930 891011 8 9 10 11 891011 SRC: SourceDestination Sync event  00b = 32-bits  01b = 16-bits  10b = 8-bits  11b = Reserved  00b = Fixed  01b = Increment  10b = Decrement  11b = Modified by INDEX  FRMCNT = M - 1

36. Chapter 5, Slide 36 Example: 1-D Transfer with FS=0 DST: 8 bits 8 9 10 11 8-bit Pixels 123456 712 131415161718 192021222324 252627282930 891011 8 9 10 11 891011 Source = SRC+7 Destination = DST FRMIDX ELEIDX Link Addr Count Reload 3116150 FRMCNT = 0 ELECNT = 4 ESIZE ESIZE Options 10 10 SRC: SourceDestination

37. Chapter 5, Slide 37 DST: 8 bits 6 10 14 18 22 Example: 1-D Transfer with FS=0  ESIZE = 10b (8-bits)  ELECNT = 5, FRMCNT = 0  SUM = 11b  ELEIDX = 4 8-bit Pixels 1234 5 9101112 13141516 17181920 678 21222324 25262728 6 10 14 18 22 6 10 14 18 22 SourceDestination SRC: In this mode: Next frame addr = Last element addr + FRMIDX Sync event

38. Chapter 5, Slide 38 1-D Transfer Synchronisation  Frame synchronized (FS=1):  In this case the EDMA transfers a whole frame after receiving the synchronization event.  In this mode the frame index no longer represents the difference between the address of the last element of the frame and the start address of the next frame.  The frame index is added to the start address of the frame to derive the start address of the next frame.  See the example on the following slide.

39. Chapter 5, Slide 39 16 bits 8 10 12 16 36... 40 42 44... 16-bit Data 1234567 121314 15161718192021 22232425262728 891011 29303132333435 36373839404142 43444546474849 Example: 1-D Transfer with FS=1  All elements in a frame are offset by ELEIDX bytes.  All frames in a block are offset by FRMIDX bytes. DST: 8 10 12 12810 SRC: SourceDestination 201618 282426 3234 36 16... 36 40 42 44 4042 44 Sync event

40. Chapter 5, Slide 40 16 bits 8 10 12 16 36... 40 42 44 16-bit Data 1234567 121314 15161718192021 22232425262728 891011 29303132333435 36373839404142 43444546474849 Example: 1-D Transfer with FS=1  ESIZE = 01b (16bits)  ELECNT = 3  FRMCNT = 4  SUM = 11b, 2DS = 0, FS = 1  FRMIDX = 16, ELEIDX = 4 DST: 8 10 12 12810 SRC: SourceDestination 201618 282426 36 3234 16... 36 40 42 44 4042 44 In this mode: Next frame addr = First element addr + FRMIDX

41. Chapter 5, Slide 41 DST: 8 bits 8-bit Pixels 123456 712 131415161718 192021222324 252627282930 891011 SRC:SourceDestination2 4 14 16 26 28 Example: 1-D Transfer with FS=1 24 1416 2628  ESIZE = 10b  ELECNT = 2  FRMCNT = 2  SUM = 01b, 2DS =0b, FS = 1  FRMIDX = 12, ELEIDX = 2 2 4 14 16 26 28 Sync event

42. Chapter 5, Slide 42 2-D Synchronization  There are two modes of synchronization in the 2-D transfer mode.  These are:  Array synchronized: each event causes one line of the array to be transferred.  Block synchronized: each event causes the entire block to be transferred.  The FS bit is used to specify the synchronization mode.

43. Chapter 5, Slide 43 2-D Transfer Synchronization  Array synchronized (FS=0):  This is the same as the 1-D frame synchronisation mode except that the elements are all contiguous.  One array is transferred per synchronisation event.  The frame count is equal to the number of frames minus one because when the FRMCNT=0 the complete transfer parameters are reloaded after sending the last transfer request to the address generation hardware.  The frame index is added to the start address of the frame to derive the next frame address.

44. Chapter 5, Slide 44 16-bit Data 1234567 121314 15161718192021 22232425262728 891011 29303132333435 36373839404142 43444546474849 Example: 2-D Transfer with FS=0  With 2D transfers there is no indexing between elements, therefore ELEIDX is not used in 2D transfers.  To specify a 2D source set 2DS in channel options. 16 bits 8 9 10 11... 15 40 DST: 911810 SRC: SourceDestination 8 9 10 11 16181517 23252224 30322931 37403638 15... 40 Sync event

45. Chapter 5, Slide 45 16-bit Data 1234567 121314 15161718192021 22232425262728 891011 29303132333435 36373839404142 43444546474849 Example: 2-D Transfer with FS=0 16 bits 8 9 10 11... 15 40 DST: 911810 SRC: SourceDestination 8 9 10 11 16181517 23252224 30322931 37403638 15... 40  ESIZE = 01b (16bits)  ELECNT = 4, FRMCNT = 4  SUM = 01b, 2DS = 1b  FRMIDX = 14, ELEIDX = N/A In this mode: Next frame addr = First element addr + FRMIDX

46. Chapter 5, Slide 46 2-D Transfer Synchronization  Block synchronized (FS=1):  This is the same as the 1-D frame synchronization mode except that the elements are all contiguous.  The entire block is transferred following the synchronization event.  At the end of each frame the frame index is added to the last element address to calculate the next frame start address.

47. Chapter 5, Slide 47 Example: 2-D Transfer with FS=1 16-bit Data 1234567 121314 15161718192021 22232425262728 891011 29303132333435 36373839404142 43444546474849 16 bits 8 9 10 11... 15 40 DST: 911810 SRC: 8 9 10 11 16181517 23252224 30322931 37403638 15... 40 SourceDestination  ESIZE = 01b (16bits)  ELECNT = 4, FRMCNT = 4  SUM = 01b, 2DS = 1b  FRMIDX = 8, ELEIDX = N/A In this mode: Next frame addr = Last element addr + FRMIDX Sync event

48. Chapter 5, Slide 48 EDMA Interrupt Generation  The EDMA controller is responsible for generating transfer completion interrupts to the CPU.  The EDMA generates a single interrupt (EDMA_INT) to the CPU on behalf of all 16 channels.  The programmer has to read the CIPR register to determine which channel caused the interrupt or which interrupts are pending while the ISR is being serviced.

49. Chapter 5, Slide 49 EDMA Interrupt Generation TCINTTCC 312019160OPTIONS  Each channel has an OPTIONS register  OPTIONS contains:  TCINT- do you want to interrupt CPU?  TCC - 4 bit completion code (your choice)

50. Chapter 5, Slide 50 EDMA Interrupt Generation TCINTTCC 312019160OPTIONS  Each channel has an OPTIONS register  OPTIONS contains:  TCINT- do you want to interrupt CPU?  TCC - 4 bit completion code (your choice)  Upon completion:If you set TCINT = 1, then CIPR bit equal to TCC value (you set) is set to one rsvdCIP15CIP14CIP8CIP7CIP6CIP5CIP4CIP3CIP2CIP1CIP0 311514876543210CIPR

51. Chapter 5, Slide 51 EDMA Interrupt Generation TCINTTCC 312019160OPTIONS  Each channel has an OPTIONS register  OPTIONS contains:  TCINT- do you want to interrupt CPU?  TCC - 4 bit completion code (your choice)  Upon completion:If you set TCINT = 1, then CIPR bit equal to TCC value (you set) is set to one  CIER bit must be set for CPU to be interrupted  Only 1 EDMA interrupt to CPU. Upon int, CPU should service all pending channels set in CIPR rsvdCIP15CIP14CIP8CIP7CIP6CIP5CIP4CIP3CIP2CIP1CIP0 311514876543210CIPR CIER rsvdCIE15CIE14CIE8CIE7CIE6CIE5CIE4CIE3CIE2CIE1CIE0

52. Chapter 5, Slide 52 Chaining EDMA Transfers  After completion of an EDMA channel transfer another EDMA channel transfer can be triggered.  This triggering mechanism is similar to event triggering.  However this method can only be used to trigger EDMA channels 8 to 11.

53. Chapter 5, Slide 53 Chaining EDMA Transfers  In addition to setting the TCINT and TCC bits there is also another register, the Channel Chain Enable Register (CCER) that must be set. CCE11CCE10ReservedCCE8CCE9Reserved1110 7 0 89 31 12 Channel Chain Enable Register (CCER)

54. Chapter 5, Slide 54 Chaining EDMA Transfers Channel Changing … ah, that is, Channel Chaining CCER rsvdCCE11CCE10CCE8 rsvd CCE9  Upon completion, one EDMA channel can kick-off another  Rather than setting CIER bit (to enable CPU int), set CCER to enable channel 8-11 to start TCINTTCC 312019160 OPTIONS CIPR CIP11CIP10CIP8 CIP9

55. Chapter 5, Slide 55 EDMA Interrupt Generation

56. Chapter 5, Slide 56 Options Source Destination Index Link Addr Count Reload 3116150 Transfer Count EDMA_Handle myEDMA, myLNK; EDMA_Config myConfig = { options, source, length, destination, index, reload:link }; EDMA_Handle myEDMA, myLNK; EDMA_Config myConfig = { options, source, length, destination, index, reload:link }; edma_init () { 1. open XEVT0 EDMA channel // McBSP0 transmit event 2. allocate LINK parameter location 3. update EDMA_Config with LINK location 4. configure EDMA channel & link location 5. enable EDMA channel 6. enable EDMA interrupt to CPU } edma_init () { 1. open XEVT0 EDMA channel // McBSP0 transmit event 2. allocate LINK parameter location 3. update EDMA_Config with LINK location 4. configure EDMA channel & link location 5. enable EDMA channel 6. enable EDMA interrupt to CPU } EDMA Config

57. Chapter 5, Slide 57 Options Source Destination Index Link Addr Count Reload 3116150 Transfer Count EDMA_Handle myEDMA, myLNK; EDMA_Config myConfig = { options, source, length, destination, index, reload:link }; EDMA_Handle myEDMA, myLNK; EDMA_Config myConfig = { options, source, length, destination, index, reload:link }; EDMA Config void edma_init (void) { hEdma = EDMA_open( EDMA_CHA_XEVT0, EDMA_OPEN_RESET ); hEdmaLINK = EDMA_allocTable( -1 ); myConfig.rld = EDMA_MK_RLD(myLNK,0); EDMA_config(hEdma, &my_edma_Config); EDMA_config(hEdmaLINK, &my_edma_Config); EDMA_enableChannel( hEdma ); EDMA_intClear(5); EDMA_intEnable(5); } void edma_init (void) { hEdma = EDMA_open( EDMA_CHA_XEVT0, EDMA_OPEN_RESET ); hEdmaLINK = EDMA_allocTable( -1 ); myConfig.rld = EDMA_MK_RLD(myLNK,0); EDMA_config(hEdma, &my_edma_Config); EDMA_config(hEdmaLINK, &my_edma_Config); EDMA_enableChannel( hEdma ); EDMA_intClear(5); EDMA_intEnable(5); }

58. Chapter 5, Slide 58 DSK edma_HWI DAC McBSP EDMA Interrupt (to CPU) // Interrupt Service Routine edma_HWI() { block_sine(); } // Interrupt Service Routine edma_HWI() { block_sine(); } Buffer EDMA

59. Chapter 5, Slide 59 DSK edma_HWI DAC McBSP block_sine() Buffer EDMA short buffer[128]; main() { init_EDMA(); init_HWI()... } short buffer[128]; main() { init_EDMA(); init_HWI()... } void block_sine() { for (i = 0; i < 128; i++) { buffer[i] = sineGen(); }} void block_sine() { for (i = 0; i < 128; i++) { buffer[i] = sineGen(); }}

60. Chapter 5, Slide 60 Introduction to the Quick DMA (QDMA)  The QDMA provides a very efficient way of moving data.  It supports nearly all the same modes as the EDMA however transfer requests are submitted faster.  However it does not support reload of a count or link.  Therefore the QDMA is suited to one-off moves of blocks of data internally whereas the EDMA is suited to moving data between peripherals and the memory.

61. Chapter 5, Slide 61 QDMA Registers  The QDMA is programmed via two sets of five write-only memory mapped registers:  Writing to the first set of registers configures the QDMA but does not submit a request.  Writing to the second set of registers configures the QDMA and submits a transfer request. Options Source Destination Index 3116150 Transfer Count Options Source Destination Index 3116150 Transfer Count 0x0200 0000 0x0200 0004 0x0200 0008 0x0200 000c 0x0200 0010 0x0200 0020 0x0200 0024 0x0200 0028 0x0200 002c 0x0200 0030 QDMA Registers (Set 1) QDMA Pseudo Registers (Set 2)

62. Chapter 5, Slide 62 QDMA Options Register EDMA Channel Options Register ESIZE2DSTCCTCINTSUMPRI 31 29 2DDDUMRSVDFS 28 27 26 25 24 23 22 21 20 19 16 10RSVD 15 2 Bit Field 31:2928:272625:242322:212019:160LabelPRIESIZE2DSSUM2DDDUMTCINTTCCFSDescription Priority levels for the QDMA event Element size (32/16/8-bit) Source dimension Source address update mode Destination dimension Destination address update mode Transfer complete interrupt enable Transfer complete code Frame synchronisation

63. Chapter 5, Slide 63 Other QDMA Registers  Source: Start address of the source.  Transfer Count:  Upper 16 bits [31:16]: Frame count.  Lower 16 bits [15:0]: Element count.  Destination: Start address of the destination.  Index:  Upper 16 bits [31:16]: Frame index.  Lower 16 bits [15:0]: Element index.

64. Chapter 5, Slide 64 Configuring the QDMA  Five writes are required to submit a request:  The first four registers are configured by writing to the corresponding QDMA registers.  The fifth register is configured by writing to the corresponding pseudo register causing the request to be submitted. Options Source Destination Index 3116150 Transfer Count Options Source Destination Index 3116150 Transfer Count 0x0200 0000 0x0200 0004 0x0200 0008 0x0200 000c 0x0200 0010 0x0200 0020 0x0200 0024 0x0200 0028 0x0200 002c 0x0200 0030 QDMA Registers (Set 1) QDMA Pseudo Registers (Set 2)

65. Chapter 5, Slide 65 Features of the QDMA  All transfers are frame synchronised.  Although linking is not supported, completion interrupts and channel chaining are supported.  The values held in the registers are not changed by the hardware hence the same transfer can be repeated by a single write to one of the pseudo registers.

66. Chapter 5, Slide 66 Programming the EDMA  There are three methods available for programming the EDMA: (1)Writing directly to the EDMA registers. (2)Using the Chip Support Library (CSL). (3)Graphically using the DSP/BIOS GUI interface.

67. Chapter 5, Slide 67 Programming the EDMA - Direct (1)Writing directly to the EDMA registers:  Although this method is straightforward, it relies on a good understanding of the EDMA and the DSP memory map.  This method is tedious and prone to errors. #include #include void EDMA_setup (void) { *(unsigned volatile int *) ECR = 0xffff; *(unsigned volatile int *) EER = 0xffff; *(unsigned volatile int *) CIPR = 0xffff; *(unsigned volatile int *) CIER = 0xffff;...}

68. Chapter 5, Slide 68 Programming the EDMA - CSL (2)Using the Chip Support Library:  The CSL provides a C language interface for configuring and controlling the on-chip peripherals, in this case the EDMA.  The library is modular with each module corresponding to a specific peripheral. This has the advantage of reducing the code size.  Some modules rely on other modules also being included, for example the IRQ module is required when using the EDMA module.

69. Chapter 5, Slide 69 Programming the EDMA - CSL  The CSL can be divided into four sections:  See Code Composer Studio help for more details.

70. Chapter 5, Slide 70 Programming the EDMA - CSL Example: Polling #includes Uint16 src[N], dst[N]; // Global Declarations void TEST_edma() { Int16 i; Int16 i; EDMA_Handle hEdmaCha8; // EDMA number 8 is used in this example EDMA_Handle hEdmaCha8; // EDMA number 8 is used in this example EDMA_Config edmaCfg8 = { EDMA_Config edmaCfg8 = { EDMA_FMKS(OPT, PRI, URGENT) | // highest priority for EDMA EDMA_FMKS(OPT, PRI, URGENT) | // highest priority for EDMA EDMA_FMKS(OPT, ESIZE, 16BIT) | // element size is 16 bits EDMA_FMKS(OPT, ESIZE, 16BIT) | // element size is 16 bits EDMA_FMKS(OPT, 2DS, NO) | // 1-dimensional transfer from source EDMA_FMKS(OPT, 2DS, NO) | // 1-dimensional transfer from source EDMA_FMKS(OPT, SUM, INC) | // increment source address while transferring elements EDMA_FMKS(OPT, SUM, INC) | // increment source address while transferring elements EDMA_FMKS(OPT, 2DD, NO) | // 1-dimensional transfer to destination EDMA_FMKS(OPT, 2DD, NO) | // 1-dimensional transfer to destination EDMA_FMKS(OPT, DUM, INC) | // increment dest address while transferring elements EDMA_FMKS(OPT, DUM, INC) | // increment dest address while transferring elements EDMA_FMKS(OPT, TCINT, YES) | // indicate transfer completion EDMA_FMKS(OPT, TCINT, YES) | // indicate transfer completion EDMA_FMK (OPT, TCC, TCC_NUM) | // set bit 8 upon transfer completion EDMA_FMK (OPT, TCC, TCC_NUM) | // set bit 8 upon transfer completion EDMA_FMKS(OPT, LINK, NO) | // after transfer completion don't link to other configuration EDMA_FMKS(OPT, LINK, NO) | // after transfer completion don't link to other configuration EDMA_FMKS(OPT, FS, YES), // select frame-sync. An event implies a transfer of a frame of elemnts EDMA_FMKS(OPT, FS, YES), // select frame-sync. An event implies a transfer of a frame of elemnts (Uint32)src, // source address (Uint32)src, // source address EDMA_FMKS(CNT, FRMCNT, OF(0)) | // 0 - means: transfer only one frame EDMA_FMKS(CNT, FRMCNT, OF(0)) | // 0 - means: transfer only one frame EDMA_FMKS(CNT, ELECNT, OF(16)), // each frame (one in this example) consists of 16 elements EDMA_FMKS(CNT, ELECNT, OF(16)), // each frame (one in this example) consists of 16 elements (Uint32)dst, // dest address (Uint32)dst, // dest address }; }; … // to be continued … // to be continued

71. Chapter 5, Slide 71 Programming the EDMA - CSL Example : Polling /* Set src values and clear destination */ for (i = 0; i < N; i++) { for (i = 0; i < N; i++) { src[i] = i; src[i] = i; dst[i] = 0; dst[i] = 0; } /* Configure EDMA */ /* Configure EDMA */ hEdmaCha8 = EDMA_open(8, EDMA_OPEN_RESET); hEdmaCha8 = EDMA_open(8, EDMA_OPEN_RESET); EDMA_config(hEdmaCha8, &edmaCfg8); EDMA_config(hEdmaCha8, &edmaCfg8); /* Start CPU initiated EDMA transfer by setting bit 24 in ESR */ EDMA_setChannel(hEdmaCha8); EDMA_setChannel(hEdmaCha8); /* Poll EDMA interrupt to see if its done */ while (!EDMA_intTest(TCC_NUM)); while (!EDMA_intTest(TCC_NUM)); { ; } /* We are done, so close EDMA channel */ /* We are done, so close EDMA channel */ EDMA_close(hEdmaCha8); EDMA_close(hEdmaCha8); /* Check data */ for (i = 0; i < N; i++) for (i = 0; i < N; i++) if (dst[i] != src[i]){ if (dst[i] != src[i]){ printf("failed\n"); } printf("failed\n"); } /* Test passed */ printf("success\n"); printf("success\n");}

72. Chapter 5, Slide 72 Programming the EDMA - CSL Example : Polling main(){ /* Call BSL init */ /* Call BSL init */ DSK6416_init(); DSK6416_init(); printf("Start EDMA test\n"); TEST_edma();}

73. Chapter 5, Slide 73 Programming the EDMA - CSL Example : Int #includes Uint16 src[N], dst[N]; // Global Declarations void TEST_edma() { Int16 i; Int16 i; EDMA_Handle hEdmaCha8; // EDMA number 8 is used in this example EDMA_Handle hEdmaCha8; // EDMA number 8 is used in this example EDMA_Config edmaCfg8 = { EDMA_Config edmaCfg8 = { EDMA_FMKS(OPT, PRI, URGENT) | // highest priority for EDMA EDMA_FMKS(OPT, PRI, URGENT) | // highest priority for EDMA EDMA_FMKS(OPT, ESIZE, 16BIT) | // element size is 16 bits EDMA_FMKS(OPT, ESIZE, 16BIT) | // element size is 16 bits EDMA_FMKS(OPT, 2DS, NO) | // 1-dimensional transfer from source EDMA_FMKS(OPT, 2DS, NO) | // 1-dimensional transfer from source EDMA_FMKS(OPT, SUM, INC) | // increment source address while transferring elements EDMA_FMKS(OPT, SUM, INC) | // increment source address while transferring elements EDMA_FMKS(OPT, 2DD, NO) | // 1-dimensional transfer to destination EDMA_FMKS(OPT, 2DD, NO) | // 1-dimensional transfer to destination EDMA_FMKS(OPT, DUM, INC) | // increment dest address while transferring elements EDMA_FMKS(OPT, DUM, INC) | // increment dest address while transferring elements EDMA_FMKS(OPT, TCINT, YES) | // indicate transfer completion EDMA_FMKS(OPT, TCINT, YES) | // indicate transfer completion EDMA_FMK (OPT, TCC, TCC_NUM) | // set bit 8 upon transfer completion EDMA_FMK (OPT, TCC, TCC_NUM) | // set bit 8 upon transfer completion EDMA_FMKS(OPT, LINK, NO) | // after transfer completion don't link to other configuration EDMA_FMKS(OPT, LINK, NO) | // after transfer completion don't link to other configuration EDMA_FMKS(OPT, FS, YES), // select frame-sync. An event implies a transfer of a frame of elemnts EDMA_FMKS(OPT, FS, YES), // select frame-sync. An event implies a transfer of a frame of elemnts (Uint32)src,// source address (Uint32)src,// source address EDMA_FMKS(CNT, FRMCNT, OF(0)) | // 0 - means: transfer only one frame EDMA_FMKS(CNT, FRMCNT, OF(0)) | // 0 - means: transfer only one frame EDMA_FMKS(CNT, ELECNT, OF(16)), // each frame (one in this example) consists of 16 elements EDMA_FMKS(CNT, ELECNT, OF(16)), // each frame (one in this example) consists of 16 elements (Uint32)dst,// dest address (Uint32)dst,// dest address }; }; … //to be continued

74. Chapter 5, Slide 74 Programming the EDMA - CSL Example : Int /* Set src values and clear destination */ /* Set src values and clear destination */ for (i = 0; i < N; i++) { for (i = 0; i < N; i++) { src[i] = i; src[i] = i; dst[i] = 0; dst[i] = 0; } } /* Configure EDMA */ /* Configure EDMA */ hEdmaCha8 = EDMA_open (8, EDMA_OPEN_RESET); hEdmaCha8 = EDMA_open (8, EDMA_OPEN_RESET); EDMA_config (hEdmaCha8, &edmaCfg8); EDMA_config (hEdmaCha8, &edmaCfg8); EDMA_intEnable (TCC_NUM); // enable CIER bit 8 to cause a interrupt to CPU EDMA_intEnable (TCC_NUM); // enable CIER bit 8 to cause a interrupt to CPU IRQ_clear (IRQ_EVT_EDMAINT); // clear any possible pending interrupts IRQ_clear (IRQ_EVT_EDMAINT); // clear any possible pending interrupts IRQ_enable (IRQ_EVT_EDMAINT); // enable EDMA interrupt enterring CPU IRQ_enable (IRQ_EVT_EDMAINT); // enable EDMA interrupt enterring CPU IRQ_globalEnable (); // actually, not necessary, since this is done by DSP/BIOS IRQ_globalEnable (); // actually, not necessary, since this is done by DSP/BIOS /* Start CPU initiated EDMA transfer by setting bit 24 in ESR */ /* Start CPU initiated EDMA transfer by setting bit 24 in ESR */ EDMA_setChannel (hEdmaCha8); EDMA_setChannel (hEdmaCha8);}

75. Chapter 5, Slide 75 Programming the EDMA - CSL Example : Int void edmaISR(void) { if (EDMA_intTest (TCC_NUM)){ if (EDMA_intTest (TCC_NUM)){ SWI_post (&SWIedma); } } void SWIcheckEdma (void) void SWIcheckEdma (void) { int i; int i; /* Check data */ /* Check data */ for (i = 0; i < N; i++) for (i = 0; i < N; i++) if (dst[i] != src[i]){ if (dst[i] != src[i]){ printf ("failed\n"); printf ("failed\n"); return; return; } /* Test passed */ /* Test passed */ printf ("success\n"); printf ("success\n");}

76. Chapter 5, Slide 76 Programming the EDMA - CSL Example : Int main(){ /* Call BSL init */ /* Call BSL init */ DSK6416_init(); DSK6416_init(); printf("Start EDMA test\n"); TEST_edma();}

77. Chapter 5, Slide 77 Programming the EDMA - CSL Example : Timer #includes Uint16 src[N], dst[N]; // Global Declarations TIMER_Handle hTimer; // handle for the timer device // int numTimer1Intr = 0; // timer-count void TEST_edma() { Int16 i; Int16 i; EDMA_Handle hEdmaCha2; // EDMA number 8 is used in this example EDMA_Handle hEdmaCha2; // EDMA number 8 is used in this example EDMA_Config edmaCfg2 = { EDMA_Config edmaCfg2 = { EDMA_FMKS (OPT, PRI, URGENT) | // highest priority for EDMA EDMA_FMKS (OPT, PRI, URGENT) | // highest priority for EDMA EDMA_FMKS (OPT, ESIZE, 16BIT) | // element size is 16 bits EDMA_FMKS (OPT, ESIZE, 16BIT) | // element size is 16 bits EDMA_FMKS (OPT, 2DS, NO) | // 1-dimensional transfer from source EDMA_FMKS (OPT, 2DS, NO) | // 1-dimensional transfer from source EDMA_FMKS (OPT, SUM, INC) | // increment source address while transferring elements EDMA_FMKS (OPT, SUM, INC) | // increment source address while transferring elements EDMA_FMKS (OPT, 2DD, NO) | // 1-dimensional transfer to destination EDMA_FMKS (OPT, 2DD, NO) | // 1-dimensional transfer to destination EDMA_FMKS (OPT, DUM, INC) | // increment dest address while transferring elements EDMA_FMKS (OPT, DUM, INC) | // increment dest address while transferring elements EDMA_FMKS (OPT, TCINT, YES) | // indicate transfer completion EDMA_FMKS (OPT, TCINT, YES) | // indicate transfer completion EDMA_FMK (OPT, TCC, TCC_NUM) | // set bit 8 upon transfer completion EDMA_FMK (OPT, TCC, TCC_NUM) | // set bit 8 upon transfer completion EDMA_FMKS (OPT, LINK, NO) | // after transfer completion don't link to other configuration EDMA_FMKS (OPT, LINK, NO) | // after transfer completion don't link to other configuration EDMA_FMKS (OPT, FS, NO), // select frame-sync. An event implies a transfer of a frame of elemnts EDMA_FMKS (OPT, FS, NO), // select frame-sync. An event implies a transfer of a frame of elemnts (Uint32)src, // source address (Uint32)src, // source address EDMA_FMKS (CNT, FRMCNT, OF(0)) | // 0 - means: transfer only one frame EDMA_FMKS (CNT, FRMCNT, OF(0)) | // 0 - means: transfer only one frame EDMA_FMKS (CNT, ELECNT, OF(16)), // each frame (one in this example) consists of 16 elements EDMA_FMKS (CNT, ELECNT, OF(16)), // each frame (one in this example) consists of 16 elements (Uint32)dst, // dest address (Uint32)dst, // dest address }; };

78. Chapter 5, Slide 78 Programming the EDMA - CSL Example : Timer /* Set src values and clear destination */ /* Set src values and clear destination */ for (i = 0; i < N; i++) { for (i = 0; i < N; i++) { src[i] = i; src[i] = i; dst[i] = 0; dst[i] = 0; } } /* Configure EDMA */ /* Configure EDMA */ hEdmaCha2 = EDMA_open (2, EDMA_OPEN_RESET); hEdmaCha2 = EDMA_open (2, EDMA_OPEN_RESET); EDMA_config (hEdmaCha2, &edmaCfg2); EDMA_config (hEdmaCha2, &edmaCfg2); EDMA_intEnable (TCC_NUM); // enable CIER bit 8 to cause a interrupt to CPU EDMA_intEnable (TCC_NUM); // enable CIER bit 8 to cause a interrupt to CPU IRQ_clear (IRQ_EVT_EDMAINT); // clear any possible pending interrupts IRQ_clear (IRQ_EVT_EDMAINT); // clear any possible pending interrupts IRQ_enable (IRQ_EVT_EDMAINT); // enable EDMA interrupt enterring CPU IRQ_enable (IRQ_EVT_EDMAINT); // enable EDMA interrupt enterring CPU IRQ_globalEnable(); // actually, not necessary, since this is done by DSP/BIOS IRQ_globalEnable(); // actually, not necessary, since this is done by DSP/BIOS // create handle for timer 1 hTimer = TIMER_open (TIMER_DEV1, TIMER_OPEN_RESET); // configure timer TIMER_configArgs (hTimer, TIMER_CTL_OF (0x200), TIMER_PRD_OF (TPRD), TIMER_CNT_OF (0) ); ); //Enable timer interrupt // IRQ_enable (IRQ_EVT_TINT1); // timer-count TIMER_start (hTimer); EDMA_enableChannel (hEdmaCha2); }

79. Chapter 5, Slide 79 Programming the EDMA - CSL Example : Timer void timerISR(void) // timer-count void timerISR(void) // timer-count{ // numTimer1Intr++; // timer-count } void edmaISR(void) void edmaISR(void) { if (EDMA_intTest(TCC_NUM)){ SWI_post(&SWIedma); } } void SWIcheckEdma(void) void SWIcheckEdma(void) { int i; /* Check data */ /* Check data */ for (i = 0; i < N; i++) for (i = 0; i < N; i++) if (dst[i] != src[i]) { if (dst[i] != src[i]) { printf("failed\n"); printf("failed\n"); return; return; } /* Test passed */ /* Test passed */ printf("success\n"); printf("success\n");}

80. Chapter 5, Slide 80 Programming the EDMA - CSL Example : Timer main(){ /* Call BSL init */ /* Call BSL init */ // DSK6416_init(); // DSK6416_init(); printf("Start EDMA test\n"); TEST_edma(); // go to DSP/BIOS }

81. Chapter 5, Slide 81 Programming the EDMA - CSL Example Ping_data EDMA Outbuff swiProcess Func Buffer (ping) Buffer (pong ) Pong_data Sync event Timer 1 1000 1000 1000 1000 2000

82. Chapter 5, Slide 82 Programming the EDMA - CSL Example Ping_data EDMA Outbuff swiProcess Func Buffer (ping) Buffer (pong ) Pong_data Sync event Timer 1 1000 1000 1000 1000 2000 2000 2000 200010001000 1000 Processing by CPU

83. Chapter 5, Slide 83 Programming the EDMA - CSL Example Ping_data EDMA Outbuff swiProcess Func Buffer (ping) Buffer (pong ) Pong_data Sync event Timer 1 1001 1000 1000 1000 2000 1001 1001 100120002000 2000 Processing by CPU 2000 2000 2000

84. Chapter 5, Slide 84  CSL programming procedure: (1)Create handles for the EDMA channel and reload parameters: (2)Create the EDMA configuration: Programming the EDMA - CSL Example EDMA_Handle hEdma; EDMA_Config cfgEdma;

85. Chapter 5, Slide 85  CSL programming procedure (cont): (3)Create the configuration structures for the ping and pong channels: Programming the EDMA - CSL Example EDMA_Config cfgEdmaPong = { 0x28720002, EDMA_SRC_OF(McBSP0_DRR), EDMA_CNT_OF(BUFF_SZ), EDMA_DST_OF((unsigned int)cin_data), EDMA_IDX_OF(0x00000004), }; EDMA_RLD_OF(0x00000000) }; EDMA_Config cfgEdmaPing = { EDMA_Config cfgEdmaPing = { 0x28720002, EDMA_SRC_OF(McBSP0_DRR), EDMA_CNT_OF(BUFF_SZ), EDMA_DST_OF((unsigned int)in_data), EDMA_IDX_OF(0x00000004), }; EDMA_RLD_OF(0x00000000) };

86. Chapter 5, Slide 86 Pong Configuration : 0x403A0002, //Options FS=0 (element sync); bits 0 LINK=1 (concatenating of blocks of frames); bits 1 TCC=1010b (CIPR[0xA] bit is set upon transfer completion); bits 19-16 TCINT=1 (Set CIPR[0xA] bit upon transfer complete; if CIPR[0xA] is also set, then an interrupt to the CPU is generated); bits 20 SUM=0 (source address not updated); bits 25-24 DUM = 01b (destination address is incremented by element size ); bits 22-21 2DD=2DS=0 (non 2D synchronization) ; bits 26, 23 ESIZE=00b (32-bits elements); bits 28-27 PRI=010b (Low priority); bits 31-29 EDMA_SRC_OF(&pong_data), // Source address: (address of pong data integer) EDMA_CNT_OF(BUFF_SZ), // Transfer count: FC=0 (one frame); // EC=BUFF_SZ EDMA_DST_OF(pong), // Destination address (pong buffer) EDMA_IDX_OF(0x00000004), // Index:FIX=0; EIX=4 EDMA_RLD_OF(0x00000000) // Element count reload and link address

87. Chapter 5, Slide 87 Pong Configuration using CSL EDMA_Config cfgEdmaPong = { EDMA_OPT_RMK( EDMA_OPT_RMK( EDMA_OPT_PRI_LOW, EDMA_OPT_PRI_LOW, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_NO, EDMA_OPT_2DS_NO, EDMA_OPT_SUM_NONE, EDMA_OPT_SUM_NONE, EDMA_OPT_2DD_NO, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_INC, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(TCCINTNUM), EDMA_OPT_TCC_OF(TCCINTNUM), EDMA_OPT_LINK_YES, EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO EDMA_OPT_FS_NO ), ), EDMA_SRC_OF(&pong_data), EDMA_SRC_OF(&pong_data), EDMA_CNT_OF(BUFF_SZ), EDMA_CNT_OF(BUFF_SZ), EDMA_DST_OF(pong), EDMA_DST_OF(pong), EDMA_IDX_OF(0x00000004), EDMA_IDX_OF(0x00000004), EDMA_RLD_OF(0x00000000) EDMA_RLD_OF(0x00000000)};

88. Chapter 5, Slide 88 Programming the EDMA - CSL Example  CSL programming procedure (cont): (4)Map the event to a physical interrupt (see Interrupt section): This maps the EDMA_INT interrupt to CPU_INT8. (5)Set the interrupt dispatcher configuration structure (see Interrupt section): IRQ_map (IRQ_EVT_EDMAINT, 8); IRQ_configArgs (IRQ_EVT_EDMAINT, EdmaIsr, EdmaIsr, 0x00000000, 0x00000000, IRQ_CCMASK_DEFAULT, IRQ_CCMASK_DEFAULT, IRQ_IEMASK_ALL); IRQ_IEMASK_ALL);

89. Chapter 5, Slide 89 Programming the EDMA - CSL Example  CSL programming procedure (cont): (6)Open up an EDMA channel associated with the Timer 1 (remember each EDMA is associated with a specific event): (7)Allocate the EDMA reload parameters: Note: -1 means allocate at any available location. (8)Copy the first reload configuration structure to the EDMA configuration structure: hEdmaPing = EDMA_allocTable (-1); hEdmaPong = EDMA_allocTable (-1); cfgEdma = cfgEdmaPing; hEdma = EDMA_open (EDMA_CHA_TINT1, EDMA_OPEN_RESET);

90. Chapter 5, Slide 90 Programming the EDMA - CSL Example  CSL programming procedure (cont): (9)Configure the link fields of the configuration structure: This can be done at stage 3 but in this way we do not know the numerical value of the reload address. (10)Setup the EDMA channel using the configuration structure: cfgEdmaPing.rld = EDMA_RLD_RMK(0,hEdmaPong); cfgEdmaPong.rld = EDMA_RLD_RMK(0,hEdmaPing); cfgEdma.rld = EDMA_RLD_RMK(0,hEdmaPong); EDMA_config (hEdmaPing, &cfgEdmaPing); EDMA_config (hEdmaPong, &cfgEdmaPong);

91. Chapter 5, Slide 91 Programming the EDMA - CSL Example  CSL programming procedure (cont): (11)Finally initialise all the EDMA registers: EDMA_RSET (ECR, 0xffff);// clear all events EDMA_enableChannel(hEdma); EDMA_RSET (EER, 0x4);// set the timer 1 event enable bit EDMA_RSET (CIPR, 0xffff); EDMA_RSET (CIER, 0x4);// make the timer 1 event generate // an EDMA_INT interrupt  An example CCS project is included in:  \Lab 05\Edma_Inout_Staticcfg

92. Chapter 5, Slide 92 Programming the EDMA - DSP/BIOS GUI (3)DSP/BIOS GUI Interface  With this method the configuration structure is created graphically and the setup code is generated automatically.

93. Chapter 5, Slide 93  Procedure: (1)Create a configuration using the EDMA configuration manager. Programming the EDMA - DSP/BIOS GUI

94. Chapter 5, Slide 94 Programming the EDMA - DSP/BIOS GUI  Procedure: (2)Right click and select “Properties”, see the figure below, and then select “Advanced” and fill all parameters as shown below.

95. Chapter 5, Slide 95 Programming the EDMA - DSP/BIOS GUI  Procedure: (3)If you are using symbolic parameters such as “in_data” you need to declare it in the “CSL Extern Declaration”, see below figure.

96. Chapter 5, Slide 96 Programming the EDMA - DSP/BIOS GUI  Procedure: (4)A file is then generated that contains the configuration code. The file generated for this example is shown on the next slide.

97. Chapter 5, Slide 97 Programming the EDMA - DSP/BIOS GUI /* Do *not* directly modify this file. It was */ /* generated by the Configuration Tool; any */ /* changes risk being overwritten. */ /* INPUT edma_inout_csl.cdb */ /* Include Header File */ #include "edma_inout_cslcfg.h" extern far Uint16 McBSP0_DRR; extern far Uint16 in_data[]; extern far Uint16 BUFF_SZ; /* Config Structures */ EDMA_Config cfgEdmaPing = { 0x28720002, /* Option */ 0x28720002, /* Option */ 0x018C0000, /* Source Address - Numeric */ 0x018C0000, /* Source Address - Numeric */ 0x00000002, /* Transfer Counter */ 0x00000002, /* Transfer Counter */ (Uint32) in_data, /* Destination Address - Symbolic */ (Uint32) in_data, /* Destination Address - Symbolic */ 0x00000004, /* Transfer Index */ 0x00000004, /* Transfer Index */ 0x000001B0 /* Element Count Reload and Link Address */ 0x000001B0 /* Element Count Reload and Link Address */}; /* Handles */ /* * ======== CSL_cfgInit() ======== * ======== CSL_cfgInit() ======== */ */ void CSL_cfgInit() {}

98. Chapter 5, Slide 98 *------------------------------------------------------------------------------ * This program uses the timers to trigger EDMA events. These events in turn * trigger linked EDMA parameter tables to fill a ping-pong buffer structure. * Set a breakpoint on swiProcessFunc(int arg). Then open two memory windows. * Use ping as the address for one memory window and pong for the other. Then * run the application. You'll note that the program bounces between the ping * and pong buffers filling each with a value that comes from the source. The * source in this case is the SDRAM timer control register and it simulates * input data.(Note: This example runs with CACHE enable). \******************************************************************************/ #include #include /*----------------------------------------------------------------------------*/ /* declare DSP/BIOS objects created with the configuration tool */ extern far SWI_Obj SwiMain; extern far LOG_Obj LogMain; extern far SWI_Obj swiProcess; extern far LOG_Obj trace; /* Pick which EDMA transfer completion interrupt we want to use */ #define TCCINTNUM 10 Pre-processor replaces all occurrences of identifier with the define value. By convention, identifiers are all capital Pre-processor replaces line with the named ‘header file’

99. Chapter 5, Slide 99 /* define some constants */ #define BUFF_SZ 256 /* ping-pong buffer sizes in # of ints */ #define FCPU 150000000 /* CPU clock frequency */ #define SRATE 8000 /* data sample rate (simulated w/timer */ #define TPRD (FCPU/(4*SRATE)) /* timer period */ /* Create the buffers. We want to align the buffers to be cache friendly */ /* by aligning them on an L2 cache line boundary. */ #pragma DATA_ALIGN(ping,128); #pragma DATA_ALIGN(pong,128); #pragma DATA_ALIGN(outbuff,128); int ping[BUFF_SZ]; int pong[BUFF_SZ]; int outbuff[BUFF_SZ]; /* These two variables serve as the data sources for this example. */ /* Also want to align these on a cache line boundary since they */ /* sources of EDMA transfers. */ #pragma DATA_ALIGN(ping_data,128); #pragma DATA_ALIGN(pong_data,128); static int ping_data; static int pong_data; /* global variable used to track the ping-pong'ing */ static int pingpong = 0; Assign an initial value to the variable An array of BUFF_SZ integers. Indexed as pong[0], pong[1], …

100. Chapter 5, Slide 100 /* declare some CSL objects */ TIMER_Handle hTimer; /* Handle for the timer device */ EDMA_Handle hEdma; /* Handle for the EDMA channel */ EDMA_Handle hEdmaPing; /* Handle for the ping EDMA reload parameters */ EDMA_Handle hEdmaPong; /* Handle for the pong EDMA reload parameters */ EDMA_Config cfgEdma; /* EDMA configuration structure */ /* Create the EDMA configuration structure for ping transfers */ EDMA_Config cfgEdmaPing = { EDMA_OPT_RMK( EDMA_OPT_RMK( EDMA_OPT_PRI_LOW, // low priority EDMA_OPT_PRI_LOW, // low priority EDMA_OPT_ESIZE_32BIT, // element size = 4 bytes EDMA_OPT_ESIZE_32BIT, // element size = 4 bytes EDMA_OPT_2DS_NO, // one-dimension synchronization for source EDMA_OPT_2DS_NO, // one-dimension synchronization for source EDMA_OPT_SUM_NONE, // do not increment source address EDMA_OPT_SUM_NONE, // do not increment source address EDMA_OPT_2DD_NO, // one-dimension synchronization for destination EDMA_OPT_2DD_NO, // one-dimension synchronization for destination EDMA_OPT_DUM_INC, // increment destination address EDMA_OPT_DUM_INC, // increment destination address EDMA_OPT_TCINT_YES, // upon EDMA completion, generate an EDMA interrupt to PC EDMA_OPT_TCINT_YES, // upon EDMA completion, generate an EDMA interrupt to PC EDMA_OPT_TCC_OF(TCCINTNUM), // set bit 10 in Channel Interrupt Pending Register (CIPR) EDMA_OPT_TCC_OF(TCCINTNUM), // set bit 10 in Channel Interrupt Pending Register (CIPR) EDMA_OPT_LINK_YES, // Upon completion, reload parameter specified by link-address EDMA_OPT_LINK_YES, // Upon completion, reload parameter specified by link-address EDMA_OPT_FS_NO // FS=0  element synchronization EDMA_OPT_FS_NO // FS=0  element synchronization ), ), EDMA_SRC_OF(&ping_data), // source address: address of ‘ping_data’ variable EDMA_SRC_OF(&ping_data), // source address: address of ‘ping_data’ variable EDMA_CNT_OF(BUFF_SZ), // one frame (FRMIDX=0); ‘BUFF_SZ’ elements in frame EDMA_CNT_OF(BUFF_SZ), // one frame (FRMIDX=0); ‘BUFF_SZ’ elements in frame EDMA_DST_OF(ping), // one frame (FRMCNT=0); ‘BUFF_SZ’ EDMA_DST_OF(ping), // one frame (FRMCNT=0); ‘BUFF_SZ’ EDMA_IDX_OF(0x00000004), // difference between adjacent elements = 4 bytes (no gaps) EDMA_IDX_OF(0x00000004), // difference between adjacent elements = 4 bytes (no gaps) EDMA_RLD_OF(0x00000000) // to be defined later EDMA_RLD_OF(0x00000000) // to be defined later};Type Variable name Variables defined externally to a function body (including ‘main’) have a global scope.

101. Chapter 5, Slide 101 /* Create the EDMA configuration structure for pong transfers */ EDMA_Config cfgEdmaPong = { EDMA_OPT_RMK( EDMA_OPT_RMK( EDMA_OPT_PRI_LOW, EDMA_OPT_PRI_LOW, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_NO, EDMA_OPT_2DS_NO, EDMA_OPT_SUM_NONE, EDMA_OPT_SUM_NONE, EDMA_OPT_2DD_NO, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_INC, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(TCCINTNUM), EDMA_OPT_TCC_OF(TCCINTNUM), EDMA_OPT_LINK_YES, EDMA_OPT_LINK_YES, EDMA_OPT_FS_NO EDMA_OPT_FS_NO ), ), EDMA_SRC_OF(&pong_data), // source address = address of ‘pong_data’ variable EDMA_SRC_OF(&pong_data), // source address = address of ‘pong_data’ variable EDMA_CNT_OF(BUFF_SZ), EDMA_CNT_OF(BUFF_SZ), EDMA_DST_OF(pong), // destination address = ‘pong’ buffer EDMA_DST_OF(pong), // destination address = ‘pong’ buffer EDMA_IDX_OF(0x00000004), EDMA_IDX_OF(0x00000004), EDMA_RLD_OF(0x00000000) EDMA_RLD_OF(0x00000000)};

102. Chapter 5, Slide 102 /*----------------------------------------------------------------------------*/ void main(){ /* initialize the CSL library */ /* initialize the CSL library */ CSL_init(); CSL_init(); /* initialize the input source data */ /* initialize the input source data */ ping_data=0x00000000; ping_data=0x00000000; pong_data=0x80000000; pong_data=0x80000000; /* Since these variables are the source of an EDMA transfer, we */ /* Since these variables are the source of an EDMA transfer, we */ /* need to flush them out of the cache since we just wrote to them. */ /* need to flush them out of the cache since we just wrote to them. */ CACHE_flush(CACHE_L2,&ping_data,1); CACHE_flush(CACHE_L2,&ping_data,1); CACHE_flush(CACHE_L2,&pong_data,1); CACHE_flush(CACHE_L2,&pong_data,1); /* Let's disable/clear related interrupts just in case they are pending */ /* Let's disable/clear related interrupts just in case they are pending */ /* fram a previous run of the program. */ /* fram a previous run of the program. */ IRQ_reset(IRQ_EVT_EDMAINT); // reset any pending EDMA interrupt at CPU IRQ_reset(IRQ_EVT_EDMAINT); // reset any pending EDMA interrupt at CPU EDMA_intDisable(TCCINTNUM); // prevent generation EDMA interrupt ( CIER[10] = 0) EDMA_intDisable(TCCINTNUM); // prevent generation EDMA interrupt ( CIER[10] = 0) EDMA_intClear(TCCINTNUM); // clear pending interrupt at EDMA ( CIPR[10] = 0) EDMA_intClear(TCCINTNUM); // clear pending interrupt at EDMA ( CIPR[10] = 0) /* Although not required, let's clear all of the EDMA parameter RAM. */ /* Although not required, let's clear all of the EDMA parameter RAM. */ /* This makes it easier to view the RAM and see the changes as we */ /* This makes it easier to view the RAM and see the changes as we */ /* configure it. */ /* configure it. */ EDMA_clearPram(0x00000000); EDMA_clearPram(0x00000000); /* Let's open up a timer device, we'll use this to simulate input events */ /* Let's open up a timer device, we'll use this to simulate input events */ /* at a gien sample rate. */ /* at a gien sample rate. */ hTimer = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET); hTimer = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET);

103. Chapter 5, Slide 103 /* Lets open up the EDMA channel associated with timer #1. */ /* Lets open up the EDMA channel associated with timer #1. */ hEdma = EDMA_open(EDMA_CHA_TINT1, EDMA_OPEN_RESET); hEdma = EDMA_open(EDMA_CHA_TINT1, EDMA_OPEN_RESET); /* We also need two EDMA reload parameter sets so let's allocate them */ /* We also need two EDMA reload parameter sets so let's allocate them */ /* here. Notice the -1, this means allocate any availale tale. */ /* here. Notice the -1, this means allocate any availale tale. */ hEdmaPing = EDMA_allocTable(-1); hEdmaPing = EDMA_allocTable(-1); hEdmaPong = EDMA_allocTable(-1); hEdmaPong = EDMA_allocTable(-1); /* Let's copy the ping reload configuration structure to an */ /* Let's copy the ping reload configuration structure to an */ /* intermediate configuration structure. */ /* intermediate configuration structure. */ cfgEdma = cfgEdmaPing; cfgEdma = cfgEdmaPing; /* Let's initialize the link fields of the configuration structures */ /* Let's initialize the link fields of the configuration structures */ cfgEdmaPing.rld = EDMA_RLD_RMK(0,hEdmaPong); // Ping parameters reloads Pong parameters cfgEdmaPing.rld = EDMA_RLD_RMK(0,hEdmaPong); // Ping parameters reloads Pong parameters cfgEdmaPong.rld = EDMA_RLD_RMK(0,hEdmaPing); // Pong parameters reloads Ping parameters cfgEdmaPong.rld = EDMA_RLD_RMK(0,hEdmaPing); // Pong parameters reloads Ping parameters cfgEdma.rld = EDMA_RLD_RMK(0,hEdmaPong); cfgEdma.rld = EDMA_RLD_RMK(0,hEdmaPong); /* Now let's program up the EDMA channel with the configuration structure */ /* Now let's program up the EDMA channel with the configuration structure */ EDMA_config(hEdma, &cfgEdma); EDMA_config(hEdma, &cfgEdma); /* Let's also configure the reload parameter tables in the EDMA PRAM */ /* Let's also configure the reload parameter tables in the EDMA PRAM */ /* with the values in the configuration structures. */ /* with the values in the configuration structures. */ EDMA_config(hEdmaPing, &cfgEdmaPing); EDMA_config(hEdmaPing, &cfgEdmaPing); EDMA_config(hEdmaPong, &cfgEdmaPong); EDMA_config(hEdmaPong, &cfgEdmaPong);

104. Chapter 5, Slide 104 /* Configure up the timer. */ /* Configure up the timer. */ TIMER_configArgs(hTimer, TIMER_configArgs(hTimer, TIMER_CTL_OF(0x00000200), TIMER_CTL_OF(0x00000200), TIMER_PRD_OF(TPRD), TIMER_PRD_OF(TPRD), TIMER_CNT_OF(0) TIMER_CNT_OF(0) ); ); /* Enable the related interrupts */ /* Enable the related interrupts */ IRQ_enable(IRQ_EVT_EDMAINT); // enable EDMA interrupt at CPU IRQ_enable(IRQ_EVT_EDMAINT); // enable EDMA interrupt at CPU EDMA_intEnable(TCCINTNUM); // enable generating interrupt at EDMA (CEIR[10] = 1) EDMA_intEnable(TCCINTNUM); // enable generating interrupt at EDMA (CEIR[10] = 1) /* Enable the EDMA channel */ /* Enable the EDMA channel */ EDMA_enableChannel(hEdma); // enable EDMA channel 2 (associated with Timer 1) EER[2] =1 EDMA_enableChannel(hEdma); // enable EDMA channel 2 (associated with Timer 1) EER[2] =1 /* Finally, enable the timer which will drive everything. */ /* Finally, enable the timer which will drive everything. */ TIMER_start(hTimer); TIMER_start(hTimer);}

105. Chapter 5, Slide 105 void swiProcessFunc (int arg){ int *inbuff; int *inbuff; int x; int x; if (pingpong){ if (pingpong){ /* If pingpong is 0, then we own the ping input buffer */ /* If pingpong is 0, then we own the ping input buffer */ inbuff = ping; inbuff = ping; LOG_printf(&trace,"Ping"); LOG_printf(&trace,"Ping"); }else{ }else{ /* If pingpong is 1, then we own the pong input buffer */ /* If pingpong is 1, then we own the pong input buffer */ inbuff = pong; inbuff = pong; LOG_printf(&trace,"Pong"); LOG_printf(&trace,"Pong"); } /* Now let's process the input buffer, for simplicity, we'll */ /* Now let's process the input buffer, for simplicity, we'll */ /* just copy it to the output buffer. */ /* just copy it to the output buffer. */ for (x=0; x<BUFF_SZ; x++) { for (x=0; x<BUFF_SZ; x++) { outbuff[x] = inbuff[x]; outbuff[x] = inbuff[x]; } /* If this example is enhanced to actually do something with the */ /* If this example is enhanced to actually do something with the */ /* output buffer such as DMA it somewhere, you will want to flush */ /* output buffer such as DMA it somewhere, you will want to flush */ /* it out of the cache first. */ /* it out of the cache first. */ CACHE_flush(CACHE_L2,outbuff,BUFF_SZ); CACHE_flush(CACHE_L2,outbuff,BUFF_SZ); /* Since we're done processing the input buffer, clean it from cache, */ /* Since we're done processing the input buffer, clean it from cache, */ /* this invalidates it from cache to ensure we read a fresh version */ /* this invalidates it from cache to ensure we read a fresh version */ /* the next time. */ /* the next time. */ CACHE_clean(CACHE_L2,inbuff,BUFF_SZ); CACHE_clean(CACHE_L2,inbuff,BUFF_SZ);}

106. Chapter 5, Slide 106 void hwiEdmaIsr ( int arg){ /* Clear the pending interrupt from the EDMA interrupt pending register */ /* Clear the pending interrupt from the EDMA interrupt pending register */ EDMA_intClear(TCCINTNUM); // CIPR[10] = 0 EDMA_intClear(TCCINTNUM); // CIPR[10] = 0 /* Perform ping-pong */ pingpong = (pingpong + 1) & 1; pingpong = (pingpong + 1) & 1; /* Based on if we ping'ed or pong'ed, we need to set the EDMA channel */ /* Based on if we ping'ed or pong'ed, we need to set the EDMA channel */ if (pingpong){ /* Currently doing pong so setup next frame for ping */ /* Currently doing pong so setup next frame for ping */ /* Modify the input data source, this just simulates */ /* Modify the input data source, this just simulates */ /* the input data changing. */ /* the input data changing. */ ping_data++; ping_data++; /* Rememer to flush this variable out of the cache */ /* Rememer to flush this variable out of the cache */ /* since it's the source of an EDMA transfer */ /* since it's the source of an EDMA transfer */ CACHE_flush(CACHE_L2,&ping_data,1); CACHE_flush(CACHE_L2,&ping_data,1);}else{ /* Currently doing ping so setup next frame for pong */ /* Currently doing ping so setup next frame for pong */ /* Modify the output data source, this just simulates */ /* Modify the output data source, this just simulates */ /* the input data changing. */ /* the input data changing. */ pong_data++; pong_data++; /* Rememer to flush this variable out of the cache */ /* Rememer to flush this variable out of the cache */ /* since it's the source of an EDMA transfer */ /* since it's the source of an EDMA transfer */ CACHE_flush(CACHE_L2,&pong_data,1); CACHE_flush(CACHE_L2,&pong_data,1);} /* Notify the app that we just ping-pong'ed */ /* Notify the app that we just ping-pong'ed */ SWI_post(&swiProcess); SWI_post(&swiProcess);}

107. Chapter 5 Enhanced Direct Memory Access (EDMA) - End -