1. Feifarek 1 MAPLD 2005/A220 Jonathan F. Feifarek jonathan.feifarek@lmco.com Timothy C. Gallagher timothy.c.gallagher@lmco.com Lockheed Martin Space Systems Co. FPGA Based Processor for Hubble Space Telescope Autonomous Docking – A Case Study Courtesy NASA GSFC

2. Feifarek 2 MAPLD 2005/A220 Background: Need for Hubble Repair ● 4 / 1990: Hubble Space Telescope (HST) launch ● 12/1993: SM* 1- Corrective COSTAR, WFP Camera2 ● 2 / 1997: SM 2 – Add NICMOS, STIS, Thermal Blankets ● 10/1997: Hubble Operations Extended from 2005 to 2010 ● 12/1997: SM3A Replace 6 Gyros, 3 Fine Guidance Sensors ● 3 / 2002: SM3B Replace Solar Panels, NICMOS Coolant ● 3 / 2003: SM 4 Cancelled Following Columbia Disaster ● 6 / 2004: Hubble HRV Request For Proposal Issued ● 8 / 2004: Lockheed Martin awarded HST Robotic Vehicle (HRV) ● 12/2007: Target HRV Launch Date * SM = Service Mission

3. Feifarek 3 MAPLD 2005/A220 HRV Mission : Autonomous Docking Mission Phase System Approach Requirement Pursuit Orbit phasing with HST HRV checkout Range from HST for initial sensor acquisition Proximity Ops HST approach with safe-hold points Acquire sensor data on HST orientation and rotation rate Approach Capture/Berth Rate matching with HST Maneuver to HST capture point Capture HST: – Robotic Arm Captures HST Grapple Fixture – Berth to HST aft interface

4. Feifarek 4 MAPLD 2005/A220 Vision Processing Algorithm Selection Criteria ● Implementation Concerns - Computational Intensive – Field Programmable Gate Array (FPGA) – Flight Computer, DSP Processor – Combination ● Implementation Approach – All: Conventional Programming Languages – FPGA High-Order Languages (HOLs) – FPGA Register Transfer Logic (RTL) in VHDL or Verilog ● Error-prone ● Time consuming (calendar time plus engineering cost) ● Difficult to achieve bit accurate & cycle accurate operations using hand-coded conversions

5. Feifarek 5 MAPLD 2005/A220 Vision Processing Algorithm Selection Results ● FPGA Reconfigurable Architecture Chosen – Searched Internet and Conference Proceedings for comparisons between Processors and FPGA Reconfigurable Computer (RCC) ● Space Based RCC technology leaders such as Los Alamos National Labs 1 and NASA 2 noted FPGA system performed between 10-1000x faster then processors ● Many other references on FPGA based accelerated image processing from University studies 3,4 ● Microprocessor Embedded in FPGA – Allows rapid evaluation of architecture performance – Can host large amounts of existing code such as decision logic and complex sequential math – For certain algorithms Floating Point is more efficiently implemented in processor code then in gates

6. Feifarek 6 MAPLD 2005/A220 Vision Processing Algorithm Selection Results ● FPGA Implementation: Combination of HOL, RTL – HOL (Celoxica Handel-C) for fast and efficient implementation – Provided fast development cycle needed for mission ● Quickly ported math libraries & existing C++ code ● Performance matched RTL speed, area ; slower than hand- code ● Highest speed increase from hand floorplanning – RTL for IO Wrapper, IO reuse, and custom-optimized code – Combined the benefits of all worlds – Microprocessor Implementation ● Incorporated Xilinx MicroBlaze ™ Core in FPGA ● Xilinx tools: Platform Studio© SDK / EDK suite ● Used gnu© C compiler / “gdb” debugger

7. Feifarek 7 MAPLD 2005/A220 Vision Processing FPGA Development Flow C Algorithm Acceleration C to RTL Generate human-readable VHDL and Verilog for 3rd party synthesis C to FPGA Direct implementation to device optimized programmable logic FPGA Implementation Provide rapid iteration of partitioning decisions throughout flow Verification Drive continuous system verification from concept to hardware Used with permission of Celoxica, Inc.

8. Feifarek 8 MAPLD 2005/A220 Vision Processing Card (VPC) Block Diagram

9. Feifarek 9 MAPLD 2005/A220 Vision Processor Card Architecture SRAM Flash Power Switch PCI-PCI Bridge / Config Internal PCI COP A Xilinx V2 Port A SRAM SDRAM COP B Xilinx V2 Port B COP C Xilinx V2 Port C COP D Xilinx V2 Port D Common Interconnect Bus J8 PCI Connectors SerDes SDRAM SRAM SDRAM SerDes SDRAM SRAM SDRAM SerDes SDRAM SRAM SDRAM SerDes SDRAM

10. Feifarek 10 MAPLD 2005/A220 VPC Engineering Development Board Used with permission of SEAKR Engineering, Inc.

11. Feifarek 11 MAPLD 2005/A220 VPC SEU Approach ● Main SEU Mitigation: Dual Voting at FPGA output – Detects SEE's but cannot correct for them – Tight power restrictions (thermal reasons) restrict triple voting – Vision Processing Algorithm tolerant of drop-outs ● Multiple camera views / algorithms into Kahlman filter ● HRV mission uses very low rate docking (1 inch / sec) ● SEU Correction at FPGA-to-Memory Interfaces ● Microprocessor returned to Reset State after each image ● Algorithm memory only 1 image deep; flushes SEU effects ● Voting, Configuration Scrubbing Performed in Rad Hard Part ● Analysis Shows Low SEE Rate (1 effective upset / 10 hours)

12. Feifarek 12 MAPLD 2005/A220 VPC Sizing Results for NFIR Algorithm Single LK Tracker Quad LK Trackers

13. Feifarek 13 MAPLD 2005/A220 VPC Performance Results for NFIR Algorithm

14. Feifarek 14 MAPLD 2005/A220 VPC Performance Results for NFIR Algorithm (cont.)

15. Feifarek 15 MAPLD 2005/A220 Summary: Lessons Learned ● Using OpenGL algorithm for development hampered design ● Parallel PC board and FPGA designs helped meet schedule ● Using FPGA’s was key to meeting speed requirements ● Use of microprocessor core reduced development time ● Early allocation of algorithm to hardware/software paid off ● Use of HOLs made implementing complex tasks possible ● Engage expert tool user on team (MicroBlaze, Handel-C) ● Having reference software / test data eased verification ● Benefited from small, enthusiastic, tight knit team ● Worked around MicroBlaze libraries bugs with custom logic

16. Feifarek 16 MAPLD 2005/A220 References ● (1) “A Space Based Reconfigurable Radio”, Michael Caffrey, Los Alamos National Laboratory, MAPLD September 2002 ● (2) “Developing Reconfigurable Computing Systems for Space Flight Applications”, Thomas P. Flatley, NASA Goddard Space Flight Center Greenbelt, Maryland 20771 ● (3) "Implementing Image Applications on FPGAs," B. Draper, R. Beveridge, W. Böhm, C. Ross and M. Chawathe. International Conference on Pattern Recognition, Quebec City, Aug. 11-15, 2002. ● (4) “Performance of Reconfigurable Architectures for Image-Processing Applications”, Domingo Benitez, University of Las Palmas G.C., Journal of Systems Architecture: the EUROMICRO Journal, September 2003