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MURI Total Ionizing Dose Effects in Bulk Technologies and Devices Hugh Barnaby, Jie Chen, Ivan Sanchez Department of Electrical Engineering Ira A. Fulton.

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Presentation on theme: "MURI Total Ionizing Dose Effects in Bulk Technologies and Devices Hugh Barnaby, Jie Chen, Ivan Sanchez Department of Electrical Engineering Ira A. Fulton."— Presentation transcript:

1 MURI Total Ionizing Dose Effects in Bulk Technologies and Devices Hugh Barnaby, Jie Chen, Ivan Sanchez Department of Electrical Engineering Ira A. Fulton School of Engineering Arizona State University

2 Outline  Overview of ASU tasks  Total ionizing dose defect models  Device TID response oDrain-to-source leakage oInter-device leakage  Analysis of defect buildup across oxide structure and between technologies  Other work

3 ASU task Characterize and model TID effects in modern devices, primarily CMOS transistors Technologies: deep sub-micron bulk CMOS, and silicon on insulator, general isolations

4 ASU task Characterize and model TID effects in modern devices, primarily CMOS transistors Technologies: deep sub-micron bulk CMOS, and silicon on insulator, general isolations In Year 1, we have primarily focused on deep-sub-micron bulk CMOS and general isolation technologies.

5 Primary TID Threat TID defect build-up in the “thick” shallow trench isolation (STI) Defects N ot - oxide trapped charge (E’ ) N it – interface traps (Pb) Both N it and N ot are related to holes generated and/or hydrogen present in oxide N ot, N it  t ox first order assumption

6 After Fleetwood et al. TNS 1994 Model Parameters Model for N ot buildup D - total dose [rad] k g - 8.1 x 10 12 [ehp/radcm 3 ] f y - field dependent hole yield [hole/ehp] f ot - trapping efficiency [trapped hole/hole] t ox - oxide thickness [cm]

7 Hole trapping processes + + - surviving hole (p) - hole trap (N T ) - trapped hole (N ot ) fpfp - hole flux area = 

8 After Rashkeev et al. TNS 2002 Simple analytical model (N ot ) (steady state) (f p > 0 for all x) f ot D (No saturation or annealing and traps at interface)

9 After Rashkeev et al. TNS 2002 Model Parameters Model for N it buildup D - total dose [rad] k g - 8.1 x 10 12 [ehp/radcm 3 ] f y - field dependent hole yield [hole/ehp] f DH - hole, D’H reaction efficiency [H + /hole] f it - H +, SiH de-passivation efficiency [interface trap/H + ] t ox - oxide thickness [cm]

10 De-passivation processes - protons - Si-H (N SiH ) - dangling bond (N it ) area =  it H H+ fHfH - proton flux - hydrogen defect (D’H)

11 After Rashkeev et al. TNS 2002 De-passivation processes f it D (f H > 0 for all x) (steady state) (No saturation or annealing and traps at interface)

12 Leakage paths 1 2 3 1 2 3 NMOS Drain-to-Source NMOS D/S to NMOS S/D NMOS D/S to NWELL Defect build-up in STI creates leakage paths in CMOS ICs. CMOS inverters 2 and 3 are inter-device leakage

13 NMOS drain-to-source leakage Increasing total dose

14 Parasitic leakage model Parasitic “edge” device modeled as MOSFET operating in parallel with “as drawn” FET. “Effective” parameters for “edge” device are extracted from data.

15 Extracting electrical characteristics I D“edge” (post) ≈ I Dtotal (post) – I Dtotal (pre) I D“edge” (post) I Dtotal (post) I Dtotal (pre) Two assumptions: 1.I Dtotal (pre) ≈ I D“as-drawn” (pre) 2.I D“as-drawn” (post) ≈ I D“as-drawn” (pre)

16 “Edge” Capacitor Prior to radiation exposure, the MOS capacitor of the “edge” device has small dimensions, W and t ox STI W eff  t ox-eff + + + +

17 + + “Edge” Capacitor Upon radiation exposure, the “edge capacitor is degraded and the dimensions enlarged. STI W eff  t ox-eff + + + + STI W eff  t ox-eff + + + + + + + Increasing total dose

18 + + “Edge” Capacitor Increased defect buildup in the STI sidewall leads to further increases in W and t ox, until inherent limitations are met. STI W eff  t ox-eff + + + + STI W eff  t ox-eff + + + + + + + Increasing total dose + + STI W eff  t ox-eff + + + + + + + + + + + + + + + + + + + +

19 2D simulations N ot = 2×10 12 cm -2 N ot = 5×10 12 cm -2 N ot = 7×10 12 cm -2 Simulations show how increased N ot along sidewall increases the width of the channel and the capacitor thickness W eff

20 New Test Structure Devices designed by Faccio and fabricated at STMicro enable measurements on sidewall capacitor. 1.3 um 90 um overlap Pre-rad

21 Parameter extraction 1.W eff increases with TID (increased strong -inv current) 2.N ot and N it increase with TID (shift in threshold voltage) 3.N it and t ox increase with TID (reduced subthreshold slope) 4.N ot increase with TID (shifts in midgap voltages)

22 Simultaneous equations 1. 2. 3. 4. Solving simultaneously enables extraction of parameters and defect levels at each TID value

23 Parameters and sidewall defects V TH-eff (V)t OX-eff (nm)W eff (nm) preN/A 100 krad0.19417.943.7 500 krad0.18017.999.9 1 Mrad0.16920.0128.1 Parameters Defects  N ot (cm -2 )  N Iit (cm -2 ) 100 krad – 500 krad8.5×10 10 6.4×10 10 100 krad – 1 Mrad1.0×10 11 1.2×10 11

24 Inter-device leakage n+ D/S to n-welln+ D/S to n+ D/S Charge build-up in STI base

25 Field oxide transistors 130 nm bulk CMOS noise floor p-well STI n+ n-well - n+ D/S n-well Metal 1 + + + +

26 Field oxide capacitors 1500 Single Cell FOXCAPs in parallel gate area of individual cell ~ 7.4 μm x 11.4 μm Single cell 130 nm data

27 Defect build-up in STI base Defect build-up is: 1.Greater for higher oxide fields (consistent w/ f y ) 2.Linear with dose (no saturation … yet)

28 Comparison to other isolation technologies (N ot ) Devicet ox (nm)TypeArea (cm 2 )∆V ot (V)K (x 10 3 ) FOXCAP320p0.00236.563.5 RF25600p0.00124.17511.6 XFCB600p0.00706.1217 E4403/W21*1080n0.0307.733.01 SIMOX370n0.0222.216.07 *data taken after 20 krad(SiO2) exposures **radiation bias is 0V for all devices

29 Sidewall vs. Base Comparison (N ot ) Indicates saturation in defect buildup 500 k1000k STI sidewall.0147.0068 STI base.0109.0094

30 Sidewall vs. Base Comparison (N it )

31 Other Work Separation of switch state defects in thick isolation oxides using frequency dependent charge pumping Packaging issues

32 Gate sweep data N ss Increased current is caused by switching state buildup (Nss) which is composed of both interface and border traps

33 Separation of Switching States Indicates border traps

34 Packaging Issues Recent testing showed 3x increase in N it in GLPNP devices packaged with sealed gold plated kovar lids than packages with taped-on lids. ΔNot (cm -2 )ΔNit (cm -2 ) Unsealed~1.7x10 11 ~0.8x10 11 Sealed~1.4x10 11 ~2.5x10 11

35 It’s a hydrogen problem As sealed lid is removed, H 2 moves quickly out of the package and a concentration gradient is established for the remaining H 2 in the oxide to diffuse out, thus reducing N it generation.

36 Another time dependent process Results shows time dependence of N it build-up related hydrogen out diffusion … we are working on the rate equations for this Not (cm -2 )Nit (cm -2 ) Sealed~1.7x10 11 ~2.4x10 11 Unsealed 1hr ~1.6x10 11 ~1.5x10 11 Unsealed 13hrs ~1.6x10 11 ~6.9x10 10 Unsealed 7days ~1.6x10 11 ~6.1x10 10


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