1. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 1 GLAST Large Area Telescope: Tracker Subsystem WBS 4.1.4 2A: Electronics Design and Status Robert Johnson Santa Cruz Institute for Particle Physics University of California at Santa Cruz Tracker Subsystem Manager johnson@scipp.ucsc.edu Gamma-ray Large Area Space Telescope

2. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 2 TKR Electronics Requirements Details of the requirements are in released LAT documents: –LAT-SS-17Level-3 Performance requirements –LAT-SS-134Level-4 Mechanical & Thermal requirements –LAT-SS-152Level-4 Electronics requirements The major challenges are –Low power: <168 W of conditioned power Less than 0.29 W per MCM or 190  W/channel The flight design achieves 0.25 W per MCM! –Low noise occupancy: (noise trigger rate <500 Hz) The trigger requires occupancy less than 5/100,000 ch/trigger Readout and onboard processing requires <1/10,000 ch/trigger The beam-test/balloon flight tracker achieved much better… –Compact packaging: bring signals around the tray corner –Manufacturing and QC: 884,736 channels, >98% functional –Reliability: design, redundancy, testing

3. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 3 Some Detailed Requirements Internal charge injection for calibration and test, with pulse- height control and arbitrary selection of channels. Threshold uniformity: <15 mV rms across 64 channels. Threshold control per GTFE chip by an internal DAC. Dead time & Readout speed: less than 10% at 10 kHz cosmic rate. TOT: measure up to 4 MIPs. Non-destructive readback of configuration registers. Error checking: event alignment; command & data parity. Layer-OR jitter 0.5 MIP. Reliability: –Redundant readout paths. –Redundant power paths. –Protection against power shorts. Radiation hardness: 4 kRad TID; >37 MeV/mg/cm 2 SEL thresh Passive cooling; temperature monitoring.

4. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 4 Tracker Readout Architecture Emphasis on compactness, minimum of wiring, and redundancy: Serial, LVDS readout and control lines on flat flex-circuit cables. Either of the two communications cables can fail without affecting the other. Two readout and control paths for every 64-channel front-end chip. Any single chip can fail without preventing the readout of any other. Trigger output = OR of all 1536 channels in a layer. Upon trigger (6-fold coincidence) data are latched into a 4- event-deep buffer in each front-end chip. Read command moves data into 1 of 2 GTRC buffers. Token moves data from GTRCs to TEM.

5. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 5 Tracker Readout Architecture Block diagram of the ends of two readout layers and their connections to the TEM –Clock, Command, Trigger, and Reset are bussed to the GTRC chips –Token and Data daisy-chain up and down the 9 layers –Each layers sends its Layer-OR directly to the TEM –The TEM communicates only with the GTRC chips, always by serial LVDS. –The GTRC communicates with 24 GTFE chips on the MCM.

6. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 6 MCM Readout Module Configuration 8-layer polyimide PWB Top edge thickened and machined to a 0.64 mm radius 1-layer flex circuit (“pitch adapter”) bonded over the radius Fully encapsulated wire bonds Conformal coating 2 Omnetics nano connectors Steel mounting screws + adhesive

7. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 7 MCM PWB Layout Concept Low-noise environment for the amplifier chips 8 layers are used for good analog/digital separation plus low-impedance ground and power planes. Analog and digital traces are well separated and never wrap around each other. Power planes and split analog/digital GND planes Complete planes are also used for the SSD bias and AVDD2  low impedance path to the decoupling caps for the SSD signal return. Stackup and arrangement of conductors in the PWB 1.Digital traces; SMT parts; ASICs 2.Digital busses 3.Split digital/analog power 4.Split digital/analog ground 5.Analog ground 6.Analog traces from ASICs to the SMT parts 7.AVDD2 (analog 1.5V) 8.Detector bias

8. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 8 Pitch Adapter 1-layer Kapton flex circuit Ni + Au plating for wire bonding Precision tooling holes (not shown) Circuit & traces are trimmed to length after bonding to the PWB (see Presentation 6E) SSD Side (228  m pitch) ASIC Side “ground” Bias HV

9. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 9 F.E. Readout Chip (GTFE) Schematics-based design, using standard cells for logic. Standard-cell I/O pad ESD protection. Manual layout of the analog channel, I/O cells, memory, global routing. Automated place-and-route of the logic blocks. Design verification: Spice and gate level simulations; DRC; LVS; simulation of the final extracted netlist in Nanosim. 64 amplifier-discriminator channels. 4-deep event memory (addressed by TEM) Custom layout 2 custom DACs Trigger and Data mask registers Standard-cell auto route Control logic, command decoders Standard-cell auto route Cap Calibration mask and capacitors I/O pads and protection structures

10. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 10 GTFE Block Diagram 64 amplifier-discriminator channels 7-bit threshold DAC Calibration mask register 7-bit calibration DAC Trigger mask register and trigger layer-OR Data mask register 4-deep event buffer Pair of redundant command decoders Pair of redundant trigger receivers Leftward readout register Rightward readout register LVDS I/O cells

11. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 11 Readout Controller Chip (GTRC) All digital Tanner standard-cells, except for LVDS I/O cells. SEU hardened configuration register. RAM (64 hits, 2 buffers) Design in VHDL; synthesis, auto place and route. Verification: VHDL sim; DRC; LVS; Nanosim of extracted netlist.

12. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 12 Readout Cables Standard-technology 4-layer Kapton flex circuits 8 unique layouts (with identical schematics) Require 36-inch panels for manufacture Power traces/planes, LVDS signals, and thermistor loops Procurement specification: LAT-PS-01132 Thru-holes for Micro-D connector EM cable manufactured by Parlex Thermistor Location Solder pads for nano- connector 4 Termination resistors

13. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 13 Electronics Cooling Low IC power density (20 MHz clock): –GTFE chip: 7.8 mW for 0.33 cm 2  0.024 W/ cm 2 –GTRC chip: 32 mW for 0.12 cm 2  0.26 W/cm 2 Total MCM power of 0.25 W is spread by the PWB over about 100 cm 2 along the tray edge  2.4 mW/cm 2. The 8-layer board has several full copper planes to spread the heat. A 5-mil 3M high-thermal-conductivity transfer adhesive lies between the MCM and carbon-carbon tray closeout. The carbon-carbon carries the heat to the sidewall through a 20 cm long boss and 10 fasteners into the tower sidewalls. The 1.5 mm thick K13D/YS90 sidewalls carry the heat to the bottom of the tower. Copper straps carry heat from the sidewalls into the Grid. SSDs stay below 30°C operational. The ICs will be only a few degrees warmer.

14. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 14 Example EM Tray Connector Saver Handle for assembly fixtures Thermal Boss Bias Circuit MCM Encapsulated ASICs The bias circuit is a 2-layer Kapton flex circuit. Top layer: 16 wire-bond pads (Ni-Au plating) + HV bias traces and bulls-eye pads for conductive adhesive. Bottom layer: hatched “ground” plane.

15. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 15 Grounding & Shielding LAT RF SHIELD BOX ENCLOSURE LAT Overview

16. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 16 Tracker Grounding & Shielding Aluminum covering on all 6 sides Conductive tape on joints Cu thermal straps provide the conduction path to the Grid 8 cables ground the 19 trays & electronics to the TEM Zillion screws tie the sidewalls into the trays

17. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 17 Tray Grounding & Shielding The bias circuit includes a hatched “gnd” plane (actually 1.5 V) that corresponds to the amplifier voltage reference. It separates the SSDs from the structure and couples closely to the 120 V bias on the backs of the SSDs. The MCMs have separate analog and digital ground planes with separate returns to the TEM, but they are coupled together on each MCM by an SMT jumper. 3 long screws tie each MCM ground into the aluminum core

18. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 18 Tray Grounding & Shielding The 1.5 V analog supply (AVDDA) feeds the source of the input FET and is thus the small-signal reference of the detector system. It couples to the SSD bias via HV capacitors on the MCM and through the capacitance of the bias circuit. This provides the small-signal current return path of the detector system. All voltage supplies occupy planes on the MCM and are coupled to ground via numerous ceramic and tantalum capacitors on the MCM.

19. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 19 EMI/EMC The Tracker will be well shielded: –All transmitted signals are LVDS and digital (very low radiation and excellent noise rejection). In addition, power and ground reference planes are always directly under or over the signal pairs. –Aluminum foil (over carbon-fiber) covering all 6 tower module sides. –Conductive tape around the corners to connect the sides. SSD strips are the sensitive nodes, but –They are well shielded from any radiation. –Only a very local reference is needed (the amplifiers are millimeters from the strips with well identified, short current return paths). –The local grounding around the SSDs is critical for noise performance. EM emissions will be tested from the qual unit, but we expect it to satisfy requirements easily (433-RQMT-0005). Preliminary measurements on the BTEM showed no measurable emission, even with the aluminum shielding walls removed.

20. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 20 EMI/EMC Primary document 433-RQMT-005 Radiated Emissions (RE101, RE102) –20% of total emissions are allocated to subsystems outside LAT RF shield ACD, Tracker, Heaters –60% of total emissions are allocated to subsystems inside LAT shield Radiated Susceptibility (RS101,RS103) –All subsystems must meet Section 5.3 of 433-RQMT-005 Conducted Emissions (CE101, CECM) –Only the T&DF subsystem is affected and must meet requirements Conducted Susceptibility (CS101, CS116) –Only the T&DF subsystem is affected and must meet requirements

21. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 21 BTEM EMI Test Spectrum Analyzer BTEM with Shield removed Electric field antenna Magnetic field antenna No measurable EMI detected, clock on or off, even with the tower shield removed.

22. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 22 Prototype Electronics Performance See LAT-TD-1090. Reviewed at TKR ASIC review Dec 6, 2002. Analog tests with “mini-MCM” plus full-length ladder (384 channels) –Gain and noise from charge-inject/threshold scans –Noise measurements from trigger-rate threshold scans –Noise occupancy from random triggers –Noise injection from digital readout –Gain versus number of channels pulsed –Pulse shapes and Time-Over-Threshold Functional tests with full MCMs (no SSDs attached) –All digital functionality –Power consumption –Voltage and timing margins –DAC calibrations –Thermal cycling Radiation Testing See Presentation 3B for more recent results on Engineering-Model trays.

23. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 23 Threshold Dispersion The RMS dispersion, with or without SSDs connected, is below 8 mV, better than the requirements. The dispersion is independent of the number of channels simultaneously pulsed. No load on inputs.

24. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 24 Trigger Rates 1.3 fC=1/4 MIP Long TOT pulses; look like cosmic rays Three ladders connected to mini-MCMs were tested. These are the results for Ladder-0

25. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 25 Noise Occupancy Ladder 0, 80V bias, 1.3 fC threshold, 1.5 million triggers. Our first direct measurement of noise occupancy with the new electronics system.

26. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 26 MCM Power Consumption AVDDA 1.5 V AVDDB 2.5 V DVDD 2.5 V address 5 DVDD 2.5 V address 0 No Clock77.4 mW39.3 mW82.8 mW 20 MHz77.4 mW39.3 mW134.3 mW138.5 mW MCM Power (W)Allocation MCM Address > 00.251 MCM Address = 00.255 Tower9.0510.5 W 16 Towers145168 W

27. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 27 ASIC Review Action Items Test full trays Test noise 1 channel at a time Noise occupancy vs threshold (deviation from gaussian noise) Noise versus threshold Efficiency vs threshold Test FIB ICs with ladder Test at high rates Wafer probing system (see Presentation 5D) Approved parts (see Presentation 5B) Procurements (see Presentation 5A)

28. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 28 Actions from ASIC Review Measurements with complete trays (EM mini-tower) –Four trays, with a total of 6 SSD planes have been tested. –Initially there were noise problems that were solved by fixing the grounding Grounding of the Al core via long screws in the MCM (always has been a Level-IV specification). Grounding of the metallic tray service/storage box. –Now the noise and gain are consistent with what has been seen on the mini-MCMs connected to single ladders. Long grounding screw in plated- through hole. (Conformal coat had to be scraped off.) Aluminum handle (part of service box), also grounded to the core.

29. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 29 Actions from the ASIC Review Example Layer-OR counting rate from 1 GTFE chip on a mini-tower tray (OR of 64 channels).

30. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 30 Actions from ASIC Review Make threshold scans on G and F version chips pulsing only one channel per chip at a time. –Pulsing only one channel, the noise sigma was about the same for G and F versions. –This confirmed the suspicion that the higher noise sigma seen in the F chip was related to crosstalk effects when multiple channels were pulsed. Measure noise occupancy versus threshold and determine at which threshold the occupancy deviates from gaussian noise. –The resulting plots give noise sigmas consistent with expectations. –Deviations from the exponential curve at low threshold are due to saturation from the time-over-threshold. We cannot see any evidence of spurious pickup.

31. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 31 Example Noise Rate Plot OR of 64 Channels. With a gain of 75 mV/fC the fitted ENC is 1710 electrons.

32. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 32 Single-Channel Noise Rates Only one channel at a time is enabled in the trigger mask, and the Layer-OR rate is measured by a frequency counter at each threshold setting. Two channels from the first chip are shown below. Fitted noise ENC: 1580 electrons and 1542 electrons respectively. No evidence of excess noise down to as low as 0.5 fC threshold.

33. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 33 Actions from ASIC Review Chips 0, 2, and 3 are FIB’ed ICs

34. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 34 Actions from ASIC Review Study the how the efficiency varies with threshold. –This was studied by the Bari group by Monte Carlo. –See LAT-TD-1128. The simulation is for single muons. Threshold (MIP)0 degrees40 degrees 0.2599.9 0.3098.596.0 0.3598.294.0 0.4097.792.4 0.4596.390.8 0.5092.089.5

35. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 35 Actions from the ASIC Review Test the system at high rates –This was done with a ladder, mini-MCM, and SLAC EGSE. –Self trigger, using the Layer-OR, and lower the thresholds on a subset of channels to achieve high trigger rates. –No new problems were found. –Below is a  source profile at low and high trigger rates.

36. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 36 Prelim. Results on the Flight ASICs GTFE V-G3: 1 wafer was diced without prior probe testing: –14 ICs were mounted on mini-MCMs and 4 on a full-size MCM (also populated with 20 older-version GTFE chips). –All 18 randomly selected chips worked 100%. –No evidence of the comparator instability that plagued the previous version (all 18 chips show identical behavior, with stable Layer-OR outputs even at the minimum threshold setting). –The timing margin on the register read-back was corrected: All 4 chips on the full-size MCM load and read correctly at VDD=2.5V up to 28 MHz (old versions fail at 23 MHz). All 4 chips also load and read correctly at VDD=2.25V and 20 MHz. –One mini-MCM was connected to a full-size ladder. Noise performance is similar to the previous versions. GTRC V-6: 1 wafer was diced without prior probe testing –Tested with probe card & test suite, as well as on mini-MCM and full MCM –All functionality is correct. –Timing margin improved: data readout works up to 30 MHz at 2.5V

37. GLAST LAT ProjectMarch 24, 2003 2A Tracker Peer Review, WBS 4.1.4 37 GTFE Version-G3 Noise Fits Example noise rate vs. threshold for a channel connected to an SSD strip. Distribution of fitted noise values, for a fitted average gain of 74 mV/fC. Avg.=1634 e 1638 electrons