1. The 10-ps TDC implemented in an FPGA
Jinhong Wang, Shubin Liu, and Qi An

2. Outline Implementation of FPGA TDC @ USTC
Timing Performance of FPGA TDC
TDC USTC

3. The Principle of the FPGA TDC
Coarse Counter (Coarse Time)+Time Interpolation within
one clock period (Fine Time)

4. Implementation of the Time Interpolation
Time Interpolation with the delay of Carry lines
a) Carry-in in a Slice
c) Carry chain of a multibit adder
b) Rout in a SLICE

5. FPGA TDC @FELab, USTC Up to the present
~100 ps Bin Size, 50 ps RMS ; In the year 2005
TNS Vol.53, Issue 1 Part 2
Time interpolation with the dedicated Carry lines
~50 ps Bin Size, < 20 ps RMS ; In the year 2009
TNS Vol.57, Issue 2 Part 1
With Several Compensation Strategies: self-test, Temperature compensation
Up to the present
~ 10 ps Bin Size (Effective) , <10 ps RMS
a Modified Wave Union TDC

6. The 10-ps FPGA TDC
Wave Union Launcher
INV+Delay+MUX

7. Signal Processing of the Raw TDC Time
N times Oscillation

8. Timing Performance 3 2 1 RMS vs. N
Uneven of the tap delay + Uncertainty of the Osc. Period
σosc << σcell
σosc ≈ σcell
σosc >> σcell 3
Simulation 2 1
Actual implementation falls in to Case 2
RMS vs. N

9. Timing Performance
Bin Size
scales as 1/N
Similar to dither
Bin VS. N

10. FPGA TDC Module ~20 ps RMS, 50 ps Bin NIM, USB, other platforms
Xilinx, Altera
< 10 ps RMS, 12 ps Bin (planed)
PXI, VME, USB
Xilinx Virtex 4, Virtex 5…

11. The 25-ps FPGA TDC Module
Altera + XILINX
<25 ps RMS, 50 ps Bin

12. The 10-ps FPGA TDC Module 16 + Chnl. <10 ps RMS , ~10 ps Bin
Virtex 4 / Virtex 5, …
Platform: VME, PXI, USB 2.0
Others: Trigger Matching

13. Thank you ~

14. TDC
Resource
Used
Available
Utilization
10-ps TDC
Slice Register
2081
50560
4.1%
4-input LUT
3280
6.5%
20-ps TDC
684
1.4%
606
1.2%