1. Taking the Mystery out of Signal Integrity
Jan 2002
Taking the Mystery out of Signal Integrity
Dr. Eric Bogatin, CTO, GigaTest Labs
Signal Integrity Engineering and Training
134 S. Wolfe Rd
Sunnyvale, CA 94086
In this presentation, we're going to look at kind of a whirlwind view of what signal integrity is and, in particular, the role of high bandwidth models of interconnects.
Copies of the PDF versions of this file are available from the GigaTest website that you're welcome to download.
Copies of this presentation are available for download from

2. Overview
“There are two kinds of design engineers, those that have signal integrity problems, and those that will”
The four signal integrity problems
Why signal integrity will get harder to solve
The right design methodology
The role of accurate, high bandwidth measurements
Two case studies: switching noise, probing
You know, it's sometimes said that we quote here at the top that there are two kinds of design engineers -- those that have signal integrity problems and those that will. And this presentation is really about why that's the case.
We're going to be looking at how to generalize all signal integrity issues in terms of four fundamental families of problems, why these kinds of problems are going to get harder and harder to solve, and, in that perspective, how do we approach the design methodology to get the design right the first time and avoid the signal integrity problems.
And, in that perspective, we're going to be looking at what role measurements play and the use of measurements to build high bandwidth models of interconnects.
And, finally, we'll look at a case study, a simple example, of using measurements to create high bandwidth interconnect models for some surface mount terminating resistors.

3. What is Signal Integrity?
3 inch long PCB Trace
driver
receiver
Well, let's start with the real simple, obvious question of what really is signal integrity? And the simplest way to think about it is, it's really how the interconnects, the packaging and the passive of structures screw up the absolutely beautiful signals coming off the chips.
And, of course, once we identify the problems, what do you do about them?
As a simple example, we have a driver chip that's sending a signal out on a very short piece of interconnect, nice controlled impedance line on a circuit board to a receiver. The first simulation on the left hand side, we see the signal coming out of the driver as it would be if there was nothing connected to the driver. Nice, beautiful, simple signal, about a 100 MHz clock.
Well, in the adjacent simulation on the right hand side, we show what would the receiver see just sitting there three inches away on a nice controlled impedance circuit board, and you can see all the ringing.
That's a perfect example of how just the physical interconnects of the circuit board can really screw up the beautiful signals coming out of the chip.
How the electrical properties of the interconnects screw up the beautiful, pristine signals from the chips, and what to do about it.

4. General SI Problem #1:
If the instantaneous impedance a signal sees ever changes, some of the signal will reflect and the rest will be distorted.
Ringing is often due to multiple reflections between impedance discontinuities at the ends
Well, what's the cause of this ringing? Well, most people are usually familiar with this idea of impedance discontinuities. And this brings up one of the general signal integrity problems, one of the four families of problems we'll talk about in a moment, that as the signal propagates down an interconnect, if I was looking at what is the instantaneous impedance of the interconnect that it sees, if it ever sees a change in that instantaneous impedance, some of the signal's going to reflect and some of it is going to be distorted.
What we usually think of as ringing is really due to multiple reflections between the impedance discontinuities, typically at the ends, and so, we have down at the bottom on slide 4 an example of that driver chip that driving a three inch long printed circuit board trace and receiver.
That's how we would view the set up from the physical perspective, and now, if we look at it with electrical eyes, what we see is, and what the signal will see, a low impedance coming out of the driver, going into a 50 ohms impedance transmission line and a high impedance at the far end, and now, we can see that as the signal gets launched into the transmission line, going down one path, it sees this 50 ohms impedance. When it hits the end, it sees a really high impedance, it's going to reflect back and when it reflects back, and it sees the low impedance at the driver side, another impedance change, it's going to reflect back again, and now we see the origin of the ringing is the bouncing back and forth between the impedance discontinuities at the two ends.
3 inch long PCB Trace
driver
receiver
(low impedance)
(~ 50 Ohms)
(high impedance)

5. Signal Integrity Engineering is about Finding and Fixing Problems
3 inch long PCB Trace
3 inch long PCB Trace
Series termination (~40 Ohms)
Well, once we've identified the source of the problem, then we can think about how to solve the problem, and, in this case, on slide 5, we show how to get rid of this ringing problem. On the left hand side is the example of ringing from the three-inch long circuit board trace for that 100 MHz clock and on the right hand side, we show one of the solutions.
In this case, what we've done is implemented a series terminating resister on the driver side so that after the signal is launched in the transmission line, we still see 50 ohms in the circuit trace, until it hits the end of the receiver, where it sees an open. And we still get a reflection there. The signal heads back. But now, when it hits the source of the driver, if we match the series resistance that we put in there, that, plus the series resistance of the driver, the source resistance of the driver, if we match that to the 50 ohm of the transmission line, there won't be any reflection at the driver side, and so, we eliminate the multiple bounces.
And so, in this case, with a source series termination, the signal received by the receiver at the far end, we show in the simulation on the right hand side, nice beautiful, pristine signal. We've completely eliminated the ringing effects by controlling the impedance mismatch at one end of the line.

6. A Guiding Principle
In order to solve a signal integrity problem you must first understand its root cause
The simple example of how, if we understand the source of the signal [inaudible] problem, it kind of points us to the direction of the solution of that problem. And that, in a way, is kind of a general principle in signal integrity, which is, in order to solve a signal integrity problem, you first have to understand the root cause, and that is one of the biggest barriers to success in solving signal integrity problems.

7. Signal Integrity Initially Looks Confusing
TERMINATIONS
LINE DELAY
PARASITICS
CAPACITANCE
EMISSIONS
EMI/EMC
LOADED LINES
ATTENUATION
SUSCEPTABILITY
NON-MONOTONIC EDGES
POWER AND
GROUND DISTRIBUTION
GROUND BOUNCE
SKIN DEPTH
LOSSY LINES
IR DROP
INDUCTANCE
RINGING
CROSSTALK
CRITICAL NET
SIGNAL INTEGRITY
STUB LENGTHS
Because, in a way, if you have been involved in signal integrity for a while, you hear a lot of terms, a lot of effects. It's hard to make sense of them. It's hard to put them in perspective.
Here we show sometimes what the field of signal integrity looks like. It's a whole bunch of different terms that seemingly almost come up at random, hard to make sense of how to put it in perspective.
And so, we're going to provide you with a little bit of perspective about how to think about all of these signal integrity problems.
RETURN CURRENT PATH
GAPS IN PLANES
IMPEDANCE DISCONTINUITIES
TRANSMISSION LINES
REFLECTIONS
DELTA I NOISE
RC DELAY
UNDERSHOOT, OVERSHOOT
DISPERSION
MODE CONVERSION
RISE TIME DEGRADATION

8. The Four High Speed Problems
1. Signal quality of one net: reflections and distortions from impedance discontinuities in the signal or return path
2. Cross talk between multiple nets: mutual C and mutual L coupling with an ideal return path and without an ideal return path
3. Rail collapse in the power distribution system (PDS): voltage drops across impedance in the pwr/gnd network
4. EMI from a component or the system
Here we show a way of generalizing all those signal integrity effects and problems on the previous slide into four general families of problems.
The first family of problems is really related to signal quality associated with one net. One net, of course, is all the connectors connected together in a circuit board or product, so you might have a package lead going to a trace on a circuit board and it may have a couple of branches going to a couple of other packages and other receivers.
As long as they're all connected together, that's considered as one net, and, of course, when we talk about a signal net, we're talking about not only the signal net, but also the return paths, which typically in most boards is one of the planes associated with the multi-layer stack up.

9. See additional Notes
So, when we talk about signal quality of one net, what we're referring to really is this issue we just talked about, impedance discontinuities. Whenever we have impedance discontinuities that a signal sees in traveling down the signal path and the return path, as it propagates down the path, any impedance change is going to cause a reflection and what continues along is going to be distorted.
So, to minimize signal quality problems associated with one net, it says what we need to do is minimize the impedance discontinuities.
The second kind of family of signal integrity problems, crosstalk, is related not to just one signal net but to multiple signal nets, and, of course, their return paths. If we have two traces, we've illustrated here on the right hand side, and we send a signal into one, there could be another trace sitting nearby, just sitting there minding its own business. Nothing on it. But because of capacitive and inductive coupling between the active net and the quiet net, we'll get some of the energy from the signal on the active side coupled over to the quiet side. And it will couple over through either mutual capacitors or mutual inductors.
When the return path is a nice, ideal plane, as it is in most circuit board applications, the relative amount of capacitive, inductive coupling is about the same for a given system. It turns out if for a given spacing of the nets, of the traces, when the return path is an ideal plane, we've really establishing the geometry for minimum crosstalk.

10. See additional Notes
It's when we screw up that nice ideal return path and we make it not a plane, but discrete leads in a package, for example, or discrete pins in a connector that we have dramatically increased, typically the mutual inductance between the signal paths and that contributes to quite a large increase in cross talk. In the case where we have coupling through non-ideal return paths, we sometimes refer to that kind of noise as switching noise or simultaneous switching, but we're going to look at this in more detail in a little bit because it is such an important problem. This is the example we'll look at to build circuit models to describe and characterize mutual inductance in a moment.
The third general family of signal integrity problems is related not to the signal paths but to the power and ground paths. And this is in the power distribution network. Here we illustrate, on the right hand side, the power and ground distribution network typically planes, and the problem really arises from impedance in those power and ground distribution networks that as the chip switches and current flows through the core, as well as through IO drivers, we have transient currents flowing in the power distribution network, and those dI/dt's flowing through the power distribution network will cause voltage drops in the impedance of the power and ground planes, and the larger the impedance in the power and ground distribution network, then the larger the voltage drop.
And that means less voltage gets to the chip and so we say the voltage rails collapsed.

11. See additional Notes
It also says that the way to solve that problem is to minimize the impedance in the power distribution network, and one way of doing that is using planes for power and ground distribution, keep them very close together, and as large an area as possible. That's one way.
Another way is adding decoupling capacitors. They also decrease the impedance in the power distribution networks.
And the fourth general family of signal integrity problems is about EMI. It combines together the effects on the signal paths and the power distribution paths.
All three problems we talked about just recently, all contribute to EMI. In order to minimize EMI, we have to do what we can to minimize those other three signal integrity problems. EMI typically relates to either the susceptibility of the product to the outside world so that our fields from the outside world can couple in and cause false triggering in the product, or radiated emissions from the product and failing the compliance test like FCC or European stack.
So, all those problems related to signal integrity can all be grouped into one of these four categories, and if we understand the underlying cause of the problems in these four categories, the solution is pretty clear.

12. Conceptual Origin of Simultaneous Switching Output (SSO) Noise
Active loop
Switching lines
Quiet data line
On Chip V SS CC
GND
15836
© 1991 Integrated Circuit Engineering Corporation L
Bonding
Power
common
lead
inductance
Icharge
Idischarge
Quiet loop
We're going to take a close look at one of these problems related to crosstalk just to understand the mechanism and also understand a little bit the role of mutual inductance and how the rise time affects the amount of switching noise.
First, we're going to look at the measurement. This was, on the right hand side, measured signals coming off a couple of lines that are switching data lines, and you can see a little bit of ringing, what looks like ringing anyway in some of the signals. As it turns out, as we'll see, it’s that's actually due to crosstalk among the various multiple switching lines.
And you can kind of see a better idea of the crosstalk in the quiet line. On the bottom trace, here's one of the lines that was sitting there, not switching at all, and this is the voltage picked up in that line, and you can see that wherever the active lines switched, we have a little bit of noise that's generated, actually, a lot of noise that was generated.
And this noise was generated really by mutual inductance between the switching lines and the quiet lines. And to illustrate that, over on the left here, we have kind of a schematic of what the set up was for this system.
What influences SSO Noise:
 Mutual inductance between the loops
 Number of SSOs
 dI/dt

13. See additional Notes
We have a schematic of a small chip that had, in this case, five output drivers on it, and this happened to be a small 2 layer BGA package, and they were connected to transmission lines on the circuit board, which in this case, I've drawn as small coax cables, just to emphasize that there is very specific return path associated with each of the signal lines.
So, in this particular case, we had a couple of active lines that were switching. We'll look at it in the case of going from a high to low transition, and as they went from high to low, they discharged or sent current out of the signal path, went through the driver, through the ground rail on the chip itself, back out through the ground lead in the chip, and then back to the return path of the transmission line, and continue that current loop as the high to low transition propagated down the transmission line.
So, we had current sloshing in a loop that took into account a couple of the package leads and part of the trace from the circuit board.
In addition, there were these other traces, without the drivers, sitting there, and the one on the bottom, we show as the quiet line, tied to the low voltage side.

14. See additional Notes
The connections represent a loop. There was the signal path going through the chip connected to the ground rail, on the chip going through the ground lead and the package and back to the return path, and so we see there were these two loops.
When current sloshed in the active loop, it generated noise in the quiet loop. And that's exactly what we see in the noise generated on the quiet line.
The amount of noise that we generate on the quiet line depends, and we call that simultaneous switching output noise or SSO noise because it happens coincident with the switching on the active lines.
And we see at the bottom that this simultaneous output switching noise really depends on the mutual inductance between the two loops and how many of the gates are switching simultaneously and what the mutual inductance between each of those other gates might be, and it depends on how fast the current changes for the dI/dt. Sometimes this is called the dI/dt noise, sometimes Delta I noise.
And we also see that the magnitude of the noise depends, first, on the mutual inductance and, second, on the dI/dt, so, as the rise time decreases, the dI/dt is going to increase, the amount of switching noise is going to increase. And this is fundamentally why, in particular, crosstalk and switching noise is going to increase as rise times decrease, and that is, unfortunately, inevitable as clock frequencies increase.

15. Projected Increase in Clock Frequencies
Microprocessor based products
Here we show the march of, the treadmill like march of increasing clock frequencies for microprocessor based products, both clock frequencies on chip as well as on board, or coming off chip clock frequencies.
And as clock frequencies increase, it's actually inevitable that the rise times are going to have to decrease in order to provide those higher clock frequencies.
And the shorter the rise time, the larger the switching noise, in particular, and the larger impact from all the other effects of impedance discontinuities, rail collapse, and EMI.
So, microprocessor based products are going to have higher clock frequencies, which means greater signal integrity problems.
Source: SIA Roadmap

16. High Speed Serial Link Applications Drive High Frequency
Hypertransport 1.6 Gbps (400 MHz- 1.6 GHz)
AGP8x 2.1 Gbps (533 MHz)
3GIO 2.5 Gbps (2 x 1.25 GHz)
Infiniband 2.5 Gbps (2.5 GHz)
OC Gbps ( 2.5 GHz)
OC Gbps ( 10 GHz)
RapidIO16 32 Gbps (1 GHz, 16 bit mode)
OC Gbps ( 40 GHz)
In addition to microprocessor based digital products, we also have the telcom products. Slide 11 is just a list of the kind of clock frequencies or data rates associated with the telcom applications. OC-48 is in wide scale deployment right now. The data rates are about 2 1/2 gigabits a second, and, depending on the encoding scheme, clocks can easily be in the 2 to 2.5 GHz clock rate. At 2.5 GHz, the whole period is only 400 psec, so that means rise times are going to be on the order of sub 100 psec.
Now, with the short rise times, all these signal integrity problems get worse, and as OC-48 goes even into larger volume production and implementation, more and more systems are going to have these signal integrity problems and OC-48 is not the limit. OC-192 systems are coming in right behind them. Rise times there are in the sub dozen or so psec, so signal integrity problems are only going to get worse.

17. A Scary Future So what’s the right design methodology?
Smaller transistor channel lengths 
shorter rise times, higher clock frequencies
Short rise times
signal integrity problems get worse
Shorter design cycle times
designs must work the first time
And so, in a way, what we've done is kind of painted this kind of scary future of what's coming along. The reason rise times are decreasing, as shown on slide 12, is fundamentally because transistors are getting smaller and particularly the channel lengths of transistors is getting smaller and that allows it to switch faster.
That gives them shorter rise times which results in higher clock frequencies, and, as we saw earlier in the one example, shorter rise times means signal integrity problems are going to get worse. And, of course, there's the other problem that in our globally competitive marketplace these days, you get less time required, or less time available in order to get the product to market.
Design cycle times are getting shorter and shorter, and that means you don't have time for a lot of iterations. The designs have to work the first time. And that's why we often say, there are two kinds of design engineers. Those that have signal integrity problems and those that will.
If you don't have them now, as systems progress to higher clock frequencies and shorter rise times, you will have them.
“There are two kinds of design engineers, those that have signal integrity problems, and those that will”
So what’s the right design methodology?

18. Example: Gold Dot Interconnect from Delphi
General Construction
Applications
So, we have to implement a new design methodology. And by way of illustration, I'll show you what one customer did. This is an example from Delphi Electronics. This is on slide 14. This example is the design process for this particular component they make, which is very high bandwidth connector for printed circuit boards.
We show three different configurations for their connector. It's basically on the far right hand side, is an example of connecting two printed circuit boards.
There's a flex connection with two mechanical adapters for the two boards. And this is fundamentally the actual product that they're making, the flex piece and mechanical adapters.
It's currently used in high volume applications for a number of server products as well as telecommunications products.
Courtesy of Laurie Taira-Griffin, Delphi

19. The Old Build it and Test it Design/Manufacturing Cycle
Design of Circuit based on Performance of Previous Design
5 Days
Manufacture
(CAD 2 Days)
4 Weeks
Redesign
3 Days
One Cycle
9 Weeks
Average 2 Cycles/Design
Test (TDR, VNA, BERT)
1-2 Weeks
Cross Section
Confirm Physical Layout
2 Days
Well, the design process to come up with the correct mechanical design and layout and stack up for this connector used to take almost nine weeks, and we show in slide 15 why that build it and test it approach took so long for this product.
When a customer came up with a new set of performance criteria, they would take a look at what design did they have that came close in the past, modify that. That took about five days. They'd go ahead and based on the previous design make a guess about what the new design should be. They went ahead and built it. That was four weeks.
It would come back. They'd schedule in for an array of measurements to characterize the part. Then they would create the SPICE models from the measurements. Then to verify, they had the geometry read. They would do cross-sections on it, and then based on the results of the cross-section and how close the measurements came to the performance they were looking for, they might have to redesign it and then send it back in the queue, and so it was nine weeks before they had a rough idea, even if they got it right the first time that their product meet the right performance spec.
And if they needed to go two iterations, that's 18 weeks to get a product, this connector, that would meet the performance spec of their customer. Way too long in today's very short cycle time era!
SPICE Model
1 Week
Courtesy of Laurie Taira-Griffin, Delphi

20. Key Ingredient to the New Design Methodology: Predicting Signal Integrity Performance
Critical processes for predicting signal integrity problems
Create equivalent circuit models for all components
Simulate performance of components, critical nets and the whole system
The better we can predict performance:
find and fix problems as early in the design cycle as possible
reduce extra design margin required
reduce time to market
reduce risk
reduce development and production costs
So, what did they do in order to fix this? Well, the main thing they did, on slide 16, was integrate some signal integrity engineering.
And, basically, signal integrity engineering is all about predicting performance.
If you're able to predict the performance of the product before you build it, you have a lot of advantages. You don't have to design in extra margin. You get it done quicker. Lower the risks. You have confidence it's going to work the first time, and that also lowers the development and production costs.
And the key ingredient to be able to predict performance is these two processes that we list here. Be able to create equal circuit models for all the components, circuit models that you have confidence in, and be able to simulate the performance of the components based on those equivalent circuit models.

21. Role of Measurements
Verify a model and simulation from a calculation (anchor to reality)
Rules of thumb
Analytic approximation
Numerical tool: field solver, circuit simulation tool
Create a model from a real structure
Directly from the front screen
Iteration process: inverse scattering
So, creating circuit models and simulating performance based on circuit models are absolutely key, critical ingredients, and in that perspective, measurements play a very important role.
We may use. On slide 17, we show the role of measurements. We may use calculations in order to create the model. That's often the quickest way to get an equivalent circuit model for a component, either with rules of thumb or approximations or even numerical simulation tools.
But we use measurements to verify that process, to make sure that we have an accurate way of predicting the equivalent circuit model for the different components or interconnect that we're concerned about.
When we don't have a good modeling tool available to allow us to calculate a good equivalent circuit model for the component, that's when we can use measurements to create the model directly from a real physical structure, and we're going to show a couple examples of how to create circuit models, using measurements directly from the front screen and, as we'll see, there's a limit to how high bandwidth and how accurate we can get just from the front screen. Really, to get the most accurate high bandwidth models for measurements, we're going to be using an iterative process, which we call inverse scattering.

22. GigaTest Probe Station
Example: Implementing a Characterization Loop to Develop and Verify Modeling and Simulation Process at Delphi
VNA
Measured
OC-192
BER
TDR
GigaTest Probe Station
Simulated
Device Under Test
So, with this perspective, let's look at what Delphi Electronics was able to do by integrating a process that allowed them to create circuit models, using calculations, verify it with measurements and then integrate this design modeling and simulation process in their overall design flow.
They set up measurements. On slide 18, we show their lab, to fully characterize the part, and to confirm the analysis software, the simulation software, that predicted from the geometry and would show properties what the final performance would be.
They used a bit error rate tester. We show in the upper left hand corner. They had TDR, a GigaTest probe station, in order to fixture, the various configurations of their connector, and a network analyzer.
And we show a close up of one of their connectors in a specialized fixture to interface to the network analyzer in this case.
They performed a variety of measurements. One example we show here on the right hand side is the measured I diagram for an OC-192 kind of signal, and below that is the simulated signal based on the modeling and simulation tools they implemented, and they used all of these measurements to verify the modeling of simulation tools, and you can see pretty good agreement between the measured result and the simulated result for this particular connector.
Courtesy of Laurie Taira-Griffin, Delphi

23. Final Verification of Model and Performance Simulation
Parameter
Simulation
Measured
Goal
Single Ended Impedance
52.1 Ohms
53 Ohms
50 +/-10% Ohms
Differential Impedance
95.2 Ohms
98 Ohms
100 +/- 10% Ohms
Attenuation (5GHz)
<.44 dB/inch
<.5 dB/inch
Propagation Delay
152 ps/inch
158 ps/inch
170 ps/inch
Single Ended NEXT
<4.5%
<5%
Differential NEXT
<.3%
<.5%
Data Rate
>5 Gbps
5 Gbps
And on slide 19, we kind of summarize an example of using measurements to verify their simulation and we look for the various parameters that were measured, you can see a variety of them, the result obtained from the simulation in the next column compared for those same physical structures that were modeled and simulated but was actually measured, and you can see that it's a very good agreement, and so using measurements, they were able to develop a modeling and simulation process they had confidence in.
Courtesy of Laurie Taira-Griffin, Delphi

24. Cycle Time Reduction with Reliable Modeling and Simulation
Was: > 9 weeks to reach correct design
Now: 4 hours to reach correct design
Trace
Width
Pair to Pair
Spacing
Signal Layer
Ground Plane
So, now, using this modeling and simulation tool, instead of having to build it and test it and rebuild it and test it again to verify it, they were able to cut their design cycle time from over nine weeks to, we show on slide 20, about four hours, because they had a modeling and simulation tool they had verified and had confidence would provide accurate electrical predictions.
And so, now, their design process load consists of taking customer performance spec data, performing a design on the cross-section and the physical layout of the connector part, modeling that design, simulating the performance and checking for agreement with the customer performance spec, and iterating that a few times, which they can do very quickly, resulting in less than four hours to reach a final design they can send and release and manufacture and have confidence that when the part comes back, it's going to meet the performance spec.
This is an example of using measurements to verify a modeling and simulation process flow. The purpose of the measurements in this case was to make sure and provide confidence that we had a modeling tool that gave us accurate models for the interconnects.
Courtesy of Laurie Taira-Griffin, Delphi

25. Role of Models
Accurate models of interconnects
Accurate models of the active devices
Robust simulator
Prediction of performance + =
And slide 21, we show really the place for those models in the design flow. The whole goal of signal integrity engineering is, as we show on the bottom here, to predict the performance of the product, whether it is a component of a subsystem or the whole system, and, in order to predict performance, we need accurate models for the interconnects, accurate models for the active devices and a simulator that can integrate both of those sets of models and look at the actual wave forms that the real products might see.
Using as input the accurate models for the interconnects and devices and using that to evaluate the system performance, the earlier in the design cycle process we can do that, the quicker we're going to find problems and design them out and the shorter the design cycle time is going to be.
So, we're going to look at now a previous example of looking at using models from calculation and using measurements to verify the models. Now, we're going to look at, but what if you don't have a good way of calculating and simulating the models? What if we need to use measurements in order to measure the components and extract a circuit model? How do we do that?
The earlier in the design cycle problems are found and designed out, the shorter the cycle time, the lower the development costs

26. Two Case Studies: Measurement Based Model Extraction
Modeling 2 SMT resistors and predicting switching noise
Modeling an active scope probe and optimizing it for minimum artifacts

27. Important Elements to a Complete Measurement/Modeling Solution
Probes
Probe station
GigaTest Labs
Probe stations
Instruments  Controlling software
Infiniium DCA with TDR  TDA Systems software
Vector Network Analyzer  Agilent Advanced Design System (ADS)
And in slide 22, we're going to look at the components needed in the system in order to create and extract high bandwidth accurate interconnect models of passive structures. In addition to the instrument itself, for example, the network analyzer or TDR, in addition to the instrument, we need a way of interfacing from the instrument to the device under test. One of the ways of doing that is with a GigaTest probe station we see on the left hand side. It allows a large field in which to work so you can put a whole backplane and a daughter card on the probe station and allows the precise manipulation of probes to make contact with the device [under test] with minimum parasitics and allows calibration right down to the probe tip itself. On the other end, once we have interfaced the device [under test] with the instrument, if we're limited to interpreting the results right from the front screen of the instrument, there's a limit to what we can, how accurate and how high bandwidth a model we can get from the front screen. In order to get the most out of it, we need to use controlling software to interpret the results. In the case of DCA 86100, for example, with a TDR plug-in, the controlling software to talk to the TDR and interpret the results can be provided by TDA System software. In the case of a vector network analyzer, the best controlling software to take the data and interpret the results is Agilent's ADS. And we're going to show some examples of using ADS in order to take the measurements and interpret the results in terms of very high bandwidth accurate circuit models.

28. Measured S11 of one 0805 SMT Resistor
Two, 0805 resistors, ~ 120 mils centers, far end shorted to return plane ~ 15 mils below surface
Smith Chart of Measured S11
The first example that we're going to look at on slide 23 is for two surface mount terminating resistors. We show in the photograph on the upper left an example of the two resistors mounted to a circuit board. These are 0805 resistors. They're about 120 mils center-to-center pitch.
In this particular case we have a return path that's located at the plane, located about 15 mils below the surface. This is comparable to what a return path might be in an actual usage board. These resistors would be used as either source termination or far end termination. The signal would travel down to the resistor and then it would be shorted to the return path at the far end as we go through it here with the VIA.
In this particular case, we're going to connect to the front end of each of the two resistors a small connection for the signal and also to the return path adjacent to it, and we're going to do that for both ends of the resistors.
One resistor will be port 1. The other end will be port 2, and in this way, we'll be able to look at the properties of each resistor alone and when they couple together.
And
Measured with a
Vector Network Analyzer (VNA)
Close up of typical probing method

29. See additional Notes
down below, we show a close-up of how we actually do the connection to the component. We're using microprobes with very minimal parasitics and we've calibrated the probe tips with the network analyzer right down to the tips. We send. The signal path comes out of the center tip into the resistor, through the resistor, through the shorting VIA at the far end, back through the return plane and then coming up through the VIA at the front end, and then back into the return path of the cable.
And so, effectively, what we're doing is we're measuring the reflection coefficient of that resistor loop at the front end.
When we actually do an S11 measurement, we show over on the right hand side, the Smith chart of a typical measurement for this roughly 60 ohm terminating resistor.
And from this measured Smith chart, we're going to interpret a circuit model.
For those of you that might be familiar with it, you might imagine that it's going to look like a resistor at the low frequency and you can also see that there's some inductive component coming up, so the first model we might think of is a simple RL in series, and from the RL circuit models in the series, we can almost read off the front screen of the network analyzer using markers what the typical value for R and L might be.

30. 1st and 2nd Order Models, Created and Simulated with Agilent Advanced Design System (ADS)
R = 50 Ohms
L = 2 nH
C = 0.3 pF
measured
modeled
Non-optimized values
2nd order model
R = 50 Ohms
L = 2 nH
1st order model
modeled
And on slide 24, we show the values you might get off the front screen on the left hand side. We call this our first order model. It's really the simplest model we can come up with. The equivalent circuit model is really an ideal resistor in series with an ideal inductor, and that's basically what the network analyzer is assuming, when we read the real part of the impedance as 50 ohms with the markers off the front screen, and the imaginary part of the impedance, which we interpret as an inductive, we read as roughly about two nH.
So that is roughly the first starting place model that we would read right off the front screen in the network analyzer. We can't get much further than that unless we take that model and these values and use ADS to simulate what would a network analyzer measure if we had this equivalent circuit model of an ideal resistor and ideal inductor. And we show down below here the combination of the measured result on the network analyzer and what we would simulate the measurement to be based on this model, and we see that it's not too bad at low frequencies. That was kind of what we got from the network analyzer, but, clearly, the high frequency is not very good. There's no better values for R and L that's going to get us much better agreement than we've already got here in this case. We're limited in what we can do with this topology in terms of getting good agreement between the measured and the modeled results.
measured

31. See additional Notes
In order to get better results, we really have to increase the complexity of the model, and we move to a second order model. And in the second order model, what we've done is take into account a little bit of the capacitance associated with the body of the capacitor to the return path and added that in parallel. The real question, though, is, what's the value of capacitance to use? How much capacitance should we use? Now, we can start playing around with some values, just kind of guess some values, and by guessing some values and playing around with the value for the R, L, and C, we get sort of pretty good results, and we see the comparison on the bottom Smith chart of still the measured S11 for one of these resistors in red and superimposed on that, we have what we would simulate as S11 based on this ideal circuit model, given these parameter values up above, and you can see, we're getting pretty good agreement, but it's still not that great at high frequencies.
There must be a better combination of R, L and C values, parameter values to give us better agreement. We could keep trying values for hours and still not get a lot closer than this.
Really, the best way to get, to find the optimum values is to use the optimization features already built into ADS.

32. Using ADS to Optimize 2nd Order Model
Optimized values:
R = 52 Ohms
L = 1.85 nH
C = pF
measured
modeled
And in slide 25, we show that same circuit model, the R, L, and C topology that stayed the same, but now we've let the built-in optimizer in ADS find it for us, the best values for the resistance, the inductance, and the ideal capacitance, to give us good agreement between the measured result and the simulated modeled result, and you can see in the Smith chart, on the left hand side, that once we've found the optimum value for R, L and C, we get absolutely excellent agreement between the measured result and what we would simulate based on this ideal circuit model.
And to give you a little better idea of the agreement, we've re-plotted. Instead of a Smith chart, we've re-plotted the magnitude of S11, both measured and simulated and the phase of S11 and up to the entire bandwidth of the measurement, 5 GHz, but we see that there's excellent agreement between what's measured and simulated based on this ideal circuit model both in the magnitude and the phased, and this is what gives us confidence that we have a good equivalent electrical circuit model for this component.
And we also see that the bandwidth of this model is at least 5 GHz and could be much higher than that. We just don't know because the bandwidth of the measurement is only up to 5 GHz, in this case.

33. Features of the Model
A simple model matches the measured performance very well
The interconnect model is very accurate
Bandwidth of the model is at least 5 GHz- could be higher
The precise parameter values will depend on the location of the return plane and the via structures
So, we've really illustrated, summarized on slide 26, is that we've built a very simple model, composed of three ideal circuit elements that matches the measured performance very well.
It's very accurate. The model that we've created is very accurate. It matches the measured performance, almost to the line width of the pen that we used to do the plot, and it has a very high bandwidth. In this particular case, the bandwidth of the model is at least 5 GHz. Probably is higher. We just don't know. We'd have to do measurements at higher values.
So, this is a very simple example of creating very accurate high bandwidth models from measurements, using ADS to optimize these certain parameters.
Of course, in this particular case, since it was based on a specific measurement of a specific complement, the precise parameters that we extracted depends very strongly on the physical geometry.
If we changed the location of the return plane, for example, moved it closer to the top surface, we would change the loop inductance and the capacitance.
If we moved the return path closer, we'd probably decrease the loop inductance and increase the capacitance.
So, of course, it depends very strongly on the specific geometry of the problem that we, of the structure that we actually measure.
Well, given this starting place, building a circuit model for the individual resistor, now let's look at the coupling between the two resistors.

34. Measured Coupling: S21 % 1 . 10 V = What does – 60 dB coupling mean?
Now, slide 27, we're going to now measure the coupling between the two surface mount resistors by sending a signal into one port and looking at what comes out of the second port. That's basically an S21 measurement in this configuration. On the right hand side, we show the actual measured S21 and S11. I'm sorry, S21 and S12, because of the symmetry of the problem. They're both identical, and they're superimposed on the measurement. We show the measured S21 versus frequency up to 5 GHz, and you can see that, in this particular case, it starts out at very low coupling. We've seen about -60 dB at low frequency and rises up to as high as about 22, 23 dB at the high bandwidth end of the measurement. Let's think for a minute, what does this really mean? We're talking about the coupling sending signal into the one and looking how much appears on the other one. What does 60 dB really mean? Well, we can use the very simple relation and figure out how much voltage noise does that really correspond to? When we put in the numbers, that's not a tenth of a percent, so at low frequency, not much coupling at all. A tenth of a percent is almost negligible, but as the frequency of the signal increases, so the bandwidth content would increase, we see the coupling can get a lot larger. How much coupling is too much? % 1 . 10 V 3 20 dB 60
active
quiet = -
How much coupling is too much?
Depending on the noise budget, ~ -30dB (~ 3%)

35. See additional Notes
Well, as kind of a rough measure -- obviously, it depends on the noise budget and how much has been allocated, but as a rough measure, 3% is not unreasonable allocation of coupling or crosstalk, and 3% corresponds to about minus 30 dB, so just looking at the measured result, we would say, if we look at the plot, we would say that the upper limit bandwidth, the highest bandwidth this structure, this component, could be used at or these pair resistors in this configuration, is roughly about the 2 GHz range. Beyond that, we would expect to see a little too much coupling. So, that's what we can read off the front screen of the instrument without a lot of difficulty. But, really, what we'd like to do is understand, okay, maybe our application is close to that bandwidth. Maybe it's a little bit higher. Just what is going to be the impact on switching, on performance from this component.

36. Modeled Cross Talk
measured
modeled with L21 = 0.28 nH
Topology for coupled resistors uses exactly the same circuit model for isolated resistors, with mutual inductance added
What does the switching noise look like in the time domain?
@ 3.5 GHz, coupling ~ -25 dB, ~ 5%
With 100 psec rise time, expect VSSN ~ 5% x 3.3v ~ 160 mV
The way we can evaluate that is by building an equivalent circuit model to describe the mutual inductance between these two parts, and on slide 28, we show the equivalent circuit model for the two coupled resistors.
We have the simple model, the LRC model for each individual real resistor. This is what we developed in the previous example, when we did measurements on an individual resistor, and now, to take into account the coupling, we've included the mutual inductance term that couples the two loop inductances of the surface net resistors, and, again, by using ADS and optimizing the one parameter, the mutual inductance, between the two resistors, we can use the measurement to find and extract what the best value mutual inductance is, and you can see on the measured data on the right hand side, we're comparing in red the measured coupling, S21, and in blue, what we would simulate based on the model. And this circuit model, ideal components, that has this simple ideal mutual inductance between the two loops.
R = 51 Ohms
L = 1.85 nH
C = pF
K = (L12 =0.28 nH)

37. See additional Notes
And what we see is, again, absolutely excellent agreement. I mean, all of this coupling effects can be completely accounted for in terms of this ideal circuit model that includes mutual inductance.
And by varying the value of mutual inductance and optimizing the model response to the measured response, we can extract the mutual inductance in this configuration to be about .28 nH, and that should be compared to the loop inductance we see down here on the lower left of 1.85 nH per surface mount resistor, and that gives a couple coefficient of about 15% for the mutual inductance.
So, we've now got an equivalent circuit model for the two surface net resistors that includes the effective coupling, and from this equivalent circuit model, we can do system level performance simulations to look at what the impact on switching noise might be.

38. Simulating Switching Noise in the Time Domain with ADS
And in slide 29, we show how to set up a subsystem simulation, performance simulation, based on the circuit model that we've created from measurements. We have the circuit model for each individual resistor. We've added the mutual inductance between that accounts for the coupling between them, and now, we've added and made one of the resistors part of an active line, so we've got a simple model for device driver, some source impedance associated with it, a short length transmission line, and the second line is just sitting there as a quiet line, and we've effectively modeled and connected to a tri-state device, so it's just output of the device that it's connected to is in a high impedance state.
What we're going to do is drive the active line, the clock signal, and look at the noise generated on the quiet line. At the bottom here, we emphasize that it's exactly the same model that we created from the measurements. We're using a low impedance source driver, typical of a lot of bus drivers. The quiet line is in tri-state, and we're going to use a 500 MHz clock signal, not untypical to some of the high end, leading edge devices, with 500 MHz, it's about a 100 psec rise time.
Same model of the coupled resistors
5 Ohms source impedance of the driver
Quiet line receiver in tri state
Rise time of 100 psec, BW ~ 3.5 GHz, 500 MHz clock

39. Simulating Switching Noise
Active Line
And now, let's take a look at what we actually simulate. On slide 30, we show the driver signal with a 100 psec edges. This is the 500 MHz clock, and on the bottom, we show what is predicted on, or simulated on the quiet line, based on just the measured mutual inductance between the two surface net resistors, and you can see that we're predicting about a little less than 150 mV, and 150 mV out of 3 volt voltage sling is just about 3%, which is about what we estimated at the 2 or 3 GHz kind of bandwidth point.
Now, this switching noise that we see on the quiet lines should look a little familiar because that's real similar to what we saw previously, and I've reproduced on slide 31 the measured switching noise on one of these quiet lines, and that was all due to mutual inductance.
Quiet receiver
Does this look familiar?

40. Measured Switching Noise in Graphics Processor Daughter Card
Switching lines
Quiet data line
In the previous case we just simulated, it was mutual inductance in determining resistors. In this particular example, the measured switching noise on some data lines just happens to be mutual inductance in some package leads.
But it's all the same circuit model and all the same physical effect. In general, this problem of switching noise, which is related to the mutual inductance between adjacent signal paths is all about mutual inductance. It causes about, roughly 90% of all the switching noise problems.
So, if we understand mutual inductance, we understand how it physically arises, and we understand how to measure it and build circuit models for it, we can predict the performance, the switching noise performance, of real systems, using these sorts of measurements.
Mutual inductance causes 90% of all switching noise problems
Is the “ringing” real or artifact?

41. Probing Signals in Active Circuits
Agilent 1158A Active Probe,
(not using recommended fixturing)
Measured signal through probe
~ 1 GHz
200 psec rise time signal
1 nsec/div
What causes the ringing?
Is it real or artifact?
How can the artifacts be minimized?
Courtesy of Mike McTigue and Dave Dascher, Agilent

42. What Impedance does the Signal See for the Probe?
Measured impedance looking into the probe tip
(measured using VNA)
(not using recommended fixturing)
Features of the probe’s input impedance
Really high impedance < 100 MHz
Capacitive > 500 MHz
As low as 10 1 GHz!
Multiple resonances
Courtesy of Mike McTigue and Dave Dascher, Agilent

43. Circuit Model of the Probe: Simulated with Agilent ADS
Probe tip
21 nH
26 nH
Simple model fits the measured impedance really well
Ringing is due to the LC
L due to the long lead (~ 5 cm x 10 nH/cm)
Model can be used to evaluate impact on the circuit under test
123 fF
196 fF
667 fF
25k 
84 
10 
Measured impedance
Modeled impedance
Courtesy of Mike McTigue and Dave Dascher, Agilent

44. All the Ringing is Due to the Artifact of the Probe Tip
Measured
Simulated based on the Model
Courtesy of Mike McTigue and Dave Dascher, Agilent

45. Step 1: Optimize Probe Performance by Minimizing Tip Length
5 cm
There is still some LC ringing from the tip!
1 cm
Courtesy of Mike McTigue and Dave Dascher, Agilent

46. Step 2: Damp out the Ringing with a Resistor
Rdamping
Measured impedance looking into the probe
with resistor
without resistor
First order estimate of R based on Q ~ 1
Role of the resistor:
Damps the ringing
Keeps loading of the circuit high
Optimizes the bandwidth of the transfer function
R ~ 100 – 250 
Courtesy of Mike McTigue and Dave Dascher, Agilent

47. Performance Improvement from Damping Resistor: tin = 200 psec
5 cm tip
t ~ 385 psec
R added
Probe bandwidth ~ 4 GHz
1 cm tip
t ~ 225 psec
R added
Courtesy of Mike McTigue and Dave Dascher, Agilent

48. Agilent 1158A with Integrated Damping Resistor Tips
Courtesy of Mike McTigue and Dave Dascher, Agilent

49. Summary of Good Probe Techniques
Agilent 1158A
Keep probe lengths as short as possible
Use integrated damping resistor
Select R value based on Agilent recommended table
Always consider the impact of the probe’s impedance on the circuit performance
Courtesy of Mike McTigue and Dave Dascher, Agilent

50. The Critical Ingredients to Solving Signal Integrity Problems
Principles
and
Understanding
Analysis:
Rules of thumb
Approximations
Numerical simulation
Characterization
Vector Network Analyzer
Time Domain Reflectometer
So, let's kind of summarizes where we've gotten to, on slide 32. We've really said that, in order to really provide signal integrity engineering and apply that to high speed design problems in the measured MHz range, a hundred MHz clock frequency and above, where signal integrity problems start, what we've tried to illustrate is that it really takes three specialized tools.
One is the understanding. It's the principles. And we talked about the different sources of signal integrity problems, the three families, and the root causes.
It involves the use of tools to create circuit models and perform simulation, and the use of measurements in order to verify the modeling simulation tools and where modeling tools are not available, to create the circuit models directly.
And, in order to apply signal integrity engineering to new designs, so that every design is really a custom design, it really requires the combination of these three sets of tools.
Because a redesign is really custom, we really can't apply old rules that might have worked in a lower performance system to the new design that's working at higher clock frequencies, shorter rise times, or with a new set of drivers and a new physical design.

51. Conclusions The bad news: The good news:
Signal integrity problems will only get worse as rise times decrease
Design cycle times will only get shorter as the industry becomes more competitive
The good news:
Accurate modeling and simulation tools are critical to find and fix signal integrity problems as early as possible in the design cycle
Measurements are essential to verify and create accurate high bandwidth models
Understand the source of probing artifacts and optimize the probe design to minimize them
Help is available: GigaTest Labs (Agilent VAR) can assist you in:
providing a complete turn key measurement system
performing measurements and creating models for you
helping you move up the learning curve with signal integrity training
So, what have we come to in the last 35 minutes or so? On slide 33, we're summarizing where we've gotten to. We've said that because rise times are getting shorter, signal integrity problems are only going to get worse. We've said that design cycle times are getting shorter because of a more competitive industry. That means that we only have time to get it right the first time, and that absolutely requires accurate modeling and simulation tools so that we can identify and fix signal integrity problems as early in the design cycle as possible.
And, in that context, we've said that measurements are essential to first verify the modeling and simulation tools to provide confidence in that tool, and where we don't have the ability to create a circuit model from a calculation, to use the measurement to create a circuit model or to verify that a part meets a specification as it comes in to make sure that we use the right model in our simulation.
And, finally, just let me mention that GigaTest Labs, which is a value-added reseller of Agilent products can really assist you in this process.
We can provide complete turn-key measurement system that includes the probes, probe station equipment, measurement instruments, and the simulation software. We can also do the measurements for you and return high bandwidth accurate models and interconnects for you, and we can help you move up the learning curve, by providing training in signal integrity engineering.