2. May 17, 20002 Platform Design Considerations Jim Choate Intel Corporation

3. May 17, 20003 Agenda w Guidelines w Measurement Techniques w Early Testing Results w Summary

4. May 17, 20004 Guidelines w USB 2.0 guidelines will be more systematic, detailed than 1.x whitepapers w Proposed guideline areas: – Attenuation, jitter budgets – Package/board/chassis design – EMI/EMC – Use of test modes and testing for compliance

5. May 17, 20005 Board Design w 4 layer sufficient; trace impedance matching is key w 3 ns + 26 ns + 1 ns w Avoid long runs w Do not cross plane splits w Minimize vias w Maximize distance to other traces Motherboard Is the Toughest Environment

6. May 17, 20006 Board Design Guidelines w Board Stack-up: – 4 layer, impedance controlled boards required – Impedance targets must be specified – Ask your board vendor what they can achieve Classic four-layer stack Signal 1 Prepreg VCC Core Ground Prepreg Signal 2 Example target impedance: 0.005 in trace at 60+/-15%  7.5mil traces with 7.5mil spacing Zdiff  90 

7. May 17, 20007 Routing Guidelines w Control trace widths to obtain target impedance – Ask your board vendor what they can achieve – As always, cost is a consideration w Maintain strict trace spacing control w Minimize stubs D-D- D+D+ 15k  Correct way to connect to resistors

8. May 17, 20008 Routing Guidelines w Routing over plane splits w Creating stubs with test points w Violating trace spacing guidelines Common Routing Mistakes Ground or power plane tp Don’t cross plane splits Proper routing technique maintains spacing guidelines

9. May 17, 20009 Measurement Techniques w Selecting appropriate test equipment – Accurate measurement of signal quality requires an oscope and probes with adequate BW and sample rate – Proper test fixtures are also important Equipment that will work Scope: TDS 694C - 10GS/s, 3Ghz Probe: P6247 Fet Probe - 4Ghz,.4pF typ 90  Differential Probe

10. May 17, 200010 Board Testing w Use TDRs to verify adherence to budget – Typical TDR measurement u Refer to section 7.1.6.2 of the specification for details ConnectorReferenceTime

11. May 17, 200011 EMI w USB1.X EMI solutions don’t work for USB2 – Low pass filters damage signal quality D+ D - Vcc USB A Connector Typical USB 1.1 Termination Scheme

12. May 17, 200012 EMI w Proper grounding of chassis is crucial – Connector shell must connect to green wire ground early and well – IO shield must connect securely to chassis and receptacle w 2 wire common mode choke is preferred – Blocks common mode EMI from leaving chassis – Differential signal rolloff frequency should be high

13. May 17, 200013 ESD, EMC w ESD strikes spread out in time by inductance of cables and hubs in series – Bypass/flyback caps on Vbus near connector help w Hardware Protection – Well-grounded shield – 4 wire common mode choke – Spark gap arrestors – Shielded cables

14. May 17, 200014 DP1 DM1 1.51.551.61.651.71.751.81.851.9 x 10 -5 0 0.5 1 1.5 2 2.5 3 3.5 s V keyboard glitch ESD, EMC w Differential squelch/disconnect w Pattern matching before connectivity w Sampling over extended times e.g. Chirp Noise Immunity Built Into Low-Level Protocol

15. May 17, 200015 Early Testing Results USB2 Validation Motherboard Front Panel Test Chip Back Panel Test Chip

16. May 17, 200016 Routing Paths Tested USB Connector Motherboard PCI SLOT LAN South Bridge NECtest chip Long Route Front Panel Header Early Testing Results Motherboard PCI SLOT LAN PCI SLOT South Bridge USB Connector Short Route NEC test chip

17. May 17, 200017 TP2TP3 Early Testing Results w Back panel eye pattern results – EMI/ESD components – Both at A-connector (TP2) and at end of USB cable (TP3) – Three-stack connector on MB

18. May 17, 200018 Motherboard Front Panel Daughter Card Board Design w Daughtercard at front/side panel – Bypass caps, EMI control components, strain relief w Header and cable – Keyed header, cable of limited length and matched impedance Front/Side Panel Connectors

19. May 17, 200019 18” Shielded, twisted pair 18” ribbon cable Early Testing Results w Front Panel Header Cable Options Tested

20. May 17, 200020 Shielded Front Panel Cable Ribbon Front Panel Cable Early Testing Results w Front-panel cable implementation eye pattern results – 18 inch, twisted pair, shielded front panel cable – 18 inch unshielded front panel “ribbon” cable

21. May 17, 200021 Early Testing Results w Front-panel cable implementation eye pattern results – 18 inch, twisted pair, shielded front panel cable – 18 inch unshielded front panel “ribbon” cable 80  72  Connector reference 110  1.4 ns exception window Shielded, Twisted Pair Front Panel Cable 114  145  114  Ribbon Front Panel Cable Connector reference

22. May 17, 200022 Summary w USB 2.0 design presents new challenges – Board layout – Common mode chokes – Chassis grounding – Signal Quality Measurement – Compliance Testing w USBIF will be providing design guides in such areas