LOGIC DESIGN EENG 210/CS 230/Phys 319 section 02

LOGIC DESIGN EENG 210/CS 230/Phys 319 section 02
Dr. Ihab Talkhan

Group 02 – MW – SPRING 2006 (New Falaki Building, Room 810)
AMERICAN UNIVERSITY IN CAIRO School of Sciences & Engineering EE Department EENG 210/PHYS 319 / CS 230 Introduction to Logic Design Group 02 – MW – SPRING (New Falaki Building, Room 810) Catalog Description: Digital Logic Design, same as CS 230 & Phys 319. The nature of digital logic, numbering system, Boolean algebra, karnaugh maps, decision –making elements, memory elements, latches, flip-flops, design of combinational and sequential circuits, integrated circuits and logic families, shift registers, counters and combinational circuits, adders, substraters ,multiplication and division circuits, memory types. Exposure to logic design automation software. Credit: 3 hours Text book: M. Morris Mano, “ Digital Design” , third edition, Prentice Hall, 2002 References: M. Mano and C. R. Kime , “Logic and Computer Design Fundamentals”, Prentice Hall, 2000. Daniel Gajski, “Principles of Digital Design”, Prentice Hall, 1997. Dr. Ihab Talkhan

Prerequisites: 1) Phys 215 (option)
Coordinator: Prof. Hassanein Amer, Associate Professor, EE Department. Instructor: Dr. Ihab E. Talkhan, Associate Professor, EE Department. This course is designed to introduce the student to the basic techniques of design and analysis of digital circuits Prerequisites: ) Phys 215 (option) 2) CSCI 104 or 106 Dr. Ihab Talkhan

Number Systems, 1’s and 2’s complements 1 Basic Gates 2
Course contents: Assignments Title # All assignments are selected from the main text book end-of chapter problems, problems # will be announced in lectures Number Systems, 1’s and 2’s complements 1 Basic Gates 2 Boolean Algebra 3 Analysis of Combinational Circuits 4 Synthesis of Combinational Circuits using Karnaugh maps 5 NAND/NOR networks, don’t care conditions, duality 6 Design Automation Software (PSPICE A/D) 7 Latches and Flip-Flops 8 Design of clocked sequential circuits using counters as examples 9 Shift registers and different types of counters 10 Multiplexers, demultiplexers, decoders, encoders and parity circuits 11 Arithmetic circuits 12 Semiconductor memories 13 Design of circuits using ROMs and PLAs 14 Introduction to FPGAs , VHDL 15 Dr. Ihab Talkhan

Grading: 60% (best 2 out of 3 tests - no make-ups) 30% Final test
5% Attendance 5% Assignments (selected problems from the text book) Testing dates: to be announced later Final test date: refer to FALL 2005 Schedule Assistant: Eng. Marianne Azer, Office hours: to be announced later (Assistant) Office hours: W 1:30 – 2:30 pm, (Dr. Talkhan) M 1:30 – 2:30 pm room 717 Falaki Academic Center. Dr. Ihab Talkhan

System Flow Diagram Run Implement Design Plan Assess Verify
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Design Cycle Dr. Ihab Talkhan

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The Packaging Sequence
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ASIC Design Flow Dr. Ihab Talkhan

Hardware & Micro-program method
Course Outline Hardware & Micro-program method Dr. Ihab Talkhan

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Z Y X 1 Z Y X 1 Z X 1 Dr. Ihab Talkhan

Important Notes Various binary systems suitable for representing information in digital components [ decimal & Alphanumeric]. Digital system has a property of manipulating discrete elements of information, discrete information is contained in any set that is restricted to a finite number of elements, e.g. 10 decimal digits, the 26 letters of the alphabet, 25 playing cards, and other discrete quantities. Dr. Ihab Talkhan

Important Notes (cont.)
Early digital computers were used mostly for numeric computations, in this case the discrete elements used were the digits, from which the term digital computer has emerged. Discrete elements of information are represented in a digital system by physical quantities called signal [voltages & currents] which have only two discrete values and are said to be binary. Dr. Ihab Talkhan

Electrical Signals [ voltages or currents ] that exist throughout a digital system is in either of two recognizable values [ logic-1 or logic 0 ] Voltage time Logic – 1 range Logic – 0 range Transition , occurs between the two limits Intermediate region, crossed only during state transition 5 0.8 2 Dr. Ihab Talkhan

Digital computers use the binary number system that has two digits “0” and “1”, a binary digit is called a “bit”, thus information is represented in digital computers in groups of bits. By using various coding technique, groups of bits can be made to represent not only binary numbers but also any other group of discrete symbols. To simulate a process in a digital computer, the quantities must be quantized, i.e. a process whose variables are presented by continuous real-time signals needs its signals to be quantized using an analog-to-digital (A/D) conversion device. Dr. Ihab Talkhan

The memory unit: stores programs, inputs, outputs and other intermediate data.
The processor unit: performs arithmetic and other data-processing operations as specified by the program. The control unit: supervises the flow of information between the various units. It also retrieves the instructions, one by one, from the program stored in memory and informs the processor to execute them Dr. Ihab Talkhan

A CPU enclosed in a small integrated circuit package is called a microprocessor. The program and data prepared by the user are transferred into the memory unit by means of an input devices such as a keyboard. An output device, such as a printer, receives the results of the computations and the printed results are presented to the user. Dr. Ihab Talkhan

Least significant digit Most significant digit
Numbering Systems A number is base “r” contains r digits 0,1,2,…..(r-1) and is expressed with a power series in “r”. A number can also be expressed by a string of coefficients [positional notation]. Least significant digit Most significant digit Radix point Dr. Ihab Talkhan

Numbering Systems (cont.)
The Ai coefficients contain “r” digits, and the subscript “ i ” gives the position of the coefficient, hence the weight ri by which the coefficient must be multiplied. To distinguish between numbers of different bases, we enclose the coefficients in parentheses and place a subscript after the right parenthesis to indicate the base of the number. Dr. Ihab Talkhan

Decimal Numbers The decimal number system is of base or radix r = 10, because the coefficients are multiplied by powers of 10 and the system uses ten distinct digits [0,1,2,…9]. Decimal number is represented by a string of digits, each digit position has an associated value of an integer raised to the power of 10. Consider the number (724.5)10 Dr. Ihab Talkhan

Conversion from Any numbering System to Decimal System
To convert any numbering system to decimal, you expand the number to a power series with its base. Example: Convert (312)5 to its equivalent decimal, note that the number is in base 5. Conversion from base 5 number to its equivalent decimal number Radix 5 Dr. Ihab Talkhan

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Binary Numbers Converting a Binary number to its equivalent Decimal:
( )2 Note that, when a bit is equal to “0”, it does not contribute to the sum during the conversion. Therefore, the conversion to decimal can be obtained by adding the numbers with powers of two corresponding to the bits that are equal to “1’. Dr. Ihab Talkhan

Computer Units 210 = 1024 is referred to as Kilo “K”
220 = 1,048,567 is referred to as Mega “M” 230 is referred to as Giga “G” Example: 16M = 224 = 16,777,216 Dr. Ihab Talkhan

Conversion from Decimal to Binary (Integer numbers only)
The conversion of a decimal number to binary is achieved by a method that successively subtracts powers of two from the decimal number, i.e. it is required to find the greatest number (power of two) that can be subtracted from the decimal number and produce a positive difference and repeating the same procedure on the obtained number till the difference is zero. Dr. Ihab Talkhan

Example Find the binary equivalent of (625)10 625 – 512 = 113 512 = 29
625 – 512 = = 29 113 – 64 = = 26 49 – 32 = = 25 17 – 16 = = 24 1 – = = 20 (625)10 = = ( ) MSB LSB Position 10 Dr. Ihab Talkhan

General Method If the number includes a radix point, it is necessary to separate it into an integer part and a fraction part, since each part must be converted differently. The conversion of a decimal integer to a number in base “r“ is done by dividing the number and all successive quotients by “ r “ and accumulating the remainders. The conversion of a decimal fraction to base “ r “ is accomplished by a method similar to that used for integer, except that multiplication by “ r “ is used instead of division, and integers are accumulated instead of remainders. Dr. Ihab Talkhan

Example Find the binary equivalent of (41.6875)10 Integer Part:
Separate the number into an integer part & a fraction part. Integer Part: Fraction Part: remainder Integer LSB MSB = 1 = 0 41 20 + ½ 10 5 2 + ½ 1 0 + ½ 2  1  0 x 2 = x 2 = x 2 = x 2 = LSB MSB ( .6875)10 = ( .1011)2 Thus: ( )10 = ( )2 (41)10 = (101001)2 Dr. Ihab Talkhan

Important Note The process of multiplying fractions by “ r “ does not necessarily end with zero, so we must stop at a certain accuracy , i.e. number of fraction digits, otherwise this process might go forever. Dr. Ihab Talkhan

Octal Numbers Octal number system is a base 8 system with eight digits [ 0,1,2,3,4,5,6,7 ]. To find the equivalent decimal value, we expand the number in a power series with a base of “ 8 ”. Example: (127.4)8 = 1 x x x x 8-1 = (87.5)10 Dr. Ihab Talkhan

Hexadecimal Numbers The Hexadecimal number system is a base 16 system with the first ten digits borrowed from the decimal system and the letters A,B,C,D,E,F are used for digits 10,11,12,13,14 and 15 respectively. To find the equivalent decimal value, we expand the number in a power series with a base of “ 16 ”. Example: (B65F)16 = 11 x x x x 160 = (46687)10 Dr. Ihab Talkhan

Note It is customary to borrow the needed “ r “ digits for the coefficients from the decimal system, when the base of the numbering system is less than 10. The letters of the alphabet are used to supplement the digits when the base of the number is greater than 10. Dr. Ihab Talkhan

Hexadecimal Octal Binary Decimal
1 2 3 4 5 6 7 8 9 A B C D E F 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 08 09 Dr. Ihab Talkhan

Important Property The Octal & Hexadecimal systems are useful for representing binary quantities indirectly because they posses the property that their bases are powers of “2”. Octal base = 8 = 23 & Hexadecimal base = 16 = 24, from which we conclude: Each Octal digit correspond to three binary digits Each Hexadecimal digit correspond to four binary digits. Dr. Ihab Talkhan

Conversion from Binary to Octal/Hexadecimal
The conversion from Binary to either Octal or Hexadecimal is accomplished by partitioning the Binary number into groups of three or four digits each respectively, starting from the binary point and proceeding to the left and to the right. Then, the corresponding Octal or Hexadecimal is assigned to each group. Note that, 0’s can be freely added to the left or right to the Binary number to make the total number of bits a multiple of three or four. Dr. Ihab Talkhan

Example Find the Octal equivalent of the Binary number:
( )2 ( )2 ≡ ( )8 Added “0’s” Dr. Ihab Talkhan

Example Find the Hexadecimal equivalent of the Binary number:
( )2 C B F ( )2 ≡ (2C6B.F06)16 Added “0’s” Dr. Ihab Talkhan

Conversion from Octal/Hexadecimal to Binary
Conversion from Octal or Hexadecimal to Binary is done by a procedure reverse to the previous one. Each Octal digit is converted to a three-digit binary equivalent. Each Hexadecimal digit is converted to its four-digit binary equivalent. Dr. Ihab Talkhan

Example Find the Binary equivalent of (673.12)8 6 7 3 . 1 2
(673.12)8 = ( )2 Dr. Ihab Talkhan

Example Find the Binary equivalent of (3A6.C)16 3 A 6 . C
(3A6.C)16 = ( )2 Dr. Ihab Talkhan

Important Note The Octal or Hexadecimal equivalent representation is more convenient because the number can be expressed more compactly with a third or fourth of the number of digits. Dr. Ihab Talkhan

Arithmetic 1 + 1 = 10 Binary 1 + 1 = 1 Carry Two digits Gates link
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Arithmetic Operations
Arithmetic operations with numbers in base “ r “ follow the same rules as for decimal numbers Addition Subtraction 1 Augend + Addend Sum 2 1 Minuend - Subtrahend Result Dr. Ihab Talkhan

Arithmetic Operations (cont.)
Multiplication Division divisor dividend 1 Multiplicand x Multiplier Product 1 1110 1101 subtract remainder Dr. Ihab Talkhan

Notes The rules for subtraction are the same as in decimal, except that a borrow from a given column adds “2” to the minuend digit. In division, we have only two choices for the greatest multiple of the divisor Zero and the divisor itself. Dr. Ihab Talkhan

Arithmetic Operations with Base “r” Systems
Arithmetic operations with Octal , Hexadecimal or any other base “r” system is done by using the following methods: Formulation of tables from which one obtains sums and products of two digits in base “r”. Converting each pair of digits in a column to decimal , add the digits in decimal, and then convert the result to the corresponding sum and carry in base “r” system. Dr. Ihab Talkhan

Example Add : (59F)16 + (E46)16 Hexadecimal Equivalent Decimal F 9 5 6
3 1 1 15 9 5 6 4 14 + 21 19 Carry 1 =16+5 =16+3 Dr. Ihab Talkhan

Note The idea is to add F+6 in hexadecimal, by adding the equivalent decimals 15+6 = 21, then converting (21)10 back to hexadecimal knowing that; 21 = 16+5  gives a sum digit of 5 and a carry “1” to the next higher order column digit Dr. Ihab Talkhan

Multiplication The multiplication of two base “r” numbers is done by performing all arithmetic operations in decimal and converting intermediate results one at a time. Dr. Ihab Talkhan

Example Multiply (762)8 x (45)8 carry Octal Decimal 12 10=8+2 5 x 2
37 31=24+7 5 x 6 +1 45 46 38=32+6 5 x 7 + 3 4672 10 8=8+0 4 x 2 3710 31 25=24+1 4 x 6 +1 43772 4 x 7 + 3 Dr. Ihab Talkhan

Complements Complements are used to simplify the subtraction operation and for logical manipulation. Given n-digit number N in base r, its r’s complement is; Given n-digit number N in base r, its r’s complement is; Dr. Ihab Talkhan

Important Notes The r’s complement is obtained by adding “1” to the (r-1)’s complement. r’s complement of N can be formed by leaving all least significant 0’s unchanged, then subtracting the first nonzero least significant digit from “r”, and subtracting all higher significant digits from (r-1). (r-1)’s complement of N can be formed by subtracting each digit from (r-1). Dr. Ihab Talkhan

Examples 10’s complement of : 246700  753300
10’s complement of :  9’s complement of :  (106-1) 10n La single 1 followed by n 0’sa single 1 followed by n 0’s 10n – 1 La number represented by n 9’s Dr. Ihab Talkhan

Binary 1’s & 2’s Complements
Note that ; 2n = a binary number which consists of a “1” followed by n 0’s. 2n – 1= a binary number represented by n 1’s. 2’s complement is formed by leaving all least significant 0’s and the first “1” unchanged, then replacing 1’s with 0’s and 0’s by 1’s in all other higher significant bits. 1’s complement is obtained by changing 1’s to 0’s and 0’s to 1’s. Dr. Ihab Talkhan

Note The (r-1)’s complement of Octal or Hexadecimal numbers is obtained by subtracting each digit from 7 or f (15) respectively. If the number contains a radix point, then the point should be removed temporarily in order to form the r’s or (r-1)’s complement. The radix point is then restored to the complemented number in the same relative position. The complement of the complement restores the number to its original value. Dr. Ihab Talkhan

Subtraction with Complements
The subtraction method that is based or uses the borrow concept is less efficient than the method that uses complements, when subtraction is implemented with digital hardware. The subtraction of two n-digit unsigned numbers, M-N in base “r” is done as follows: Add the minuend M to the r’s complement of the subtrahend N; M + (rn – N) = M- N + rn If M≥N, the sum will produce an end carry rn, which is discarded, what is left is the result “ M-N “. If M < N, the sum does not produce an end carry and is equal to rn – (N-M) which is the r’s complement of (N-M). to obtain the answer in a familiar form, take the r’s complement of the sum and place a negative sign in front. Dr. Ihab Talkhan

Example (using 10’s complement)
Consider the two numbers & 3250, it is required to apply the rules for subtraction with complements with these two numbers, thus we have two cases: Case # 1: M = & N = 3250, required M-N. In this case M > N Note that M has 5-digits and N has only 4-digits, rule number 1: both numbers must have the same number of digits. Note also,, the occurrence of the end carry signifies that M > N and the result is positive. Dr. Ihab Talkhan

M – N = 72532 – 03250 72532 72532 -03250  + 96750 10’s Complement
 ’s Complement sum 69282 is the required answer Discard the end carry Dr. Ihab Talkhan

Example (using 10’s complement)
Case # 2: M = & N = 72532, required M-N. In this case M < N Note that M has 5-digits and N has only 4-digits, rule number 1: both numbers must have the same number of digits. Note also,, the absence of the end carry signifies that M < N and the result is negative. Dr. Ihab Talkhan

The required answer = - ( 10’s complement of 30718) = - 69282
M – N =  ’s Complement 30718 sum The required answer = - ( 10’s complement of 30718) = no carry Dr. Ihab Talkhan

Notes When subtracting with complements, the negative answer is recognized by the absence of the end carry and the complemented result. Dr. Ihab Talkhan

Subtracting with (r-1)’s Complements
The (r-1)’s complement can be used when subtracting two unsigned numbers as the (r-1)’s complement is one less than the r’s complement. Thus the result of adding the minuend to the complement of the subtrahend produces a sum which is one less than the correct difference when an end carry occurs. Removing the end-carry and adding one to the sum is referred to as an end-around carry. Dr. Ihab Talkhan

1’s Complement Example: X – Y = 1010100 – 1000011 1010100 1010100
’s Complement sum 1 End-around carry answer (X-Y) Dr. Ihab Talkhan

1’s Complement (cont.) Example (cont.): Y – X = 1000011 – 1010100
’s Complement sum Note that, there is no carry in this case Answer = Y – X = - ( 1’s complement of ) = Dr. Ihab Talkhan

Signed Binary Number Positive integers including zero can be represented as unsigned numbers. Because of hardware limitations, computers must represent everything with 1’s & 0’s, including the sign of a number. The sign is represented with a bit, placed in the left-most position of the number, where: 0 = positive sign & 1 = negative sign Dr. Ihab Talkhan

Binary number The left most bit represents the sign and the rest of the bits represent the number The left most bit is the most significant bit of the number X = 0 +ve X = 1 -ve The left most bit X Dr. Ihab Talkhan

Signed & Unsigned numbers
01001 Unsigned Signed Signed-magnitude System 11001 Unsigned Signed Dr. Ihab Talkhan

In computers, a signed-complement system is used to represent a negative number, i.e. negative number is represented by its complement. 8-bit representation Signed-magnitude representation - 9 Signed-1’s complement representation Signed-2’s complement representation Dr. Ihab Talkhan

The addition of two signed numbers, with negative numbers represented in signed 2’s complement form, is obtained from the addition of the two numbers including their sign bits. A carry out of the sign bit position is discarded. Note that the negative numbers must be initially in 2’s complement and the sum obtained after the addition, if negative, is in 2’s complement form. Dr. Ihab Talkhan

We must ensure that the result has sufficient number of bits to accommodate the sum, if we start with two n-bit numbers and the sum occupies n+1 bits, we say that an overflow occurs. 2’s complement Dr. Ihab Talkhan

Note that binary numbers in the signed-complemented system are added and subtracted by the same basic addition and subtraction rules as unsigned numbers, therefore, computers need only one common hardware circuit to handle both types of arithmetic. The user / programmer must interpret the results to distinguish between signed and unsigned numbers Dr. Ihab Talkhan

Decimal Codes The binary code is a group (string) of n bits that assume up to distinct combinations of 1’s and 0’s, with each combination representing one element of the set that is being coded, the bit combination of an n-bit code is determined from the count in binary from 0 to Each element must be assigned a unique binary combination and no two elements can have the same value Dr. Ihab Talkhan

Binary Coded Decimal “BCD”
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1 2 3 4 5 6 7 8 9 Dr. Ihab Talkhan

Note , a number with “n” decimal digit will require “4n” bits in BCD.
Note also, a decimal number in BCD is the same as its equivalent binary number, only when the number is between 0 – 9. A BCD number > 10 looks different from its equivalent binary number. The binary combinations 1010 – 1111 are not used and have no meaning in the BCD. Dr. Ihab Talkhan

12 bit 8 bit It is important to realize that BCD numbers are decimal numbers and not binary numbers. Dr. Ihab Talkhan

BCD Addition Each digit in a BCD does not exceed 9, the sum can not be greater than = 19, where the “1” being a carry. The binary sum will produce a result in the range from 0 to 19, in binary it correspond to 0000 – 10011, but in BCD 0000 – , thus when the binary sum is equal to or less (without a carry) the corresponding BCD is correct. Dr. Ihab Talkhan

BCD Addition (cont.) When the binary sum is , the result is an invalid BCD digit. To correct this problem, add binary 6 (0110) to the sum, which converts the sum to a correct BCD digit and produces a carry as required. The value 6 corresponds to the 6 invalid combinations in the BCD code (1010 – 1111). Dr. Ihab Talkhan

Examples 8 1000 0110 1 0111 4 0100 0110 1 0010 Add 6 Sum greater than 9 Sum greater than 16 carry Dr. Ihab Talkhan

Example (2) BCD carry Binary sum add 6 BCD sum Dr. Ihab Talkhan

BCD Multiplication 1 Multiply 15 x 16 in BCD 15 5 x 6 = 30 L 0011 0000
x x = L 1001 x = L 0101 x = L 0001 0110 1 Dr. Ihab Talkhan

For signed decimal numbers, the sign is represented with “Four” bits to conform with the 4-bit code of the decimal digits, where: -ve sign = (9) +ve sign = (0) Many computers have special hardware to perform arithmetic calculations directly with decimal numbers in BCD. Dr. Ihab Talkhan

Other Decimal Codes Binary codes for decimal digits require a minimum 4-bits per digit. BCD Repeated code Excess-3 code Negative code Weighted codes Always add 3 (0011) to the original binary number, e.g and so on Note, some digits can be coded in two possible ways Dr. Ihab Talkhan

Other Decimal Codes (cont.)
The 2421 & Excess-3 codes are self-complementing codes, i.e. the 9’s complement of a decimal number is obtained directly by changing 1’s to 0’s and 0’s to 1’s. BCD is not a self-complementing code The accepts positive & negative weights. Dr. Ihab Talkhan

Notes You should distinguish between conversion of a decimal number to binary and the binary coding of a decimal number. It is important to realize that a string of bits in a computer sometimes represents a binary number and at other times it represents information as specified by a given binary code. Dr. Ihab Talkhan

Alphanumeric Codes ASCII = American Standard Code for
Information Interchange ASCII consists of 7-bits to code 128 characters 26 upper-case letters [ A,B,C,…] 26 lower-case letters [a,b,c,….] 10 decimal numbers [ 0- 9] 32 special printable characters [ #,$,%,&,*,…..] 34 control characters (non-printing C/Cs) 128 characters Dr. Ihab Talkhan

Note that, binary codes merely change the symbols not the meaning of the element of information.
The 34 control characters are used for routing data and arranging the printed text into the prescribed format Dr. Ihab Talkhan

The 34 control Characters
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Parity bit ASCII code was modified to 8-bits instead of 7-bits. (ASCII is 1 byte in length) 1 byte = 8 bits The extra bit, whose position is in the most significant bit [ default is “0”] , is used for: Providing additional symbols such as the Greek Alphabet or italic type format……etc Indicating the parity of the character when used for data communication. Dr. Ihab Talkhan

Parity bit (cont.) The parity bit is an extra bit included to make the total number of 1’s in a row either even or odd. The bit is helpful in detecting errors during the transmission of information from one location to another. 1 Even parity Dr. Ihab Talkhan

Other Alphanumeric Codes
EBCDIC = Extended BCD Interchange Code, used in IBM. It is 8-bits for each character and a 9th bit for parity. Dr. Ihab Talkhan

You can Solve from the text Book
Chapter 1 Problems , page 30 Chapter 2 Problems 2-1 – 2-23 , page 61 Need to submit within two weeks (i.e. due date is 3 October , 2005) Chapter 1 – odd problems Chapter 2 – even problems Dr. Ihab Talkhan

Binary Logic Digital circuits are hardware components that manipulate binary information. Gates are circuits that are constructed with electronics components [ transistors, diodes, and resistors] Boolean algebra is a binary logic system which is a mathematical notation that specifies the operation of a gate [ Boolean => the English mathematician “George Boole” 1854 ] Dr. Ihab Talkhan

Electrical Signals [ voltages or currents ] that exist throughout a digital system is in either of two recognizable values [ logic-1 or logic 0 ] Voltage time Logic – 1 range Logic – 0 range Transition , occurs between the two limits Intermediate region, crossed only during state transition 5 0.8 2 Dr. Ihab Talkhan

You should distinguish between binary logic and binary arithmetic
You should distinguish between binary logic and binary arithmetic. Arithmetic variables are numbers that consist of many digits. A logic variable is always either 1 or 0. A Truth Table is a table of combinations of the binary variables showing the relationship between the values that the variables take and the result of the operation. The number of rows in the Truth Table is , n = number of variables in the function. The binary combinations are obtained from the binary number by counting from 0 to Dr. Ihab Talkhan

Arithmetic 1 + 1 = 10 Binary 1 + 1 = 1 Carry Two digits
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AND and OR gates may have more than two inputs.
Timing diagrams illustrate the response of any gate to all possible input signal combinations. The horizontal axis of the timing diagram represents time and th vertical axis represents the signal as it changes between the two possible voltage levels Dr. Ihab Talkhan

Timing Diagram Dr. Ihab Talkhan

Logic Function Definition
Language description Function description Boolean Equation Graphic Symbols Truth Table Timing Diagram VHDL code (hardware language) Dr. Ihab Talkhan

Gates Link Z = X . Y Z = X + Y Z Y X 1 Z Y X 1 Z Y X 1 Z Y X 1
Z Y X 1 Z Y X 1 Z Y X 1 Z = X . Y Z = X + Y Dr. Ihab Talkhan

Building the Basic Functions from Other gates
NOT (inverter) Using NAND Gates Basic Function Using NOR Gates B AB AND A+B OR Dr. Ihab Talkhan

Boolean Algebra It is an algebra that deals with binary variables and logic operations: A Boolean function consists of: An algebraic expression formed with binary variables. The constants “0” and “1” The logic operation symbol ( . , +, NOT) Parentheses and an equal sign Dr. Ihab Talkhan

Example Given a logic function “F”, defined as follows: 0 otherwise
F = if X = 1 or if both Y & Z are equal to 1 0 otherwise The logic equation that represents the above function is given by: Dr. Ihab Talkhan

The truth table for the given function is as shown.
Z Y X 1 The truth table for the given function is as shown. The Boolean function can be transformed from an algebraic expression into a circuit diagram composed of logic gates. Dr. Ihab Talkhan

Note : the number of inputs equal the number of variables
Logic Circuit Diagram OR AND output Complement = need an inverter X Y Z Note : the number of inputs equal the number of variables Dr. Ihab Talkhan

Notes There is only one way to represent a Boolean function in a Truth Table, where there are a variety of ways to represent the function when it is in algebraic form. By manipulating a Boolean expression according to Boolean Algebra rules, it is sometimes possible to obtain a simpler expression for the same function, thus reducing the number of gates in the circuit. Dr. Ihab Talkhan

Basic Identities of Boolean Algebra
description X . 1 = X X . 0 = 0 X . X = X X . X = 0 XY = YX X(YZ) = (XY)Z X+YZ=(X+Y)(X+Z) X + 0 =X X + 1 = 1 X + X = X X + X = 1 X = X X + Y = Y +X X+(Y+Z) = (X+Y)+Z X(Y+Z) = XY + XZ Commutative Associative Distributive DeMorgan Duality Dr. Ihab Talkhan

Duality The dual of an algebraic expression is obtained by interchanging OR and AND operations and replacing 1’s by 0’s and 0’s by 1’s. Notice that when evaluating an expression, the complement over a single variable is evaluated first , then the AND operation and the OR operation. ( ) NOT AND OR Dr. Ihab Talkhan

Extension of DeMorgan’s Theorem
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Algebraic Manipulation
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The Consensus Theorem Which Shows that the term YZ is redundant and can be eliminated Proof: Dr. Ihab Talkhan

The Dual of Consensus Theorem
Notice that, two terms are associated with one variable and its complement and the redundant term is the one which not contain the same variable. Dr. Ihab Talkhan

Complement of a Function “F”
The complement of a function “F” is obtained by interchanging 1’s to 0’s and 0’s to 1’s in the values of “F” in the Truth Table. OR, it can be derived algebraically by applying DeMorgan’s Theorem. The complement of an expression is obtained by interchanging AND and OR operations and complementing each variable. Dr. Ihab Talkhan

Example Or by taking the dual of the expression:
The original function The dual of F Complement each literal The complement of a function is done by taking the dual of the function and complement each literal. Dr. Ihab Talkhan

Standard Forms A product term in which all the variables appear exactly once either complemented or uncomplemented is called a “minterm”, note that there are distinct “minterm” for n-variables. AND operation among several variables 0 = complemented variable 1 = uncomplemented variable OR operation among several variables 1 = complemented variable 0 = uncomplemented variable Dr. Ihab Talkhan

An algebraic expression representing the function is derived from the Truth Table by finding the logical sun of all product terms for which the function assumes the binary value of “1”. A symbol for each minterm , where “j” denotes the decimal equivalent of the binary number of the minterm. A sum term that contain all the variables in complemented or uncomplemented form is called “maxterm”, symbol Note that Dr. Ihab Talkhan

Example Dr. Ihab Talkhan

Example Sum of Product SOP Product of Sum POS
Note that the decimal numbers included in the product of maxterms will always be the same as the minterm list of the complement function Dr. Ihab Talkhan

Properties of minterm There are minterm for n-Boolean variables which can be evaluated from the binary numbers 0 to Any Boolean function can be expressed as a logical sum of minterms. The complement of a function contains those minterms not included in the original function A function that includes all minterms is equal to logic-1. Dr. Ihab Talkhan

AND gates followed by OR gate forms a circuit configuration that is referred to as a Two-Level implementation (SOP). Two-Level implementation is preferred as it produces the least amount of delay time through the system. Delay is defined as the time that a signal spends to propagate from input to output. Also, Product of Sum (POS) is a two-level implementation, as it consists of a group of OR gates followed by an AND gate. Dr. Ihab Talkhan

Karnaugh map (k-map) Each square corresponds to a row of the Truth-Table and to one minterm of the algebraic equation. Only one digit changing value between two adjacent rows and columns. One square represent one minterm, giving a term of four variables (in case of 4-varaiable map). Two adjacent squares represent a term of three literals Four adjacent squares represent a term of two literals. Eight adjacent squares represent a term of one literal. Sixteen adjacent squares represent F=1. When a variable appears within a group in both inverted and non-inverted state, then the variable can be eliminated. Dr. Ihab Talkhan

K-map Procedure Fill the map from the Truth-Table.
Look at 1’s (where F=1). Make the biggest group possible: Any square can appear in more than one group. Get expression for each group. OR all expressions. Squares in a group = , n=0,1,2,… Adjacent cells Cover all 1’s Dr. Ihab Talkhan

One digit change value at a time
CD AB Cell POS SOP Dr. Ihab Talkhan

Note that there are cases where two squares in the map are considered to be adjacent,, even though they do not touch each other. YZ X Dr. Ihab Talkhan

Example CD AB 1 Dr. Ihab Talkhan

Example 2 CD AB 1 1 1 1 1 1 1 Dr. Ihab Talkhan

Prime Implicant A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map. If a minterm in a square is covered by only one prime implicant , that prime implicant is said to be essential. Dr. Ihab Talkhan

YZ X 1 1 1 1 1 Dr. Ihab Talkhan

Example 1 1 CD AB Non-essential prime implicant
essential prime implicants Dr. Ihab Talkhan

Note that, once the essential prime implicants are taken, the third term is not needed (redundant), as all the minterms are already covered by the essential prime implicants, thus: Dr. Ihab Talkhan

Example 2 CD AB 1 1 1 1 1 1 1 Non-essential or Dr. Ihab Talkhan

Complement of a Function
The complement of a function is represented in the K-map by the squares (cells) not marked by 1’s. Dr. Ihab Talkhan

Product of Sums (POS) To represent any function as a product of sums (POS), we take the dual of and complementing each literal, i.e. we get: Dr. Ihab Talkhan

Example CD AB 1 1 1 1 1 1 1 Dr. Ihab Talkhan

Don’t Care Terms There are applications where the function is not specified for certain combinations of variables, e.g. the four-bit binary code (BCD code) where there are six combinations from 10 – 15 which are not used and consequently are considered as unspecified. These unspecified minterms are called “don’t care” terms and can be used on a map to provide further simplification of the function by considering it as 1’s or 0’s (depending on the situation). Don’t care terms are represented by a cross “X” in the map. Dr. Ihab Talkhan

Example CD AB X 1 1 X X 1 1 1 Algebraically these two functions are not equal , as both covers different don’t care minterms, but the original function is satisfied as don’t care terms will not affect the original function Dr. Ihab Talkhan

Example It is required to build a car alarm system where the alarm is activated when: Any door is open The lights are on and the key is out of ignition The seat belts are not fastened and key is in ignition The key is still in ignition and the car door is open Dr. Ihab Talkhan

Assumptions Assume that:
X ≡ Car door , where “0” = door is closed & “1” = door is open Y ≡ Lights , where “0” = light is off & “1” = light is on Z ≡ Seat belt . where “0” = seat belt is fastened & “1” = seat belt is no fastened W ≡ Key , where “0” = key in ignition & “1” = key out of ignition Dr. Ihab Talkhan

F W Z Y X Dec. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Dr. Ihab Talkhan

ZW XY 1 1 1 1 1 1 1 1 1 1 1 1 Dr. Ihab Talkhan

X Y F Z W Dr. Ihab Talkhan

K-map with more than 4-variables
Five-variable map needs 32-cell Six-variable map needs 64-cell & so on. In general, maps with six or more variables needs too many cells and they are impractical to be analyzed manually, there special program (simulation programs) that can handle such situation. Dr. Ihab Talkhan

5-variables Map We use two four-variables maps, the first one has a the variable A=0 as a common factor, and the second has a common factor A=1. Each cell in the A=0 map is adjacent to the corresponding cell in the A=1 map, e.g. Any adjacent cells , k=0,1,2,3,4, in the 5-variable map represents a product term of 5-k literals. Dr. Ihab Talkhan

5-variables map DE BC A=0 A=1 Dr. Ihab Talkhan

Example DE DE BC BC 1 1 1 1 1 1 1 1 1 1 1 common A=1 A=0
Dr. Ihab Talkhan

You can Solve from the text Book
Chapter 3 Problems 3-1 – 3-30 , page 106 Need to submit within two weeks (i.e. due date is, ) Chapter 3 - all Dr. Ihab Talkhan

Two Graphic Symbols for a NAND gate
NAND and NOR gates are more popular than AND and OR gates, as they are easily constructed with electronic circuits and Boolean functions can be easily implemented with them. X Y AND-invert Invert-OR Two Graphic Symbols for a NAND gate Dr. Ihab Talkhan

Two Graphic Symbols for a NOR gate
X Y OR-invert invert-AND Two Graphic Symbols for a NOR gate Dr. Ihab Talkhan

Mixed notation, both AND-invert & invert-OR are present
The implementation of Boolean functions with NAND gates requires that the function be in the SOP form. Double inversion Mixed notation, both AND-invert & invert-OR are present AND & OR gates NAND gates Dr. Ihab Talkhan

Example 1 1 1 1 1 1 Note that Z must have a one-input NAND gate to compensate for the small circle in the second level gate Dr. Ihab Talkhan

Steps to Configure SOP with NAND gates
Simplify the function (SOP) Draw a NAND gate for each product term and the inputs to each NAND gate are the literals of the product term. (group of the first-level gates) Draw a single gate using AND-invert or invert-OR graphic symbol in the second level. A term with a single literal requires an inverter in the first level. Dr. Ihab Talkhan

Another Rule for converting AND/OR into NAND
Convert all AND/OR using AND-invert/invert-OR. Check all the small circles in the diagram. For every small circle that is not counteracted by anther small circle along the same line, insert an inverter (one-input NAND gate) or complement the input variable. Dr. Ihab Talkhan

XNOR is equal to “1” if both X & Y are equal to “1” or both are equal to “0”
Z Y X 1 Z Y X 1 Dr. Ihab Talkhan

XOR/XNOR identities Dr. Ihab Talkhan

Parity Generation & Checking
It used for error detection. The circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that checks the parity in the receiver is called a parity checker. Dr. Ihab Talkhan

Even parity generator/checker
Parity Checker Dr. Ihab Talkhan

Transmission Gates This gate is available with CMOS type electronic circuits. TG X & Y are inputs C & are control inputs Open Switch Pass signal Dr. Ihab Talkhan

Using Transmission gates to construct An Exclusive-OR gate (XOR)
TG1 TG2 Z TG2 TG1 Y X 1 Open Close Dr. Ihab Talkhan

Integrated Circuits It is a small silicon semiconductor crystal, called a chip, containing the electronic components for the digital gates. Number of pins may range from 14 in a small OC package to 64 or more in a large package. Dr. Ihab Talkhan

Inputs & outputs are connected directly to the pins 10 -100 gates
No. of gates < 10 Inputs & outputs are connected directly to the pins gates Decoder Adders Registers 100 – few thousands gates Processors Memory chips Programmable modules Dr. Ihab Talkhan

Logic Circuits Technology
Basic circuits in each technology is a NAND, NOR or an inverter. Diodes/transistors Power supply 5 V Two logic levels [0V V] Standard High speed operation Super computers Signal processors High component density Simple processing technique during fabrication Low power consumption Dr. Ihab Talkhan

Notes There are many type of the TTL family
High-speed TTL Low-power TTL Schottky TTL Low-power Schottky TTL Advanced Low-power Shcottky TTL ECL gates operates in a nano-saturated state, a condition that allows the achievement of propagation delays of 1-2 nanoseconds. Dr. Ihab Talkhan

Important Parameters that are evaluated and compared
Fan-out Power-dissipation Propagation delay Noise margin Dr. Ihab Talkhan

Fan-out It specifies the number of standard loads that the output of a typical gate can drive without impairing its normal operation. A standard load is usually defined as the amount of current needed by an input of another similar gate of the same family. Dr. Ihab Talkhan

Power Dissipation It is the power consumed by the gate which must be available from the power supply. Dr. Ihab Talkhan

Propagation Delay It is the average transition delay time for the signal to propagate from input to output when the binary changes in value. The operating speed is inversely proportional to the propagation delay. Dr. Ihab Talkhan

Noise Margin It is the maximum external noise voltage that causes an undesirable change in the circuit output. Dr. Ihab Talkhan

Positive & Negative Logic
Choosing the high-level “H” to represent logic “1” defines a positive logic system. Choosing the low-level “L” to represent logic “1” defines a negative logic system. Logic value Signal value Logic value Signal value Positive logic Negative logic Dr. Ihab Talkhan

Notes The signal values “H” & “L” are usually used in the components data sheets The actual truth table is defined according to the definition of “H” and “L” in the data sheet. Dr. Ihab Talkhan

Depending on the definition of H & L in the data sheet
X Z Y X L H TTL Gate Z Data Sheet Y Depending on the definition of H & L in the data sheet Z Y X 1 Z Y X 1 X X Z Z Y Y These small triangle in the inputs & output designate a polarity indicator Dr. Ihab Talkhan

Logic Circuits Consists of logic gates whose outputs at any time are determined directly from the values of the present inputs. No feedback or storage elements are involved. It involves storage elements (Flip-Flops). Outputs are a function of inputs and the state of the storage elements, where the state of the storage elements is a function of the previous inputs. Circuit behavior must be specified by a time sequence of inputs and internal states. Dr. Ihab Talkhan

Logic Circuits Dr. Ihab Talkhan

Outputs = f( external inputs , present states)
A sequential circuit is specified by a time sequence of inputs, outputs and internal states. It contain memory and thus can remember the changes of input signals that occurred in the past. Inputs for the sequential circuit are functions of external inputs and the present state of the storage elements. Both external inputs and the present states determine the binary value of the outputs and the condition for changing the state of the storage state. Outputs = f( external inputs , present states) Next state = f( external inputs , present states) Dr. Ihab Talkhan

Analysis Procedure To obtain the output Boolean functions from a logic diagram: Label all gate outputs that are a function of input variables with arbitrary symbols. Determine the Boolean functions for each gate. Label the gates that are a function of input variables and previous labeled gates with different arbitrary symbols. Find the Boolean functions for these gates. Repeat step 2 until the outputs of the circuit are obtained in terms of the input variables. Dr. Ihab Talkhan

Thus the Boolean functions of F1 and F2 are:
Dr. Ihab Talkhan

Another Way using the Truth Table
Determine the number of input variables in the circuit for n-inputs, list the binary number from 0 to 2n-1 in a table. Label the outputs of the selected gates with arbitrary symbols. Obtain the Truth Table for the outputs of those gates that are a function of the input variables only. Proceed to obtain the Truth Table for the outputs of those gates that are a function of previously defined values until the columns for all outputs are determined. Dr. Ihab Talkhan

F2 F1 T5 T4 T3 T2 T1 D C B A 1 Dr. Ihab Talkhan

Design Procedure Form the specifications of the circuit, determine the required number of inputs and outputs and assign a letter (symbol) to each. Derive the Truth Table that defines the required relationship between inputs and outputs. Obtain the simplified Boolean functions for each output as a function of the input variables. Draw the logic diagram. Dr. Ihab Talkhan

Need to Accomplish Minimum number of gates
Minimum number of inputs to a gate Minimum propagation delay of the signal through the gates Minimum number of interconnections Dr. Ihab Talkhan

Example Design a combinational circuit with three inputs and one output. The output must equal “1” when the inputs are less than three and “0” otherwise. [use only NAND gates] F Z Y X 1 2 3 4 5 6 7 Dr. Ihab Talkhan

Mixed-symbol notation
YZ X 1 Mixed-symbol notation Dr. Ihab Talkhan

Note When a combinational circuit has two or more outputs, each output must be expressed separately as a function of all the input variables. Dr. Ihab Talkhan

Code Converter Example
Excess-3 code BCD code Decimal Digit Z Y X W D C B A 1 2 3 4 5 6 7 8 9 Dr. Ihab Talkhan

CD AB 10 11 01 00 1 X CD AB 10 11 01 00 1 X Dr. Ihab Talkhan

Logic Diagram of BCD to Excess-3 code Converter
Dr. Ihab Talkhan

BCD to Seven-Segment Decoder
Digital read-out found in electronic caculators and digital watches use display devices such as light emitting diodes LED or liquid crystal display LCD, each digit of the display is formed from seven segments. Each consists of one LED or one crystal which can be illuminated by digital signals. Dr. Ihab Talkhan

All other input combinations
g f e d c b a D C B A 1 2 3 4 5 6 7 8 9 Not valid (don’t care) All other input combinations 10 11 12 13 14 15 7-outputs a b c g d f e Dr. Ihab Talkhan

We cannot use the don’t care condition here for the six binary combinations – 1111, as the design will most likely produce some arbitrary and meaningless display of the unused combinations. 14 AND gate and 7 OR Dr. Ihab Talkhan

Arithmetic Circuits An arithmetic circuit is a combinational circuit that performs arithmetic operations such as addition, subtraction, multiplication and division with binary numbers or with decimal numbers in a binary code. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10 A combinational circuit that performs the addition of two bits is called a “Half Adder”. Carry is added to the next higher order pair of significant bits One digit Two digits Dr. Ihab Talkhan

Two Half Adders are employed to implement a Full Adder.
A combinational circuit that performs the addition of three bits (two significant bits and a previous carry) is called a “Full Adder”. Two Half Adders are employed to implement a Full Adder. The Full adder circuit is the basic arithmetic component from which all other arithmetic circuits are constructed. Dr. Ihab Talkhan

Half-Adder It is an arithmetic circuit that generates the sum of two binary digits. Outputs Inputs S C Y X 1 Half-Adder Dr. Ihab Talkhan

Full-Adder It is a combinational circuit that forms the arithmetic sum of three input bits. Carry from the previous lower significant position Dr. Ihab Talkhan

Outputs Inputs S C Z Y X 1 10 11 01 00 1 10 11 01 00 1 YZ X YZ X
1 YZ 10 11 01 00 1 X YZ 10 11 01 00 1 X Dr. Ihab Talkhan

Binary Parallel Adder The sum of two n-bit binary numbers can be generated in serial or parallel fashion. The serial addition method uses only one Full Adder and a Storage device to hold the output carry. The parallel method uses n-Full Adders and all bits are applied simultaneously to produce the sum. 4-bit Parallel Adder FA Dr. Ihab Talkhan

Example A = 1011 B = 0011 1 Input Carry Augend A Addend B Sum S
1 Input Carry Augend A Addend B Sum S Output Carry Dr. Ihab Talkhan

Binary Adder/Subtractor
The subtraction of binary number can be done most conveniently by means of complements The subtraction “ A-B “ is done by taking the 2’s complement of “ B “ and adding it to “ A “. The 2’s complement can be obtained by taking the 1’s complement and adding “1” to the least significant bit. The 1’s complement can be implemented easily with inverter circuit and we can add “1” to the sum by making the initial input carry of the parallel adder equal to “1”. Dr. Ihab Talkhan

Adder/Subtractor Circuit
FA Adder/Subtractor Circuit S = C0 = addition S = C0 = Subtraction Dr. Ihab Talkhan

BCD Adder An adder that perform arithmetic operations directly with decimal number system employ arithmetic circuit that accept decimal numbers and present results in the same code. It requires a minimum of nine inputs and five outputs, Four bits to code each decimal digit and the circuit must have an input and output carry. When C=0 , nothing is added to the binary sum When C=1, binary 0110 is added to the binary sum through the second 4-bit adder. Any output carry from the second binary adder can be neglected. A decimal parallel adder that adds two n-decimal digits needs n BCD adders, the output carry from each BCD adder must be connected to the input carry of the adder in the next higher position. Dr. Ihab Talkhan

4-bit binary adder Augend Addend
Output carry Output carry from the first Adder Detect the binary output from Condition for correction: input carry BCD sum Augend Addend Dr. Ihab Talkhan

Binary Multiplier The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit. Such multiplication forms a partial products. Successive partial products are shifted one position to the left. The final product is obtained from the sum of the partial products. For “j” multiplier bits and “k” multiplicand bits , we need jxk AND gates and (j-1)k bit adders to produce a product of j+k bits. Dr. Ihab Talkhan

2-bit by 2-bit binary multiplier
HA B0 B1 A0 A1 A0 B0 A0 B1 A1 B0 A1 B1 C0 C1 C2 C3 2-bit by 2-bit binary multiplier Dr. Ihab Talkhan

Decoders Discrete quantities of information are represented in digital computers with binary codes. A binary code of n-bits is capable of representing up to 2n distinct elements of coded information. A decoder is a combinational circuit that converts binary information from n-coded inputs to a maximum of 2n unique outputs. A decoder has n inputs and m outputs and is referred to as “ nxm decoder” Dr. Ihab Talkhan

2-to-4 line Decoder with an Enable Input
1 x Dr. Ihab Talkhan

A0 D0 A1 D1 D2 D3 E Dr. Ihab Talkhan

Example Implement a Full Adder circuit with a decoder and OR gates:
Three inputs  a total of eight minterms  we need a 3-to-8 line decoder. This Decoder generates the eight minterms of X,Y,Z. The OR gate for output S forms the logical sum of minterm 1,2,4,aand 7. The OR gate of output C forms the logical sum of minterms 3,5,6 and 7. Dr. Ihab Talkhan

S C Z Y X 1 2 3 4 5 6 7 Dr. Ihab Talkhan

Z S 20 Y 21 X 22 C 3x8 Decoder Dr. Ihab Talkhan

Encoders An Encoder has 2n (or less) input lines and n output lines.
Dr. Ihab Talkhan

Priority Encoder It is a combinatinal circuit that implements the priority function. The operation of the priority Encoder is such that, if two or more inputs are equal to “1” at the same time, the input having the highest priority will take precedence. The input D3 in the following Truth Table has the highest priority, regardless of the values of the other inputs. Thus, if D3 is “1” , the output will indicate that A1A0 = 11, i.e. the code A1A0 = 11 means that any data appears on line D3 will have the highest priority and pass through the system irrespective of the other inputs. If D2 = “1” and D3 = “0” the code A1A0 = 10 and this means that D2 has the highest priority in this case. Dr. Ihab Talkhan

Outputs Inputs V A0 A1 D0 D1 D2 D3 1 X 10 11 01 00 1 10 11 01 00 1
1 X D1D0 D3D2 10 11 01 00 1 D1D0 D3D2 10 11 01 00 1 Dr. Ihab Talkhan

4-input Priority Encoder
A0 D2 A1 D1 V D0 4-input Priority Encoder Dr. Ihab Talkhan

Multiplexers It is a combinational circuit that selects binary information from one of many lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection variables. Normally, there are 2n input lines and “n” selection variables whose bit combinations determine which input is selected. As in decoders, multiplexers may have an enable input to control the operation of the unit. When the enable input is in the active state, the outputs are disabled. The enable input is useful for expanding two or more multiplexers onto a multiplexer with a larger number of inputs. Dr. Ihab Talkhan

4-to-1 line Multiplexer ( MUX )
S0 S1 D0 D1 D2 D3 Y Function Table Y S1 S0 D0 D1 D2 D3 1 4-to-1 line Multiplexer ( MUX ) [ Data Selector ] Dr. Ihab Talkhan

Implementing a Boolean Function of “n” variables with a Multiplexer that “n-1” Selection Inputs
The first “n-1” variables of the function are connected to the selection inputs of the multiplexer. The remaining single variable of the function is used for the data inputs. If the single variable is “Z”, the data input of the multiplexer will be either ; Dr. Ihab Talkhan

Example F Z Y X 1 4 x 1 MUX Dr. Ihab Talkhan

General Steps The Boolean function is first listed in a truth table.
The first “n-1” variables listed in the table are applied to the selection inputs of the MUX. For each combination of the selection variables, we evaluate the output as a function of the last variable. This can be 0, 1, the variable or the complement of the variable. Dr. Ihab Talkhan

Demultiplexer It is a digital function that performs the inverse operation of a MUX. It receives information from a single line and transmits it to one of 2n possible output lines. The selection of the specific output is controlled by the bit combination of n-selection lines. Dr. Ihab Talkhan

E S0 D0 D1 S1 D2 D3 1-to-4 Demultiplexer Dr. Ihab Talkhan

Sequential Circuits

Logic Circuits Consists of logic gates whose outputs at any time are determined directly from the values of the present inputs. No feedback or storage elements are involved. It involves storage elements (Flip-Flops). Outputs are a function of inputs and the state of the storage elements, where the state of the storage elements is a function of the previous inputs. Circuit behavior must be specified by a time sequence of inputs and internal states. Dr. Ihab Talkhan

Logic Circuits Dr. Ihab Talkhan

Outputs = f( external inputs , present states)
A sequential circuit is specified by a time sequence of inputs, outputs and internal states. It contain memory and thus can remember the changes of input signals that occurred in the past. Inputs for the sequential circuit are functions of external inputs and the present state of the storage elements. Both external inputs and the present states determine the binary value of the outputs and the condition for changing the state of the storage state. Outputs = f( external inputs , present states) Next state = f( external inputs , present states) Dr. Ihab Talkhan

Sequential Circuits It is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time It is a system whose behavior depends upon the order in which the inputs change, and the state of the circuit can be affected at any instant of time Dr. Ihab Talkhan

An asynchronous sequential circuit may be regarded as a combinational circuit with feedback, thus the system may operate in an unpredictable manner and sometimes may even become unstable. The various problems encountered in asynchronous systems impose many difficulties on the designer, and for this reason they are seldom used. A synchronous sequential circuit employs signals that affect the storage elements only at discrete instant of time, as synchronization is achieved by a timing device called a “Clock Generator” that produces a periodic train of clock pulses. Dr. Ihab Talkhan

The clock pulses are distributed throughout the system in such a way that storage elements are affected only upon the arrival of each pulse, the outputs of the storage elements change only when clock pulses are present. The storage elements employed in clocked sequential circuits are called “Flip-Flops”. A Flip-Flop is a binary storage device capable of storing one bit of information. When a clock pulse is not active, the feedback loop is broken because the Flip-Flop outputs cannot change even if the outputs of the combinational circuit change in value, thus the transition from one state to the other occurs only at predetermined time intervals dictated by the clock pulses. Dr. Ihab Talkhan

Combinational Circuit Synchronous clocked sequential circuit
inputs Outputs Combinational Circuit Next state change only during a clock pulse transition Next state FLIP-Flop Clock pulses Present state Synchronous clocked sequential circuit Dr. Ihab Talkhan

A Flip-Flop circuit has two outputs, one for the normal value and the other for the complemented value of the bit that is stored in it. Dr. Ihab Talkhan

Latches A Flip-Flop circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit), until directed by an input signal to switch states. Latches are the basic circuit from which all Flip-Flops are constructed. Dr. Ihab Talkhan

SR-Latch (NOR gates) SR-Latch with NOR gates Action Q R S Set state 1
Action that must be taken Action Q R S Set state 1 Reset State Undefined reset set No change SR-Latch with NOR gates Dr. Ihab Talkhan

SR-Latch (NAND gates) SR-Latch with NAND gates Action Q R S Set state
Action that must be taken Action Q R S Set state 1 Reset State Undefined set reset No change SR-Latch with NAND gates Dr. Ihab Talkhan

Notice that, the S input in the SR NOR-Latch must go back to “0” before any other changes can occur.
There are two input conditions that cause the circuit to be in the SET state, the first is the action that must be taken by input S to bring the circuit to the SET state, the second is the removing of the active input from S leaving the circuit in the same state. When S=R=1 (NOR-gate latch), both outputs go to “0”, this produces an undefined state and it also violates the requirement that output Q and Q be the complement of each other. Dr. Ihab Talkhan

Comparing the SR NAND-Latch and the SR NOR-Latch, we note that the input signals for the NAND required the complement values of those used for the NOR-Latch. Because the NAND-Latch require a “0” signal to change its state, it is sometimes referred to as an S-R Latch, the bar above the letters designates the fact that the inputs must be in their complement form to activate the circuit. Dr. Ihab Talkhan

SR-Latch with NAND gates
SR-Latch (NAND gates) set Next state of Q R S C No change X 1 Q=0 : reset state Q=1 : set state undetermined reset SR-Latch with NAND gates and a control input Dr. Ihab Talkhan

The control input C acts as an enable signal for the other two inputs.
An additional control input which determines when the state of the latch can be changed is added to the basic SR-Latch to improve its operation The control input C acts as an enable signal for the other two inputs. Dr. Ihab Talkhan

D-Latch Next state of Q D C No change X Q=0: reset state 1
Q=0: reset state 1 Q=1: set state Dr. Ihab Talkhan

One way to eliminate the undesirable condition of the indeterminate state in the SR-Latch is to insure that inputs S & R are never equal to 1 at the same time. As long as the control input is at “0”, the cross-coupled SR latch has both inputs at the 1 level and the circuit can not change regardless of the value of D. Dr. Ihab Talkhan

JK Flip-Flop Next state of Q K J C No change X 1 Q=0 : reset state
1 Q=0 : reset state Q=1 : set state Complement (toggle) Dr. Ihab Talkhan

T Flip-Flop Next state of Q T C No change X 1 complement
1 complement Dr. Ihab Talkhan

Flip-Flops Characteristic Tables & Equations
SR Flip-Flop Operation Q(t+1) R S No change Reset Set Indeterminate Q(t) 1 N/A JK Flip-Flop Operation Q(t+1) K J No change Reset Set Complement Q(t) 1 D Flip-Flop Operation Q(t+1) D Reset Set 1 T Flip-Flop Operation Q(t+1) T No change Complement Q(t) 1 Dr. Ihab Talkhan

Analysis Procedure Obtain the binary values of each Flip-Flop input equation in terms of the present state and input variables Use the corresponding Flip-Flop characteristic table to determine the next state. Dr. Ihab Talkhan

The characteristic tables are a shorter version of the truth table, it gives for every set of input values and the state of the Flip-Flop before the rising-end (edge) the corresponding state of the Flip-Flop after the rising edge of the clock signal. By using K-map we can derive the characteristic equation for each Flip-Flop Dr. Ihab Talkhan

Flip-Flop Excitation Tables
SR Flip-Flop Excitation Table R S Q(t+1) Q(t) X 1 JK Flip-Flop Excitation Table K J Q(t+1) Q(t) X 1 D Flip-Flop Excitation Table D Q(t+1) Q(t) 1 T Flip-Flop Excitation Table T Q(t+1) Q(t) 1 Dr. Ihab Talkhan

The excitation for each Flip-Flop, is used during the analysis of sequential circuits. It is derived from the characteristic table by transposing input and output columns. It gives the value of the Flip-Flop‘s inputs that are necessary to change the Flip-Flop’s present state to the desired next state after the rising edge of the clock signal. Dr. Ihab Talkhan

In addition to graphical symbols, tables, or equations, Flip-Flops can also be described uniquely by means of State diagrams or State graphs, in which case each state would be represented by a circle , and a transition between state would be represented by an arrow. Dr. Ihab Talkhan

State Diagram for various Flip-Flops
Q=0 Q=1 SR = 10 SR = 01 SR =00 or 10 SR =00 or 01 SR Flip-Flop Q=0 Q=1 JK = 10 or 11 JK = 01or 11 JK =00 or 10 JK =00 or 01 JK Flip-Flop Dr. Ihab Talkhan

State Diagram for various Flip-Flops
Q=0 Q=1 D = 1 D = 0 D Flip-Flop Q=0 Q=1 T = 1 T = 0 T Flip-Flop Dr. Ihab Talkhan

The State Diagram The state diagram can be obtained directly from the state table. The state is represented by a circle and the transition between state is indicated by a directed lines connecting the circles. The directed lines are labeled with two binary numbers separated by a slash, the input value during present state and the second is the output during the present state. Same state can represent both the source and destination of a transition. Each state can be thought of as a time interval between two rising edges of the clock signal. Dr. Ihab Talkhan

The State Diagram (cont.)
During present state Input / output Q=0 Q=1 State of a Flip-Flop Directed line Dr. Ihab Talkhan

Example Consider a sequential circuit with two JK Flip-Flops (A & B) and one input “X”, specified by the following input equations: Dr. Ihab Talkhan

A B Dr. Ihab Talkhan

State Table Flip-Flop Inputs Next State Input Present State B A X 1
1 JK Flip-Flop Excitation Table K J Q(t+1) Q(t) X 1 JK Flip-Flop Characteristic Table Operation Q(t+1) K J No change Reset Set Complement Q(t) 1 Dr. Ihab Talkhan

Steps Find , , , from the equations
Find the next state from the corresponding J & K inputs using the characteristic table of the JK Flip-Flop. Dr. Ihab Talkhan

State Diagram Value of input X 1 00 01 1 1 10 11 Dr. Ihab Talkhan

State Reduction It is the reduction of the number of flip-flops in a sequential circuit It is concerned with procedures for reducing the number of states in a state table, while keeping the external input/output requirements unchanged. Knowing that “m” flip-flops produce “2m” states, a reduction in the number of states may or may not result in a reduction in the number of flip-flops. An unpredictable effect in reducing the number of flip-flops is that the equivalent circuit might require more combinational gates. Dr. Ihab Talkhan

Example Consider the state diagram shown.
Only the input/output sequences are important The states inside the circles are denoted by letter symbol instead of their binary values. There are infinite number of input sequences that may be applied to the circuit, each results in a unique output sequence. Consider the input sequence and the initial state is “a”. Dr. Ihab Talkhan

Note we are only concerned with the input/output relationships
Example (cont.) Each input of “0” or “1” produce an output of “0” and “1” and causes the circuit to go to the next state. Thus using the state diagram with the given input sequence and “a” as the initial state, the complete sequence is as follows: a g f e d c b State 1 Input Output Note we are only concerned with the input/output relationships Dr. Ihab Talkhan

Example (cont.) It is more convenient to apply procedure for state reduction using a table rather than a diagram. The state diagram is given by [ as obtained from the state diagram]: Output Next State x = 1 x = 0 Present State 1 b d f a c e g Dr. Ihab Talkhan

Example (cont.) Dr. Ihab Talkhan

Master-Slave Flip-Flop
It consists of two Latches and an inverter. When clock pulse input C=“1”, then the output of the inverter is “0”. Thus the Master is enabled and its output Y is equal to the external input D and the Slave is disabled. When clock pulse input C=“0”, then the output of the inverter is “1”. Thus the Slave is enabled and its output Q is equal to the Master output Y and the Master is disabled. Any changes in the external D input changes the master output Y but cannot affect the Slave output Q. Dr. Ihab Talkhan

MASTER SLAVE C D Y Q External D Dr. Ihab Talkhan

Master-Slave with a JK Flip-Flop
Replacing the Master D Latch with an SR Latch with control input, the result is a Master-Slave SR Flip-Flop. But the SP Flip-Flop has the undesirable condition of producing an indeterminate next state when S=R=1. A modified version of the SR Flip-Flop that eliminates the undesirable condition is the JK Flip-Flop, in this case when J=K=1, it causes the output to complement its value Dr. Ihab Talkhan

Master-Slave with a JK Flip-Flop (cont.)
Dr. Ihab Talkhan

Flip-Flips with Asynchronous Inputs
Each Flip-Flop is usually available with and without asynchronous inputs, that are used to preset and clear the Flip-Flops independently of other Flip-Flop inputs. These inputs are used to set the Flip-Flops into initial state for their standard operation, as when power is turned on, the state of each Flip-Flop is not predictable, thus we must use asynchronous inputs to set the Flip-Flop properly. Asynchronous means, inputs do not depend on the clock signal and therefore have precedence over all other operations. Dr. Ihab Talkhan

Flip-Flips with Asynchronous Inputs
CLR & PRS are asynchronous inputs Dr. Ihab Talkhan

Active-low CLR & PRS Active-high CLR & PRS
Dr. Ihab Talkhan

Edge Triggered Flip-Flop (Latch)
It is divided into three Latches: The SET latch The Reset Latch The Output Latch A low value of asynchronous signals affects the FLIP-Flop: The Latch is preset by the signal PRS = 0 The Latch is cleared by the signal CLR = 0 Note that, the preset and clear signals force all the latches into proper states that correspond to Q = 1 & Q = 0 respectively. Dr. Ihab Talkhan

SET Latch OUTPUT Latch RESET Latch Dr. Ihab Talkhan

Edge Triggered Flip-Flop (Latch) (cont.)
Active-low preset and clear signals are more frequently found in practice. Note that, the SET latch follows the changes in the CLK signal if D is equal to “1” at the rising edge of the CLK signal, while the RESET latch follows the CLK signal if D=0 at the rising edge of the CLK signal. Dr. Ihab Talkhan

Registers The simplest of the storage components.
Each register consists of n-Flip-Flops driven by a common clock signal. SET (Preset) and RESET (Clear) inputs are independent of the clock signal and have priority over it. The register store any new data automatically on every rising edge of the clock. Dr. Ihab Talkhan

4-bit register I3 I2 I1 I0 Q3 Q2 Q1 Q0 Preset CLK Clear
Dr. Ihab Talkhan

Register with a Selector (Mutliplexer)
To control the input data of a register, a selector (Multiplexer [MUX]) unit is used, where a selector is a device that accepts many inputs and selects only one of them at a time to represent the output [ 2n-inputs, n-control and one output ]. A control signal “LOAD” or “Enable” is used, which allows loading the data into the register [parallel-load register]. The selector, selects either input data or data already stored in the register. Dr. Ihab Talkhan

Load = 1 enter new data (Ii , i = 0,1,2,3)
enter previous stored data (Qi , i = 0,1,2,3) Dr. Ihab Talkhan

Shift Register It shifts its contents one bit in the specified direction when the control signal “SHIFT” is equal to “1”. It is used to convert a serial data stream into a parallel stream. Dr. Ihab Talkhan

4-bit serial-in/parallel-out
Shift-right register 1010 Dr. Ihab Talkhan

A Multi-Functional Register
By using a 4-to-1 Selector, you can combine the SHIFT and LOADING functions into one unit. It either shift its contents or load new data. It could shift one-bit either to the left or to the right depending on the selection mode. Next State Operation Present state Q0 Q1 Q2 Q3 S0 S1 I0 IR I1 I2 I3 IL No change Load input Shift Left Shift Right 1 Dr. Ihab Talkhan

A Multi-Functional Register (cont.)
Dr. Ihab Talkhan

3 2 1 Dr. Ihab Talkhan

Counters A counter is a special type of a register.
It incorporates an incremental, which allows it to count upward or downward. The incremental consists of a series of Half-Adders [HA] arranged such that an HA in bit position “i” will have two inputs connected to the output of the Flip-Flop Qi and the carry Ci from he HA in position “i-1”. The counter equation is as follows: As long as E=1, the counter will count-up modulo 4, adding “1” to its content on every rising edge of the clock. Dr. Ihab Talkhan

D Flip-Flop Excitation Table
Counter > E Enable Clear F.F. Next Present D0 D1 D2 Q0 Q1 Q2 E 1 2 3 4 5 6 7 Q2 Q1 Q0 Enable = 0 no change = 1 count D Flip-Flop Excitation Table D Q(t+1) Q(t) 1 Three states Flip-Flops, we will use D F.F. as an example Dr. Ihab Talkhan

Q1Q0 Q1Q0 10 11 01 00 1 10 11 01 00 1 Q2 Q2 Q1Q0 10 11 01 00 1 Q2 Dr. Ihab Talkhan

3-bit up-counter Half-Adder Q2 Q1 Q0 C0 C1 C2 C3 E D1 D0 D2 carry
Dr. Ihab Talkhan

Dr. Ihab Talkhan

Up/Down Counter The previous counter can be extended to represent an up/down counter, if we replace the Half-Adder with a Half-Adder/Subtractor [HAS], which can increment or decrement under the control of a direction signal “ D “, in this case the counter equation will be: Dr. Ihab Talkhan

4-bit up/down Binary Counter
Direction signal , D = count up, D = count down D E C0 C3 C1 C2 Carry D2 D1 D0 CLEAR CLK D E No change Count-up Count-down X 1 Q2 Q1 Q0 4-bit up/down Binary Counter Dr. Ihab Talkhan

Half-Adder/Subtractor [ HAS ]
E = Ci Ci+1 Di Dr. Ihab Talkhan

3-bit up/down Counter with Parallel Load [ Presetable Counter ]
Output carry HAS HAS HAS Selector Selector Selector Load Clear CLK Q2 Q1 Q0 Dr. Ihab Talkhan

4-bit up/down Counter with Parallel Load [ Presetable Counter ] [cont
Operation D E Load No change Count-up Count-down Load input X 1 Dr. Ihab Talkhan

Dr. Ihab Talkhan

BCD Counter It can be constructed by detecting when the counter reaches a count of “9” and loading “0” instead of “10” in the next clock cycle. The detection is accomplished by an AND gate whose output is equal to “1” when the content of the counter is equal to “1001”. The output of the AND is connected to the Counter's Load input, which allows the counter to load “0” at the next rising edge of the clock. In the up direction we must load “0” into the counter when it reaches a count of “9”, while in the down direction we must load “9” when the counter reaches a count of “0”. Dr. Ihab Talkhan

Dr. Ihab Talkhan

Up/Down Counter BCD up-counter
Up/Down Counter BCD up-counter Dr. Ihab Talkhan

Up/Down BCD Counter Selector Up/Down Counter
Dr. Ihab Talkhan

Asynchronous Counter All Flip-Flops are not all clocked by the same clock signal There is no need to use an incremental or decremental, counting is achieved by toggling each Flip-Flop at half the frequency of the preceding Flip-Flop. The Flip-Flop will change its state on every 0-to-1 transition of its clock input. Note, the clock signal “CLK” is used to only clock the Flip-Flop in the least significant position. The clock-to-output delay of the ith Flip-Flop is equal to “i”. The maximum counting frequency of an n-bit asynchronous counter is: Dr. Ihab Talkhan

4-bit Asynchronous Up-Counter
Dr. Ihab Talkhan

8 7 6 5 4 3 2 1 CLK 4  Q3 3  Q2 2  Q1  Q0 t0 t1 t2 t3 t4 t5 t6 t7 Dr. Ihab Talkhan

Ring Counter It is a circular shift-register with only one flip-flop being set at any particular value, all others are cleared. The single bit is shifted from one flip-flop to the next to produce the sequence of timing signals. To generate “2n” timing signals , we need either a shift register with “2n” flip-flops or an n-bit binary counter together with a n-to-2n line decoder. Dr. Ihab Talkhan

Each flip-flop is in the “1” state once every four cycles
Ring Counter (cont.) Each flip-flop is in the “1” state once every four cycles Dr. Ihab Talkhan

Johnson Counter It is a k-bit switch-tail ring counter with 2k decoding gates to provide output for 2k timing signals. [k distinguishable states] Dr. Ihab Talkhan

Johnson Counter (cont.)
Dr. Ihab Talkhan

Counter with unused states
States that are not used in specifying the sequential circuit are not listed in the state diagram Dr. Ihab Talkhan

Ripple Counter A binary ripple counter consists of a series connection of complementing flip-flops, with the output of each flip-flop connected to the clock input of the next higher-order flip-flop. The flip-flop holding the least significant bit receives the incoming count pulses. It is an asynchronous sequential circuit. Dr. Ihab Talkhan

Ripple Counter (cont.) Dr. Ihab Talkhan

BCD Ripple Counter Dr. Ihab Talkhan

Three-Decade Decimal BCD Counter
Dr. Ihab Talkhan

Mixed-mode Counters To speed up an asynchronous counter, we must make it partly synchronous. To do this, we divide a large counter into n-bit slices, so that the operation within each slice is asynchronous, while the propagation between slices is synchronous, or vice versa. Dr. Ihab Talkhan

Synchronous Counter with 4-bit Asynchronous Slices
8-bit Mixed-mode Counter Dr. Ihab Talkhan

Asynchronous Counter with 4-bit Synchronous Slices
8-bit Mixed-mode Counter Dr. Ihab Talkhan

Memory & Programmable Logic

Major Units For any system, there are three major units:
Central processing unit CPU Memory unit Input/Output unit In digital system, memory is a collection of cells capable of storing binary information (permanent or temporary). It contains electronic circuits for storing and retrieving information. It interacts with the CPU and input/output units. Dr. Ihab Talkhan

Transfer stored information out of memory (read)
Accept new information for storage to be available later for use (write) Transfer stored information out of memory (read) RAMs may range on size from hundreds to billions of bits. It is volatile It is a programmable logic devices PLDs, which are integrated circuits with internal logic gates connected through electronic fuses. Programming is done by blowing these fuses to obtain the desired logic function. Dr. Ihab Talkhan

Conventional Symbol Array Logic Symbol Dr. Ihab Talkhan

Dr. Ihab Talkhan

Example of a PLD Chip Dr. Ihab Talkhan

Dr. Ihab Talkhan

Programming Technology
To establish the programmable connections the following technologies are used: EPROM EEPROM FLASH Dr. Ihab Talkhan

EPROM used to create a wired –AND function. The transistor has two gates, a select gate and a floating gate, charge can be accumulated and trapped on the floating gate by a mechanism called avalanche injection or hot electron injection. These transistors are referred to as FAMOS (Floating gate Avalanche-injection MOS). Note that without a charge on the floating gate the FAMOS acts as a normal n-channel transistor in that when a voltage is applied to the gate, the transistor is turned on. EPROM cells provide a mechanism to hold a programmed state, which is used in PLDs or CPLDs to establish or not establish a connection. To erase the cell remove charge from the floating gate by exposing the device to ultraviolet light. (typical erasure time is about 35 minutes under high-intensity UV light. Dr. Ihab Talkhan

Dr. Ihab Talkhan

EEPROM E2PROM, used to create a wired AND-function. It consists of two transistors (select & storage transistors). These transistors are referred to as FLOTOX (Floating gate Tunnel Oxide transistors). It is similar to the FAMOS except that the oxide region over the drain is considerably smaller, less than 10 Ao (Angstroms) compared to 200 Ao for the FAMOS. This allows charges to be accumulated and trapped on the floating gate by a mechanism called Fowler-Nordheim tunneling. E2PROM cells require a select transistor because when the floating gate does not hold a charge, the threshold voltage of the FLOTOX transistor is negative. Dr. Ihab Talkhan

Dr. Ihab Talkhan

FLASH like E2PROM, FLASH cells consist of two transistors (select & storage transistors). They create a wired AND function. The storage Transistor is a FAMOS, so programming is accomplished via hot electron injection. However the floating gate is shared by an eraser transistor that take charge off it via tunneling. Dr. Ihab Talkhan

Dr. Ihab Talkhan

RAM Random access from any random location.
It stores information in groups of bits (called “words”. A word is a group of 1’s & 0’s (represents numbers, instructions, alphanumeric characters, binary coded information). Normally, a word is a multiples of 8 bits (1 byte) in length, where 1 byte = 8 bits. Capacity of memory = total number of bytes. Dr. Ihab Talkhan

Communications between Memory & Environment
Communications between memory and environment is done through: In/Out lines Address selection lines Control lines Dr. Ihab Talkhan

Memory Unit Block Diagram
2k words n bits/word n data-in lines n data-out lines K-address lines Read Write K-address = specify particular word chosen R/W Control = Direction of transfer Computer range from 210=1024 words (requiring address of 10-bits) to 232 (requiring 32 address bits) Dr. Ihab Talkhan

Units Kilo “K” = 210 Mega “M” = 220 Gega “G” = 230
64 K = (26 x 210 ) 2 M = 221 4 G = 232 Dr. Ihab Talkhan

2k = m , m total number of words, K number of address bits (lines)
Memory Address Memory Content Decimal Binary 1023 Content of 1024 x 16 Memory L 1K x 16bit i.e. 10 address lines & 16-bit word Note: 64K x 10 16 bits in address , 10-bits word 2k = m , m total number of words, K number of address bits (lines) Dr. Ihab Talkhan

Write & Read Write Transfer binary address of desired word to address lines. Transfer data bits that must be stored to data-in lines Activate write-in Read Transfer binary address to address lines. Activate read-in Dr. Ihab Talkhan

Memory Chip Control Select IN Out S R R/W Basic Cell Dr. Ihab Talkhan

m words of n-bits/word consists of n x m binary storage cells
Operation Read/Write Memory Select None X Write 1 Read Select Basic Cell R/W = 1 read path from F.F to output 0 In to F.F. IN OUT R/W m words of n-bits/word consists of n x m binary storage cells Dr. Ihab Talkhan

Memory Chip Symbol RAM 16 x 4 Address- lines Memory Select R/W Data-IN
Data-OUT Memory Chip Symbol Dr. Ihab Talkhan

3-State Buffer It exhibits three distinct states, two of the states are the logic 1 and logic 0 of conventional logic. The third state is the high-impedance (Hi-Z) state. The high-impedance state behaves like an open circuit, i.e. looking back into the logic circuit, we would find that the output appears to be disconnected. Dr. Ihab Talkhan

OUT IN EN Hi-Z 1 X IN OUT ENABLE ) EN) Dr. Ihab Talkhan

Properties of Memory Integrated circuit “RAM” may be either Static or Dynamic It consists of internal latches that store the binary information. The stored information remain valid as long as power is applied to the RAM It stores the binary information in the form of electric charges on capacitors, the capacitors are accessed inside the chip by n-channel MOS transistors. Dr. Ihab Talkhan

SRAM is easier to use and has shorter read/write cycles.
No refresh is required The stored charge on the capacitors tends to discharge with time, and the capacitors must be periodically recharged by refreshing the DRAM. This is done by cycling through the words every few milliseconds, reading and rewriting them to restore the decaying charge. It offers reduced power consumption and larger storage capacity in a single DRAM chip Dr. Ihab Talkhan

Memory units that lose stored information when power is turned-off are said to be Volatile.
Both SRAM & DRAM are of this category, since the binary cells needs external power to maitain the stored information. Magnetic disks, CDs as well as ROM are non-volatile memories, as they retain their stored information after the removal of power. Dr. Ihab Talkhan

Array of RAM Chips Combine a number of chips in an array to form the required memory size. Capacity = number of words & number of bits/word increase in words  increase in address Usually input and output ports are combined, to reduce the number of pins on the memory package. Dr. Ihab Talkhan

4 x 4 memory

4 x 4 Memory It consists of 16 memory cells “MCs”.
For each memory access, the address decoder decodes the address and selects one of the rows. If RWS & CS are both equal to “1”  the new content will be written into each cell of the row selected. Note that the output drivers are disabled to allow the new data to be written-in If RWS = 0 & CS = 1  the data from the row selected will be passed through the tri-state drivers to the IO pins. Dr. Ihab Talkhan

Dr. Ihab Talkhan

Programming Technology
FPLD is programmed using electrically programmable switches. The properties of these programmable switches, such as size, volatility, process technology, on-resistance, and capacitance determine the major features of an FPLD architecture. Dr. Ihab Talkhan

SRAM Programming Technology
Uses SRAM cells to configure logic and control interconnections and paths for signal routing. The configuration is done by controlling pass gate or multiplexers. Reprogrammable. Volatile. Large Area, at least 5 transistors are needed to implement SRAM cell. Uses standard integrated circuit process technology. External permanent memory required to provide the programming bitstream at power-up time MUX 4 x 1 Bit 0 Bit 1 SRAM Cell Pass Gate Dr. Ihab Talkhan

Floating Gate Programming Technology (cont.)
Dr. Ihab Talkhan

Antifuse Programming Technology
It irreversibly changes from high resistance to low resistance when programmed. Relatively low on-resistance “ Ohms”. Small size Programming requires extra circuitry to provide the high voltage & relatively high current “5 mA” or more. Dr. Ihab Talkhan

An Amorphous-Silicon Antifuse
Static RAM SRAM An Amorphous-Silicon Antifuse SRAM cells are used to control the state of pass transistors, which can establish connections between horizontal and vertical wires. (the source to drain of such a pass transistor is about 1000 ohm) SRAM cells are used to drive the select inputs of multiplexers that are used to choose from one of several signals to route on a given wire source. In amorphous (uncrystallized) silicon based FPGA, the two layers of metal are separated by amorphous silicon, which provides electrical insulation. A programming pulse of 10V to 12V with a necessary duration can be applied across the via, causing the top and bottom layers of metal to penetrate the amorphous silicon, creating a bi-directional conductive link. (with a resistance about 50 ohm) Dr. Ihab Talkhan

Static RAM SRAM An Amorphous-Silicon Antifuse An SRAM memory cell consists of five transistors, two for each of the two inverters making up the latch and one addressing (used to select the memory cell for programming) An SRAM is programmable. SRAM cells are volatile, i.e. the states of the memory cells are lost when power is not applied, SRAM-based FPGAs must be programmed (usually from a serial EPROM) each time the circuit is powered on. Once programmed, an antifuse element cannot be erased or reprogrammed. Each antifuse element is isolated by with pass transistors so that other elements are not inadvertently programmed, these programming transistors, constitute the programming circuitry overhead. Dr. Ihab Talkhan

Static RAM SRAM An Amorphous-Silicon Antifuse The programming circuitry for SRAM elements must include the addressing and data registers (programming circuitry overhead). Programmable elements are strategically placed to provide a trade-off between routability, density and performance. Actel FPGA products make use of an Oxide-nitride-oxide (ONO) antifuse, which consists of three layers : The top, conductor made of polysilicon (electrically connected to one layer of metal), the middle, has an oxide-nitride-oxide chemical composition and is an insulator, the bottom, is a conductive layer of negatively doped diffusion. (300 ohm, link resistance) Because antifuse elements can be placed very densely, FPGAs that use this technology have flexibility routing architectures, which allow the electrical connection of wires at nearly every intersection. Dr. Ihab Talkhan

Comparison of Programming Technologies
Dr. Ihab Talkhan

Technological & Operational Differences Between the Programmable Devices
Type Technology Switch Reprogram- able ? Volatile? Leading Company FPGA CMOS SRAM In-circuit Yes Xilinx PLD /CPLD EPROM EEPROM Out-of-circuit No Altera Antifuse Actel Dr. Ihab Talkhan

Xilinx (Example) CLB = Configurable Logic Block
It has 13 i/p & 4 o/p, it is a complex cell (two 4-i/p LUTs (look-up tables) feed another 3 i/p LUT) Each CLB can implement any function of four or five variables and some of up to 9 varaibales Or A CLB can be configured to implement twon functions of 4-variables or one of two variables 7 another of five.. Each CLB has two FF It can be configure for special arithmetic ciruits such as 2-bit adder w/ carry-in and carry-out It can be configured for read/write RAM of 16-bit for storing data. Dr. Ihab Talkhan

Actel (Example) 8 i/p & 1 o/p, it is a very simple cell, more flexibility but more routing, need a lot of cells Dr. Ihab Talkhan

Programmable ASIC Logic Cells
Actel ACT Xilinx LCA Altera Flex Altera Max Dr. Ihab Talkhan

Actel ACT The basic logic cells in Actel ACT family of FPGAs are called logic modules. The ACT1 family use one type of logic modules. ACT2 & ACT3 FPGA families use two different types of logic modules. Dr. Ihab Talkhan

ACT1 Logic Module We can build a logic function using an Actel logic module by connecting logic signals to some or all of the logic module inputs, and connecting any remaining logic module inputs to VDD or GND Dr. Ihab Talkhan

Shanon’s Expansion Theorem
We expand a Boolean logic function “F” in terms of a Boolean variable “A”. We continue to expand a function as many as times as possible until we reach the canonical form (functions uses only minterms). Dr. Ihab Talkhan

Example Given: Expand F w.r.t. B: (multiply D by (B+B’))
Expand F2 ≡ FB w.r.t. A & F1 ≡ FB w.r.t. C: multiply D by (B+B') Dr. Ihab Talkhan

An Example of Logic Macro
Dr. Ihab Talkhan

SRAM Programming Technology
Uses SRAM cells to configure logic and control interconnections and paths for signal routing. The configuration is done by controlling pass gate or multiplexers. Reprogrammable. Volatile. Large Area, at least 5 transistors are needed to implement SRAM cell. Uses standard integrated circuit process technology. External permanent memory required to provide the programming bitstream at power-up time MUX 4 x 1 Bit 0 Bit 1 SRAM Cell Pass Gate Dr. Ihab Talkhan

Floating Gate Programming Technology (cont.)
Dr. Ihab Talkhan

Antifuse Programming Technology
It irreversibly changes from high resistance to low resistance when programmed. Relatively low on-resistance “ Ohms”. Small size Programming requires extra circuitry to provide the high voltage & relatively high current “5 mA” or more. Dr. Ihab Talkhan

Static RAM SRAM An Amorphous-Silicon Antifuse SRAM cells are used to control the state of pass transistors, which can establish connections between horizontal and vertical wires. (the source to drain of such a pass transistor is about 1000 ohm) SRAM cells are used to drive the select inputs of multiplexers that are used to choose from one of several signals to route on a given wire source. In amorphous (uncrystallized) silicon based FPGA, the two layers of metal are separated by amorphous silicon, which provides electrical insulation. A programming pulse of 10V to 12V with a necessary duration can be applied across the via, causing the top and bottom layers of metal to penetrate the amorphous silicon, creating a bi-directional conductive link. (with a resistance about 50 ohm) Dr. Ihab Talkhan