1. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 1 Václav Vrba Institute of Physics, AS CR, Prague Silicon pad sensors for W-Si ECal

2. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 2 Outline Sensor tile outer dimensions Pad array design consideration Time schedule - towards the first prototype Tests outlines

3. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 3 Sensor tile outer dimensions Outcome from the meeting at EP: - 4” high resistivity wafers - tile side: 62.0+0.0 -0.1 mm - scribe line: 100  m - scribe safety zone: 200  m - guard ring width: cca 750  m (cca 1.5 * wafer thickness)  The dead zone width is about 1 mm Wafer book keeping information 1.0 mm

4. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 4 Pad array design consideration Along with the diodes, the technique used for fabrication of bias resistors and coupling capacitors represents an important issue: a) polysilicon resistors – production of the tile needs about 7-8 masks; can be the source of additional yield reduction. b) punch through resistors – production of the tile needs about 5 masks; easy to produce – needs to check whether required parameters can be achieved. c) deposited resistors (amorphous silicon) – achievement of EP; - needs about 4-5 masks for production of the diodes array; on top of that additional fabrication of resistor and capacitors. d) ion implantation resistors – not considered here.

5. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 5 Design consideration: Polysilicon resistors Bias resistor Top view Verticalcross section Coupling capacitor Direct contact on diode – e.g. for testing Bias lines

6. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 6 Design consideration: Polysilicon resistors

7. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 7 Design consideration: Punch through resistors Coupling capacitor Direct contact on diode – e.g. for testing Bias resistor Top view Verticalcross section Bias lines

8. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 8 Deposited resistors – before deposition

9. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 9 Deposited resistors – after deposition Bias lines e.g.Wire bonding, Flex cable gluing, etc.

10. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 10 Design consideration: a partial summary a) polysilicon resistors: -should not be a problem to have resistors  10 M  ; -capacitors  1-10 nF. b) punch through resistors: -resistors to be tested; if acceptable then it is a simple solution; -capacitors as a). c) deposited resistors: -will be considered in the first prototype submission  to test the deposition technology of capacitors and resistors Compatibility of process for variants a), b) and c) on one wafer? To try all variants separately could be quite costly! Option c) as a baseline for main sensor tile?

11. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 11 Design consideration: a partial summary

12. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 12 Time schedule Pre-prototyping  using existing masks to evaluate some effects of: -high resistive Silicon; -guard rings, scribe lines, etc. -#wafers thickness [  m] - 4 SSP Wacker 500 - 3 DSP Topsil 500 - 4 DSP Topsil 300 Mask design preparation  GDS file First 10-16 wafers ready for testing now in process By end of April 2002 By end of June 2002

13. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 13 Pre-prototyping Active area cca 0.3 cm 2 Active area cca 10 cm 2 Wafer diameter: 100 mm Wafer backside all Al metallized

14. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 14 Tests outlines A) Diode tests a) C-V curves:  determination of V full-depletion ; V op = V full-depletion + 50 V. b) I-V curves: -V break-down  V op -I leak @ V op < cca 30 nA/cm 2 c) Long term stability tests: -I leak @ V op. Tile should be rejected if: -V break-down < V op -I leak > I crit (to be defined).

15. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 15 Electric characterization

16. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 16 Long term current stability on Tile x 10s time Measured @ 150V

17. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 17 Tests outlines B) Bias resistors a) shorts b) breaks c) outside specifications C) Capacitance couplings a) shorts b) breaks c) outside specifications

18. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 18 Manual Probestation

19. St Malo, 13 th April 2002Václav Vrba, Institute of Physics, AS CR 19 Manual Probestation