1. CSET 4650 Field Programmable Logic Devices Dan Solarek Logic Families Introduction & Overview

2. 2 Logic Families Logic Family : A collection of different IC’s that have similar circuit characteristics The circuit design of the basic gate of each logic family is the same The most important parameters for evaluating and comparing logic families include : Logic Levels Power Dissipation Propagation delay Noise margin Fan-out ( loading )

3. 3 Example Logic Families General comparison or three commonly available logic families. the most important to understand

4. 4 Implementing Logic Circuits There are several varieties of transistors – the building blocks of logic gates – the most important are: BJT (bipolar junction transistors) one of the first to be invented FET (field effect transistors) especially Metal-Oxide Semiconductor types (MOSFET’s) MOSFET’s are of two types: NMOS and PMOS

5. 5 Transistor Size Scaling Performance improves as size is decreased: shorter switching time, lower power consumption. 2 orders of magnitude reduction in transistor size in 30 years.

6. 6 Moore’s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months i.e., grow exponentially with time Considered a visionary – million transistor/chip barrier was crossed in the 1980’s 2300 transistors, 1 MHz clock (Intel 4004/4040) - 1971 42 Million transistors, 2 GHz clock (Intel P4) - 2001 140 Million transistors, (HP PA-8500)

7. 7 Moore’s Law and Intel From Intel’s 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond

8. 8 TTL and CMOS Connecting BJT’s together gives rise to a family of logic gates known as TTL Connecting NMOS and PMOS transistors together gives rise to the CMOS family of logic gates BJT MOSFET (NMOS, PMOS) TTL CMOS transistor types logic gate families

9. 9 Electrical Parameters And Interpretation Of Data Sheets Voltages and Currents Noise Margin Power Dissipation Propagation Delay Speed-Power Product Fan-In, Fan-Out Comparison of Logic Families Interpretation of Data Sheets

10. 10 Electrical Characteristics TTL faster (some versions) strong drive capability rugged CMOS lower power consumption simpler to make greater packing density better noise immunity Complex IC’s contain many millions of transistors If constructed entirely from TTL type gates would melt A combination of technologies (families) may be used CMOS has become most popular and has had greatest development

11. 11 For a High-state gate driving a second gate, we define: V OH (min), high-level output voltage, the minimum voltage level that a logic gate will produce as a logic 1 output. V IH (min), high-level input voltage, the minimum voltage level that a logic gate will recognize as a logic 1 input. Voltage below this level will not be accepted as high. I OH, high-level output current, current that flows from an output in the logic 1 state under specified load conditions. I IH, high-level input current, current that flows into an input when a logic 1 voltage is applied to that input. Voltage & Current Test setup for measuring values

12. 12 For a Low-state gate driving a second gate, we define: V OL (max), low-level output voltage, the maximum voltage level that a logic gate will produce as a logic 0 output. V IL (max), low-level input voltage, the maximum voltage level that a logic gate will recognize as a logic 0 input. Voltage above this value will not be accepted as low. I OL, low-level output current, current that flows from an output in the logic 0 state under specified load conditions. I IL, low-level input current, current that flows into an input when a logic 0 voltage is applied to that input. Voltage & Current Inputs are connected to V cc instead of Ground Ground V IL V OL I I IL

13. 13 Electrical Characteristics Important characteristics are: V OHmin min value of output recognized as a ‘1’ V IHmin min value input recognized as a ‘1’ V ILmax max value of input recognized as a ‘0’ V OLmax max value of output recognized as a ‘0’ Values outside the given range are not allowed. logic 0 logic 1 indeterminate input voltage

14. 14 Typical acceptable voltage ranges for positive logic 1 and logic 0 are shown below A logic gate with an input at a voltage level within the ‘indeterminate’ range will produce an unpredictable output level. Logic Level & Voltage Range Logic 1 Logic 0 5.0V 0V 2.5V Indeterminate 0.8V TTL Logic 1 Logic 0 5.0V Indeterminate 0V 1.5V CMOS 3.5V

15. 15 Noise Margin Manufacturers specify voltage limits to represent the logical 0 or 1. These limits are not the same at the input and output sides. For example, a particular Gate A may output a voltage of 4.8V when it is supposed to output a HIGH but, at its input side, it can take a voltage of 3V as HIGH. In this way, if any noise should corrupt the signal, there is some margin for error.

16. 16 Noise Margin If noise in the circuit is high enough it can push a logic 0 up or drop a logic 1 down into the indeterminate or “illegal” region The magnitude of the voltage required to reach this level is the noise margin Noise margin for logic high is: N MH = V OHmin – V IHmin V OHmin V IHmin V ILmax V OLmax logic 0 logic 1 indeterminate input voltage

17. 17 Noise Margin Difference between the worst case output voltage of one stage and worst case input voltage of next stage Greater the difference, the more unwanted signal that can be added without causing incorrect gate operation NM high = V OHmin - V IHmin NM low = V ILmax - V OLmax

18. 18 Given the following parameters, calculate the noise margin of 74LS series. Solution: High Level Noise Margin, V NH = V OH (min) - V IH (min)=2.7V-2.0V=0.7V Low Level Noise Margin, V NL = V IL (max) - V OL (max)=0.8V-0.4V=0.4V Worked Example

19. 19 Noise immunity of a logic circuit refers to the circuit’s ability to tolerate noise voltages on its inputs. A quantitative measure of noise immunity is called noise margin High Level Noise Margin, V NH = V OH (min) - V IH (min) Low Level Noise Margin, V NL = V IL (max) - V OL (max) Noise Margin & Noise Immunity Logic 1 Logic 0 Logic 1 V OH (min) V OL (max) V IH (min) V IL (max) V NH V NL Output Voltage Ranges Input Voltage Ranges

20. 20 Further Important Characteristics The propagation delay (t pd ) which is the time taken for a change at the input to appear at the output The fan-out, which is the maximum number of inputs that can be driven successfully to either logic level before the output becomes invalid

21. 21 Speed: Rise & Fall Times Rise Time Time from 10% to 90% of signal, Low to High Fall Time Time from 90% to 10% of signal, High to Low rise time 10%90% 10% fall time

22. 22 A logic gate always takes some time to change states t PLH is the delay time before output changes from low to high t PHL is the delay time before output changes from high to low both t PLH & t PHL are measured between the 50% points on the input and output transitions Speed: Propagation Delay 50% Input Output 0 0 t PHL t PLH

23. 23 Power Dissipation Static I 2 R losses due to passive components, no input signal Dynamic I 2 R losses due to charging and discharging capacitances through resistances, due to input signal

24. 24 Speed (propagation delay) and power consumption are the two most important performance parameters of a digital IC. A simple means for measuring and comparing the overall performance of an IC family is the speed- power product (the smaller, the better). For example, an IC has an average propagation delay of 10 ns an average power dissipation of 5 mW the speed-power product = (10 ns) x (5 mW) = 50 picoJoules (pJ) = 50 picoJoules (pJ) Speed-Power Product

25. 25 Logic Family Tradeoffs Looking for the best speed/power product t p and Pd are normally included in the data sheet for each device Older logic families are the worst CMOS is one of the best FPGAs use CMOS

26. 26 Comparison of Logic Families

27. 27 TTL - Example SN74LS00 Recommended operating conditions V cc supply voltage 5V ± 0.5 V input voltages V IH = 2V V IL = 0.8V Electrical Characteristics output voltage V OH = 2.7V (worst case) V OL = 0.5V max input currentsI IH = 20µA I IL = -0.4mA propagation delay t pd = 15 nS noise margins for a logic 0 = 0.3V for a logic 1 = 0.7V Fan-out20 TTL loads 5 Volt 0 Volt 0.8 0.5 2.0 2.7 Input Range for 1 Input Range for 0 Output Range for 0 Output Range for 1

28. 28 Fan-In Number of input signals to a gate Not an electrical property Function of the manufacturing process NAND gate with a Fan-in of 8

29. 29 Fan-Out A measure of the ability of the output of one gate to drive the input(s) of subsequent gates Usually specified as standard loads within a single family e.g., an input to an inverter in the same family May have to compute based on current drive requirements when mixing families Although mixing families is not usually recommended

30. 30 V OH I IH Low V OL I IL High Current Sourcing and Sinking Current-source : the driving gate produces a outgoing current Current-sinking : the driving gate receives an incoming current

31. 31 Fan-Out An illustration of fan-out and the associated source and sink currents

32. 32 How many 74LS00 NAND gate inputs can be driven by a 74LS00 NAND gate outputs ? Solution: Refer to data sheet of 74LS00, the maximum values of I OH = 0.4mA, I OL = 8mA, I IH = 20uA, and I IL = 0.4mA I OH = 0.4mA, I OL = 8mA, I IH = 20uA, and I IL = 0.4mAHence, fan-out(high) = I OH (max) / I IH (max)=0.4mA/20uA=20 fan-out(low) = I OL (max) / I IL (max)=8mA/0.4mA=20, the overall fan-out = fan-out(high) or fan-out(low) whichever is lower. Hence, overall fan-out = 20 Worked Example

33. 33 A logic gate can supply a maximum output current I OH (max), in the high state or I OL (max), in the low state A logic gate requires a maximum input current I IH (max), in the high state or I IL (max), in the low state Ratio of output and input current decide how many logic gates can be driven by a logic gate fan-out(high) = I OH (max) / I IH (max) fan-out(low) = I OL (max) / I IL (max) overall fan-out = fan-out(high) or fan-out(low) whichever is lower A typical figure of fan-out is ten (10) Gate Drive Capability: Fan-Out

34. 34 Wired-AND Open collector outputs connected together to a common pull- up resistor Any collector can pull the signal line low Logically an AND gate

35. 35 Tri-State Logic Both output transistors of totem-pole output are turned off Usually used to bus multiple signals on the same wire Gates not enabled present high-Z to bus and therefore do not interfere with other gates putting signals on the bus

36. 36 Tri-State Logic Tri-state logic includes a switch at the output In the figure below, the three states are illustrated: a) Logic High output b) Logic Low output c) High impedance (Hi-Z) output

37. 37 Electronic Combinational Logic Within each of these families there is a large variety of different devices We can break these into groups based on the number gates per device AcronymDescription No Gates Example SSI Small-scale integration <12 4 NAND gates MSI Medium-scale integration 12 – 100 Adder LSI Large-scale integration 100 – 1000 6800 VLSI Very large-scale integration 1000 – 1M 68000 ULSI Ultra large scale integration > 1M 80486/80586

38. 38 SSI Devices Each package contains a code identifying the package N74LS00 Manufacturers Code N = National Semiconductors SN = Signetics Specification Family L LS H Member 00 = Quad 2 input NAND 02 = Quad 2 input Nor 04 = Hex Invertors 20 = Dual 4 Input NAND

39. 39 7400 Series History 1960s space program drove development of 7400 series Consumed all available devices for internal flight computer $1000 / device (1960 dollars) 10:1 integration improvement over discrete transistors 1963 Minuteman missile forced 7400 into mass production Drove pricing down to $25 / circuit (1963 dollars)

40. 40 7400 Series Evolution BJT storage time reduction by using a BC Schottky diode. Schottky diode has a Vfw=0.25V. When BC junction becomes forward biased Schottky diode will bypass base current. B C

41. 41 Too Much of a Good Thing? FamiliesPackages Reliability options Speed grades FeaturesFunctions An availability nightmare! >> 500K unique devices

42. 42 Different Families Don’t all Speak the Same Language

43. 43 Sometimes Things Get Lost or Added in the Translation* Different families aren’t always on speaking terms with one another

44. 44 The World of TTL

45. 45 Success Drives Proliferation New families introduced based on Higher performance Lower power New features New signaling threshold Spawned over 32 unique families! 1960 2003

46. 46 Success Drives Proliferation Products introduced in the 1960 are near the end of their life cycle Decreasing supplier base Increasing prices Not recommended for new designs Products considered to be “mature” are about 2 decades into their life cycle High-volume production Multiple suppliers Low prices Newer products are only a few years into their life cycle High performance High level of vendor and supplier support Newest technologies Higher prices

47. 47 Characteristics: TTL and MOS TTL stands for Transistor-Transistor Logic uses BJTs MOS stands for Metal Oxide Semiconductor uses FETs MOS can be classified into three sub-families: PMOS (P-channel) PMOS (P-channel) NMOS (N-channel) NMOS (N-channel) CMOS (Complementary MOS, most common) CMOS (Complementary MOS, most common) Remember:

48. 48 A standard TTL NAND gate circuit Table explaining the operation of the TTL NAND gate circuit TTL Circuit Operation

49. 49 Transistor-Transistor Logic Families Transistor-Transistor Logic Families: 74L Low power 74H High speed 74S Schottky 74LS Low power Schottky 74AS Advanced Schottky 74ALS Advance Low power Schottky

50. 50 Table explaining the operation of the CMOS inverter circuit A CMOS inverter circuit MOS Circuit Operation

51. 51 CMOS Logic Families 40xx/45xxMetal-gate CMOS 74CTTL-compatible CMOS 74HCHigh speed CMOS 74ACTAdvanced CMOS -TTL compatible

52. 52 CMOS Family Evolution CMOS Logic Trend: Reduction of dynamic losses (cross-conduction, capacitive charge/discharge cycles) by decreasing supply voltages: 12V→5V →3.3V →2.5V → 1.8V → 1.5V … Reduction of IC power dissipation is the key to: lower cost (packaging) higher integration improved reliability

53. 53 Comparison of Logic Families vivi vovo

54. 54 Comparison Logic Families

55. 55 Comparison of Logic Families speed power product = a constant