System & Device Tutorial

System & Device Tutorial
TCAM Dynamics System & Device Tutorial Rob Raghavan, Computing and Communications Date June 24, 2010 Rev. 0.00 © 2010 Renesas Electronics America Inc. All rights reserved. 00000-A

Packet Processing Dynamics
© 2010 Renesas Electronics America Inc. All rights reserved.

Packet Switching Networks

Backplane Fabric / FPGA Backplane Fabric / ASIC
Gig E Switch Architecture CPU Packet Processor Chipset Backplane Fabric / FPGA Associated Data Clock Distribution Network (NPU) Buffer SRAM Backplane Fabric / ASIC TCAM Associative Data SRAM ASIC FPGA 3rd party NPU Broadcom Cavium EZChip Marvell Wintegra Xelerated Packets Out Packets In © 2010 Renesas Electronics America Inc. All rights reserved.

Data Packet Analogy Payload Priority Source Address John Q 100 Main St
San Jose, CA 95135 USA Steve B 200 Park Ave New York, NY Destination Address © 2010 Renesas Electronics America Inc. All rights reserved.

Data Packet Description
Packet Header Packet Payload QoS, ACL, VPN, Billing, Flow Monitoring Source & Destination Addresses Malware & Intrusions Data Voice Video Layer 2-4 (SPI) bits Layer 7 (DPI) 5K+ bits 10-40 Gbps Packet HEADER Inspection Layer 2-4 (Network Awareness) 10 Gbps Packet PAYLOAD Inspection Layer 7 (Content Awareness) TCAMs can search all layers in a data packet and determine it’s destination & priority This is becoming more important with Voice, Video, & Data transmissions © 2010 Renesas Electronics America Inc. All rights reserved.

Applications Packet Forwarding Packet Classification
Shallow Packet Inspection (SPI) Packet Classification Deep Packet Inspection (DPI) & SPI The process of categorizing packets into “flows” in an internet router is called packet classification Extracts basic protocol information such as IP addresses (source, destination) © 2010 Renesas Electronics America Inc. All rights reserved.

Forward Information Base (FIB) Search
TCAM Header Payload trailer 2 (Search) Source & Destination Address Associative Data QDR SRAM 3 (Pointer) 4 (Next Switch Address) (Ingress) Network Processor (NPU) NSE Header Payload trailer 1 Unicast Forwarding Multicast Forwarding Forwarding is the relaying of packets from one network segment to another by nodes in a computer network (Egress) Header Payload trailer 5 (Packet sent to next destination) © 2010 Renesas Electronics America Inc. All rights reserved.

Packet Classification Search
TCAM Header Payload trailer 2 (Search) QoS, QoE, ACL, SLA All packets belonging to the same flow obey a pre-defined rule and are processed in a similar manner by the router. Associative Data QDR SRAM 3 (Pointer) 4 (Next Switch Address, QoS, QoE, ACL, SLA) Header Payload trailer 1 (Ingress) Network Processor (NPU) NSE Quality of Service QoS provides preferential delivery service for the applications that need it by ensuring sufficient bandwidth Access Control List An ACL is a common means by which access to and denial of services is controlled (Egress) Header Payload trailer Priority 1 Deny Priority 2 Header Payload trailer Packet filtering Policy routing Accounting & billing Traffic rate limiting Traffic shaping Intrusion detection Packet classification is needed for services that require the capability to distinguish and isolate traffic in different flows for suitable processing. © 2010 Renesas Electronics America Inc. All rights reserved.

The Increasing Need for Packet Processing
 Application Acceleration Protection Malware 10+ Gbps Security ACL Billing QoS IPv6 DRM IPS Layers 2-4 Layers 4-7 © 2010 Renesas Electronics America Inc. All rights reserved.

The Increasing Need for Deep Packet Processing
2005/06 2010 Router ACL VLAN ACL IPSec ICMP Redirect ACL-based RTF TCP-SYN Protection PBR Ctrl plane Policing L2-4 Security Ingress ACL Egress ACL L2-4 QoS Policing Shaping Packetized Voice Video-on-demand IPTV Gaming Policing (per protocol or per TOS byte) Aggregation Level 1 Aggregation Level 2 Mobile services Billing L2-4 Routing IPv4 database IPv6 database L7 Security IPS/IDS Anti-Virus Anti-Spam Unified Threat Mgmt Malware Protection L7 QoS/ Routing Application Acceleration Protocol Identif. Datacenter Load Balancing © 2010 Renesas Electronics America Inc. All rights reserved.

TCAM Architecture & Portfolio

What is a TCAM CAM stands for Content Addressable Memory
In a standard memory device the operating system provides an address, and receives the data stored at the supplied address With a CAM, the operating system supplies the data, and the CAM returns a list of addresses where the data is stored, if it finds any A CAM searches the entire memory in one operation, so it is considerably faster than RAM Any switch capable of forwarding Ethernet frames at line-speed gigabit is using CAMs for lookups Binary CAMs search only for ones and zeros; a simple operation. MAC address tables in switches commonly get stored inside binary CAMs A TCAM is a Ternary CAM. This allows the operating system to match a third state, "X." The X state is a "mask," meaning its value can be anything. This lends itself well to networking, since netmasks operate this way. To calculate a subnet address we mask the bits we don't care about © 2010 Renesas Electronics America Inc. All rights reserved.

TCAM Architecture 0001 1101 0101 1110 1101/20 next-hop 30.40.50.62
XXXX XXXX XXXX © 2010 Renesas Electronics America Inc. All rights reserved.

TCAM Roadmap ASSP CAM Custom CAM ~ CY09 CY10/1H CY10/2H CY11/1H
Quad Search Dual Search Interlaken 360Msps 125Msps 600Msps 20M 18M 80M 125Msps ASSP Dual Search 4.5M 600Msps ASSP 40M Interlaken ASSP CAM 600Msps ASSP 5M Interlaken Custom Custom TCAM Gen 2 –18M Custom Custom TCAM Gen 3 –18M Custom Custom TCAM Gen 4 –20M Custom Custom TCAM Gen 5 –80M Custom Custom TCAM Gen 2 – 4.5M Custom Custom TCAM Gen 3 – 4.5M Custom Custom TCAM Gen 4 – 10M Custom Custom TCAM Gen 5 – 40M Custom Custom TCAM Gen 2– 2.5M Custom Custom TCAM Gen 4 – 5M Custom Custom TCAM Gen 5– 5M Custom CAM © 2010 Renesas Electronics America Inc. All rights reserved.

Renesas TCAM Portfolio
Quad Search TCAM Dual Search TCAM Part number R8A20410BG TBD Density 20M 4.5M 18M Parallel Search Engines 4 banks 2 banks Clock Frequency 360MHz 250MHz Search Mode (bit width) 40b/80/160/320/480/640 72/ 144/ 288 Search Rate Single Quad Single Dual single dual Core Voltage 1.0V+/- 5% I/O Voltage 1.5V +/- 5% (HSTL) 2.5V +/- 5% (SSTL2) Data Bus 80bit (DDR) 72bit (SDR) Package 576pins FCBGA 360pins PBGA 360pins FCBGA Datasheet Now August Models November Sample December Production Q1 2011 © 2010 Renesas Electronics America Inc. All rights reserved.

Quad Search Overview (20Mb TCAM)
Description Comments Capacity 20M Full Ternary CAM 32Blks (80bit x 8K each, 80bit x 256K entries total) Search 4 searches in parallel out of 28 configurable tables. 8 search profiles switchable on-the-fly Search Key 40b L / 40b H / 80b / 160b / 320b / 480b / 640b 40b search uses 80b entry w/special high & low masks Data I/F 80-bit DDR Input only, read data comes from result IND bus Result I/F Single 20-bit Index bus IND Output only Frequency 360MHz Single table 160b = 360 Msps max, quad search 720Msps Context Registers 128 x 320-bit context registers Write Mask 7 write masks Data Block Mask 8 DBM per data block Search Key Config Search Key can be compacted in 80b resolution Valid Bit A Valid bit for each 80b entry WDS Source Synchronous Clock for DDR input signals x3 2 for 80b bus & 1 for controls Clock Signals All complementary clocks Similar to QDR Data Alignment Data Bus center-aligned. Result IND Bus programmable to center or edge-aligned Cascade 2 devices maximum 40Mb total Impedance Control Output Impedance Control ZC similar to QDR ODT On-Die-Termination Can be turned off Parity Interface parity support. 2-bit for D and 1-bit for IND Array parity support plus Array Integrity Scanner to scan for SER 4-bit per 80b segment Latency 26 cycles For cascade mode = = 34 cycles Power 1.0V Core 1.5V HSTL I/O & PLL Package 576 FCBGA © 2010 Renesas Electronics America Inc. All rights reserved.

Quad Search Block Diagram
WDS[0]/WDS#[0] P_THRU PLL CAM_CLK TMS F_SEL TCK JTAG TDI TDO Search Key Configuration TRST PARITY CONTROLLER PARITY_ERR Block31 Block30 OP/TERS[3:0] Priority Encoder For table A RDS/RDS# IND[19:0] Context Register (80bits X 4) Block2 Block1 MAT Block0 Search Key Search Mask CAM Array Priority Encoder For table B O_VD WDS[2:0]/ WDS#[2:0] Priority Encoder For table C D[79:0] DP[1:0] Device Register Priority Encoder For table D C_SEL OP_ENA Write Mask CI_RDS/RDS# Write Data Cascade CI_IND[19:0] CI_MAT RSTL CI_O_VD © 2010 Renesas Electronics America Inc. All rights reserved.

Quad Search Key Configuration
Original Search Key [319:240] [239:160] [159:80] [79:0] TableA SKCR TableB SKCR TableC SKCR TableD SKCR SKCR 1 1 1 1 1 1 1 1 1 319 159 79 159 Internal Search Key [319:240] [239:160] [159:80] [79:0] [319:240] [239:160] [79:0] [319:240] [79:0] 320bit Search Key 160bit Search Key 80bit Search Key 160bit Search Key Based on SKCR selection, 4 individual search keys can be generated, one for each table. © 2010 Renesas Electronics America Inc. All rights reserved.

Quad Search Context Register
Context Registers are effective in reducing I/O bandwidth requirement for long search keys Renesas TCAM has three methods of search key input. 1) From external D-bus 2) From internal Context Register ( consists of 80bit x 4segments ) 3) Combination of external D-bus & internal context Register. From Context Registers From D bus D[79:0] [319:240] [239:160] [159:80] [79:0] [319:240] [239:160] [159:80] [79:0] CR_SEL[6:0] 127 [319:240] [239:160] [159:80] [79:0] [319:240] [239:160] [159:80] [79:0] KS_ENA KS_ENA KS_ENA KS_ENA KS_ENA KS[2:0] KS[2:0] KS[2:0] KS[2:0] KS[2:0] LAST_KS If KS_ENA is “1”, Context register is overwritten by external D-bus. Overwrite OP[3:0] (WM_SEL) (SP_SEL) OP_ENA [319:240] [239:160] [159:80] [79:0] © 2010 Renesas Electronics America Inc. All rights reserved.

Quad Search Cascaded System
WDS/WDS#, OP_ENA, OP, D, DP, CR_SEL, KS, KS_ENA, LAST_KS Input Side CI_RDS/ CI_RDS# RDS/ RDS# CI_RDS/ CI_RDS# RDS/ RDS# CI_IND IND CI_IND IND ASIC/NPU or FPGA CI_O_VD O_VD CI_O_VD O_VD CI_MAT MAT CI_MAT MAT ID 1 ID 1 OALIGN OALIGN CAM-0 CAM-1 Higher priority CAM Lower priority CAM Output Side © 2010 Renesas Electronics America Inc. All rights reserved.

Renesas Value & Differentiation

Custom TCAM Cell Memory cell is the most cost sensitive component in CAM LSI, Renesas’ design is based on customized cell instead of generic rules In any process technology, Renesas CAM array will have a significant die size advantage 1bit cell 1bit cell 1bit cell 130nm TCAM 90nm TCAM 65nm TCAM © 2010 Renesas Electronics America Inc. All rights reserved.

Proprietary Repair Technology
Although TCAM cell is SRAM based, defect density of TCAM cell is about 2x of SRAM Replacing defective cells with redundant cells is not as trivial as in regular memory due to Priority consideration in search Renesas Repair technology is able to bring TCAM yield up to SRAM level © 2010 Renesas Electronics America Inc. All rights reserved.

Sub-Core Pre-charge Technology
Constant pre-charge and discharge of Match-Line Sense Amplifiers during search consumes a lot of power By reducing the sense amp pre-charge voltage to ½ of core voltage, can effectively reduce overall power consumption by 25%. 25% © 2010 Renesas Electronics America Inc. All rights reserved.

TCAM Market & Applications

Markets & Customers TCAM SRAM & DRAM Alcatel-Lucent Avaya Brocade
Core Metro Access/Enterprise Access: Active Ethernet Access Switches IPDSLAM GPON OLT, 10GPON OLT - Core Routers - Multiservice Provisioning Platforms - Carrier Ethernet Switch/Routers - Metro Aggregation Switches Enterprise: Advanced Stackable Switches Enterprise Chassis Switches TCAM SRAM & DRAM Alcatel-Lucent Avaya Brocade Calix Ciena Cisco Cloudshield Enterasys Ericsson Extreme Force10 F5 Networks GEIP HP Huawei Juniper Kontron Nokia/Siemens Palo Alto Tellabs © 2010 Renesas Electronics America Inc. All rights reserved.

TCAM TAM Cisco: 40% ASSP: 60% Cisco: 72% ASSP: 28%

Netlogic Product Portfolio
2005 2006 2007 2008 2009 NSE3128 NL3100 NETL7 NL8000 NL9000 NL7512 NSEX256 NL6000 NL6000XS NLS1005 NLS205 NL33100 CFP3256 NL71024 NL8256 NL71024XT NSEx512 NL3140LV TCAM3 NL56615 NLP10142 NL5000GLQ Netcam Cypress NL3380 NLP1220 TCAM2 NL91024XT IDT Ayama 10000 Aeluros NLS2000 Ayama 20000 Puma SerDes TCAM4 NSE70000 PCI Express PHY route accelerator Sahasra 50000 SATA-II PHY 75S10000A XAUI PHY NLP10000 75S10000B NLP2040 RMI NLP3040 XLP uP XLR Thread uP XLS uP Alchemy uP © 2010 Renesas Electronics America Inc. All rights reserved.

TCAM Cross reference Netlogic Density I/F Renesas NL6128 4.5M 72 bit
Dual Search 4.5M NL7512 20M Dual Search 18M NL9512 80 bit Quad Search 20M R8A20410BG IDT 75P52100 4M 75K72100 18M 75S10020B © 2010 Renesas Electronics America Inc. All rights reserved.

TCAM Ecosystem Partnerships

Backplane Fabric / FPGA Backplane Fabric / ASIC
Gig E Switch Architecture CPU Packet Processor Chipset Backplane Fabric / FPGA Associated Data Clock Distribution Network (NPU) Buffer SRAM Backplane Fabric / ASIC TCAM Associative Data SRAM ASIC FPGA 3rd party NPU Broadcom Cavium EZChip Marvell Wintegra Xelerated Packets Out Packets In © 2010 Renesas Electronics America Inc. All rights reserved.

Cavium Networks OCTEON Roadmap
OCTEON Plus OCTEON II OCTEON III CN7xxx Family cnMIPS III cores Full SW Compatibility 2X+ Performance Application Acceleration V4 50%+ reduction in Power Consumption CN68XX Up to 1500 MHz 16-32 cnMIPS II cores 4MB L2 Cache, 4xDDR3 Cores CN58xx Up to 800 MHz 4-16 cnMIPS64 cores 2MB L2 Cache CN66XX Up to 1500 MHz 8-16 cnMIPS II cores 4MB L2 Cache, 2xDDR3 8 - 16 Cores CN38xx Up to 600 MHz 4-16 cnMIPS64 cores 1MB L2 Cache CN56xx Up to 800 MHz 6-12 cnMIPS64 cores 2MB L2 Cache CN36xx Up to 600 MHz 6 cnMIPS64 cores 512KB L2 Cache CN54xx Up to 700 MHz 4-6 cnMIPS64 cores 1MB L2 Cache CN63XX Up to 1500 MHz 2-6 cnMIPS II cores 2MB L2 Cache, 1xDDR3 2 - 8 Cores CN31xx Up to 500 MHz 1-2 cnMIPS64 cores 256KB L2 Cache CN52xx Up to 800 MHz 2-4 cnMIPS64 cores 512KB L2 Cache CN62XX Up to 1500 MHz 2-4 cnMIPS II cores 1MB L2 Cache, 1xDDR3 1 - 2 Cores CN30xx Up to 500 MHz 1-2 cnMIPS64 cores 64-128KB L2 Cache CN50xx Up to 700 MHz 1-2 cnMIPS64 cores 128KB L2 Cache CN60XX Up to 1000 MHz 2 cnMIPS II cores 256KB L2 Cache, 1xDDR3 Production Sampling In Design Planned © 2010 Renesas Electronics America Inc. All rights reserved.

Xelerated & Cavium Xelerated HX NPU Cavium Octeon NPU L2-4 processing
L2 - L7 processing Line Card Tables, counters, meters L4-L7 Pizzabox Table Memories SRAM Buffer Memories (HX330) Tables, counters, meters SRAM DRAM DRAM DRAM SRAM Buffers TCAM DRAM SRAM Cavium CN58XX CN68xx Buffers TCAM DRAM HX320 HX330 DRAM Buffers (HX330) 4x SGMII or XAUI Stack i/f TCAM DRAM HX320 HX330 TCAM DRAM Fabric I/F Fabric VOQ Stack i/f HX320 HX330 Fabric I/F Fabric VOQ HX320 HX330 Fabric I/F Fabric VOQ 48x SGMII Octal PHYv 6 Octal PHY CPU 48 RJ45 RJ45 RJ45 RJ45 L2-L4 Security Router ACL VLAN ACL IPSec ICMP Redirect L7 Security IPS/IDS Anti-Virus Anti-Spam L2-4 QoS Policing Shaping Packetized Voice L7 QoS Application Acceleration Protocol Identification . Datacenter Load Balancing © 2010 Renesas Electronics America Inc. All rights reserved.

Questions for Customers
What is their application? What density is required? (e.g. 20Mbit table size) What performance is required? (MSPS – million searches per second) What is the search key width? What is the I/O frequency / Type (e.g. 360MHz, 1.5V HSTL) What is the design power budget? Are they willing to cascade devices for increased density? Are they currently using a TCAM. If so what are its characteristics (performance, density, pinout, power, interface) What type of Network Processor (NPU) is used (ASIC, FPGA, or commercial NPU from Cavium, Broadcom, Xelerated, etc) © 2010 Renesas Electronics America Inc. All rights reserved.

Renesas TCAM Value Proposition
Let them know that Renesas has deep experience in TCAM design & production We are a leading supplier of proprietary TCAMs to the world’s largest network equipment vendor We have patented technology that significantly reduces cost and power Explain that Renesas has leveraged this experience to introduce the 20M Quad Search TCAM to the general market Explain that Renesas has a rich roadmap that will cover multiple densities and performance levels Explain that Renesas is partnering with leading NPU vendors Cavium and Xelerated for interoperability Explain that only Renesas offers both TCAM and other high speed memory like QDR SRAM and LLDRAM © 2010 Renesas Electronics America Inc. All rights reserved.

Find Cavium & Xelerated NPU based designs
Call to action Focus on networking equipment vendors (similar to Alcatel, Juniper, Brocade, Extreme, etc) Find Cavium & Xelerated NPU based designs Target high end Enterprise, Metro, Core Switches & Routers All TCAM datasheet / model / pricing requests should be sent to , Make sure to get an NDA signed Find out if they use QDR/DDR SRAM or LLDRAM for packet buffering and packet lookup © 2010 Renesas Electronics America Inc. All rights reserved.

SPI - Forwarding Table Dynamics
In an Internet router, we find the next hop address for a packet by performing a Longest Prefix match (LPM) on the forwarding table Assume (IPv4) forwarding table has 4 entries as follows: /13 next-hop /8 next-hop /20 next-hop */0 next-hop Ingress packet has (IPv4) destination address: LPM gives us the correct next hop : © 2010 Renesas Electronics America Inc. All rights reserved.

SPI - Statistical vs Hardware Search
Several statistical data structures can be used in the implementation of longest prefix match. For example : PATRICIA Level and/or Path Compressed Tries Skip Lists Hash Tables As number of prefixes in forwarding table increases, the trie becomes larger and lookups take longer ASICs that use tries—digital trees for storing strings (in this case, the prefixes)—require four to six memory accesses for a single route lookup and thus have higher latencies TCAMs are able to accomplish deterministic, single-cycle search © 2010 Renesas Electronics America Inc. All rights reserved.

SPI – ACL / QoS Access Control List (ACL) Quality of Service (QoS)
Network security systems operate by allowing selective use of services An ACL is a common means by which access to and denial of services is controlled On network devices such as Routers and firewalls, they act as filters for network traffic Quality of Service (QoS) QoS provides preferential delivery service for the applications that need it by ensuring sufficient bandwidth QoS allows the use of existing resources efficiently and ensure the required level of service without reactively expanding or over-provisioning their networks © 2010 Renesas Electronics America Inc. All rights reserved.

DPI (L4-L7) DPI can be evoked to look through Layer 2-7
This includes headers and data protocol structures as well as the actual payload of the message DPI can identify and classify traffic based on a signature database that includes information extracted from the data part of a packet, allowing finer control than classification based only on header information Lawful intercept -Obtaining communications network data pursuant to lawful authority Policy definition and enforcement - Service providers obligated by the service level agreement (SLA) with their customers to provide a certain level of service, and at the same time enforce an acceptable use policy Targeted advertising - monitor web-browsing habits in a very detailed way allowing them to gain information about their customers' interests Quality of service (QoS) - ensure equitable bandwidth to all users by preventing network congestion. Higher priority can be allocated to a VoIP or video conferencing call which requires low latency versus web browsing which does not Tiered services - implement tiered service plans, to differentiate "walled garden" services from "value added" DPI can be effective against buffer overflow attacks, Denial of Service (DoS) attacks, sophisticated intrusions © 2010 Renesas Electronics America Inc. All rights reserved.

DPI Market Demand DPI is key for ISPs and carriers for the deployment of triple play and new services Analyze their current network situations and their readiness to receive rich, demanding, consuming and real time traffic Analyze their subscribers' behavior, such as traffic patterns generated per hour/day/week and measure the over-the-top services being used by subscribers To set up global application control policies - such as the total quantity of P2P or VoIP/Skype traffic To set up per subscriber SLAs/policies, in order to enforce smarter services, volume/duration-based billing, be more competitive, provide better Quality of Experience (QoE), and increase ARPU. © 2010 Renesas Electronics America Inc. All rights reserved.

Revenue YoY Growth Market Cap $0.32B $0.75B $1.17B $0.98B $1.03B
28% 19% 77% YoY Growth IPO July 2004 Market Cap $0.32B $0.75B $1.17B $0.98B $1.03B $1.28B © 2010 Renesas Electronics America Inc. All rights reserved.

TCAM4 for Cisco Platforms
Device Type ERBU Edge Routing CRBU Core Routing GSBU Gigabit Systems DSBU Desktop Switching 5M FP-5G Mara/MaraCR Spiderwoman Juhani Whales 10M FP-10G Luke/Barry/Flash Callista 20M FP-20G FP-40G Taiko 80M Obelisk/Getafix © 2010 Renesas Electronics America Inc. All rights reserved.

How OSI Works The main idea in OSI is that the process of communication between two end points in a telecommunication network can be divided into layers Each layer adding its own set of special, related functions. Each communicating user or program is at a computer equipped with these seven layers of function. So, in a given message between users, there will be a flow of data through each layer at one end down through the layers in that computer At the other end, when the message arrives, another flow of data up through the layers in the receiving computer and ultimately to the end user or program. © 2010 Renesas Electronics America Inc. All rights reserved.

Cavium Networks Overview
Founded NASDAQ (CAVM) IPO 2007 500 Employees 2009: $101M revenues, 16% YoY growth Strong Balance Sheet and Financials: $66+M Cash, No Debt – strong cash flow Pioneer and leader in Embedded Multi-core processors Addressing Multi-billion dollar Networking, Communications, Broadband and Consumer markets. MIPS and ARM based Processor SOCs 10 / 10 Top Networking and Security Vendors use Cavium Intelligent Processors for Networking, Wireless, Storage and Video 54 © 2010 Renesas Electronics America Inc. All rights reserved. 54

OCTEON™ Plus CN58XX Product Family
Core: MHz 4 , 8, 12, or 16 cores 32K-I, 16K-D L1 Cache, 2K Write Buffer w/ Auto Single Bit Error Correction 2MB L2 Cache w/ ECC Memory Controllers: 72/144b DDR2-800, 16GB Max, ECC 2x 18bit RLDRAM2 , 1GB Max. (Opt) Flexible High-Speed Interfaces: 2x [4x RGMII or SPI 4.2] 133MHz 64b PCI-X On-chip Coprocessors: Crypto Security, RNG, TCP/IP & Timer Offload, RegEx (DPI), De/Compression (ZIP), DMA, Secure Key Storage Data Plane Acceleration: Schedule/Synchronize/Order (SSO), Packet Input Processor (PIP/IPD), Packet Output Processor (PKO), Free Pool Allocator (FPA) Max Power: W Process Technology: 90nm TSMC Samples: Now Production: Now Package: 1521 FCBGA Optional 2x18-bit RLDRAM2 SPI 4.2 or 4x RGMII 32x RegEx Engines Hyper Access Low Latency Memory Controller Packet Interface Secure Vault MIPS64 r2 Integer Core Packet 32K Icache 16K Dcache 2K Write Buffer Crypto Security MIPS64 r2 Integer Core Packet 32K Icache 16K Dcache 2K Write Buffer Crypto Security CN58XX 4 to 16 cnMIPS64 cores Scheduler/ Sync. Order Boot/ Flash, CF, GPIO, DUART, I2C Misc I/O 64-bit 133MHz PCI-X Packet Input TCP Unit I/O Bridge Coherent, Low Latency Interconnect Compress /Decomp 2MB Shared L2 Cache Hyper Access Memory Controller SPI 4.2 or 4x RGMII Packet Output Packet Interface I/O Bus Device cnMIPS Cores CN5830 4 CN5840 8 CN5850 12 CN5860 16 DDR2 up to 800MHz 72 or 144-bit wide w/ECC LP: Low Power version available for 600MHz I: Industrial temp versions available © 2010 Renesas Electronics America Inc. All rights reserved.

OCTEON II CN68XX Product Family
2x 72b If x4 If x8 x20 Gen2 SERDES TCP DMA FPA Timers XAUI/DXAUI Or 4x SGMII Interlaken (ILK-LA Pass 2) PCIe v2 2x RXAUI or 1x XAUI XAUI/DXAUI or 4x SGMII XAUI or 4x SGMII RAID/ XOR Compression /Decomp v3 Secure Vault Power Optimizer HFA (Pattern Matching) Application Acceleration Manager Misc I/0 I/O Network Coproc Network Packet Input v2 Packet Output v2 2x Hyper Access Memory Controller v2 x4 4MB Shared L2 Cache CN68XX 16-32 cnMIPS II cores Crypto Security Packet 37K Icache 32K Dcache Write Back Buffer MIPS64 r2 Integer Core Boot/Flash (NOR & NAND), CF, 16 GPIO, DUART, 2x I2C, 1x USB 2.0 w/PHY, 1xRG/MII Key Features 16 to 32 cnMIPSII cores MIPS64 R enhanced instructions Up to 37 way L1 associativity Hyperconnect Crossbar & I/O interconnect with up to 8Tbps Low latency deterministic performance Most Advanced HW acceleration including: 40Gbps+ security, TCP, packet processing, QoS 15Gbps 3rd gen DPI 20Gbps+ Compression 80Gbps+ RAID/XOR/DeDup Schedule/Synch ordering engine for unlimited flows Fully SW compatible with OCTEON Plus Power Optimizer Embedded Virtualization SCP = Secure Communications Processor: Includes encryption, networking, TCP acceleration and QoS AAP = Application Acceleration Processor: Includes SCP features plus HFA RegEx acceleration and compression/decompression © 2010 Renesas Electronics America Inc. All rights reserved.

HX330 Family HX320 Family HX310 Family

Current Products 40G Network Processors
X10q (20G full-duplex; SPI-4.2) X11 (10/20G full duplex; SPI-4.2, GE, 10GE) Metro Ethernet Switch Xelerated/Dune Metro Ethernet Switch (24xGE + 2x10GE uplink) Reference Design Kits X10q RDK X11 RDK Metro Ethernet Reference Application Forwarding plane for PB, PBB, VPLS, MPLS, IPv4 and IPv6 Software Development Kit Integrated Development Environment (editor, compiler, linker, debugger, ...) Clock-cycle Accurate Simulator Services Training, Application coding, Integration services Xelerated’s complete product portfolio. Roadmap focused on core competence (data processing in layers 2-4) for continued price/performance leadership in high-volume Ethernet markets. © 2010 Renesas Electronics America Inc. All rights reserved.

Enterprise Chassis System
Line Card SRAM Fabric I/F Fabric VOQ HX320 HX330 DRAM TCAM Tables, counters, meters Buffers Fabric Card A Enterprise Chassis System Line Card SRAM Fabric I/F Fabric VOQ HX320 HX330 DRAM TCAM Tables, counters, meters Buffers Line Card Line Card Tables, counters, meters Line Card Tables, counters, meters Tables, counters, meters SRAM DRAM SRAM Buffers DRAM SRAM Buffers TCAM DRAM DRAM Buffers (HX330) TCAM DRAM HX320 HX330 TCAM DRAM Fabric I/F Fabric VOQ HX320 HX330 Fabric I/F Fabric VOQ Fabric Card B HX320 HX330 XAUI+, HiGig 48x SGMII 48x Base-X Serdes 5xXAUI 40G Interlaken XFP/SFP+ Octal PHY Octal PHY SFP optics XAUI- XFI RJ45 Octal PHY XFP/SFP+ 40G MAC or Framer SFP optics XFP/SFP+ 40G opto XAUI- XFI Octal PHY Octal PHY XFP/SFP+ Octal PHY SFP optics XFP/SFP+ Copper Ethernet 48x GE 48x FE 16x 2.5GE Optical Ethernet: 48x GE 48x FE 16x 2.5GE 10GE optical: 5x 10GE 40GE or OC768 © 2010 Renesas Electronics America Inc. All rights reserved.

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