1. Hardware design considerations: fan-in, fan-out, critical paths, hazards (summary)

2. For custom circuits (ASICS), have to pay attention to both physical and logical (“design”) faults Physical faults can be caused by fabrication errors or by such factors as circuit aging, chip damage, or environmental stresses (temperature, vibration, power glitches, etc.) Assuming adequate design rules are followed, logical faults are due to design errors For FPGAs, fabrication errors do not need to be tested for. But design choices can lead to errors such as too long a critical path, for example. In any project (hardware, software, or a mix) errors can be reduced by following a DFT (Design for Test) strategy, which emphasizes awareness of possible faults and the need to provide adequate testing to identify and remove faults

3. Main issues in performance of combinational logic: The world is ANALOG, not digital; even in designing combinational logic, we need to take analog effects into account Software doesn’t change but hardware does: --different manufacturers of the same component --different batches from the same manufacturer --environmental effects --aging --noise main areas of concern: --signal levels (“0”, “1”—min, typical, and max values; fan-in, fan-out) --timing—rise & fall times; propagation delay; hazards and race conditions --physical (fabrication) faults: “stuck-at”, bridging --how to deal with effects of unwanted resistance, capacitance, induction

4. Race conditions and hazards (“glitches”) Critical: state or output depends on order of arrival at decision point Noncritical: output value does not depend on order of arrival of inputs Hazard: (also called a decoding spike or a glitch): present if the circuit has the possibility of giving an incorrect output 2 types of hazards: Static: glitch may occur because of race between 2 or more input signals when output expected to remain at steady level Static-0: may produce erroneous 1; static-1: the opposite Dynamic: output may erroneously change more than once as result of one single input transition

5. fig_02_14 Examples: static-0 hazard: Extra delay through inverter Static-1 hazard: Adding buffers to match delays Will not work because of Parameter variations occurring In real physical parts

6. fig_02_15 Additional examples for analysis:

7. fig_02_16_01

8. fig_02_16_02

9. fig_02_17 Example: dynamic hazard One slow path and one fast path; other devices are assumed to have typical delays, all of the same value If B 0  1 there will be 3 state changes in the output before it settles

10. fig_02_18

11. “LEGACY OF THE EARLY PHYSICISTS”: RESISTANCE, CAPACITANCE, COUPLING (“micro view”, passive components) Ampere: current flowing in a wire produces magnetic field Faraday, Lenz: wire moving in magnetic field has induced current Gauss et al.: capacitance Situations to examine: Coupling between two adjacent wires Mutual capacitance between adjacent circuits …etc.

12. fig_02_19 PHYSICAL PROPERTIES: RESISTANCE R R = r * (L / A) Q: what does this say about: --length of wires? --feature sizes? --noise margins for low voltage? fig_02_20 Modeling resistance (first-order model, includes inherent parasitic devices): for DC, L and C can be ignored; but in our circuits we will have time- varying signals We are assuming a lumped system (all resistance considered to be “lumped” at one node) For a distributed system we would look at R(x)dx, L(x)dx, C(x)dx

13. fig_02_22 Capacitance: C =  A/d Many instances of capacitors on chip: --Power/ground planes --parallel wires --adjacent pins --etc. Example: part of signal in top wire shows up as noise in adjacent wire: As circuit feature sizes get smaller and smaller, these effects become more and more important fig_02_23

14. fig_02_24 First-order (lumped) model: For small feature sizes, may need to look at much more complex distributed model fig_02_25

15. fig_02_26 How do these effects change logic circuit? Example: 2 inverters in series Resistor: connecting path Capacitor: device, wire, IC package, coupling to other devices V OUT (s) = [1/Cs] / [R + 1/Cs] * V(s) IN = [1/(RCs+1)] * V(s) IN = [1/(RCs+1)] * [V IN /s] for V IN a step function V OUT (t) = V IN (1-exp(-t/RC)) Rise (and fall) times are slowed Components can be damaged or Data rate can be reduced fig_02_27: interconnect fig_02_28:interco nnect, driver fig_02_29: rise time

16. fig_02_33 Example: why you should never leave Gate inputs floating (using a 3-input AND gate for a 2-input application): 3 methods: 1 2 3 fig_02_34 1: V OUT (s) = C 1 /(C 1 +C 2 )*V IN (s); If voltage too low, output is always 0 2.Cap = C1 + C2 This doubles time constant, reduces rise/fall time; can give metastable behavior on switching 3. State of unused pin defined by pullup resistor, this will work fig_02_35

17. fig_02_36 Second-order: add parallel inductor This adds a damping factor: Natural frequency w n = 1/ (LC) 1/2 ; damping d = (R/2) * (L/C) 1/2 d < 1: underdamped—can have oscillation, noise; d = 1: damped okay; d > 1: overdamped—can have metastability fig_02_37

18. Structural faults: Stuck-at model: (a single fault model) s-a-1; s-a-0; may be because circuit is open or there is a short

19. fig_02_44 Bridging fault: bad connections, broken flakes, errant wire pieces

20. fig_02_45 Examples of bridging faults

21. fig_02_46 Bridging faults can be feedback or non-feedback faults Non-feedback faults Between input or output and power rail: use stuck-at model Between signal traces or logic pins: inputs: model as common signal to both inputs internal: who wins?

22. fig_02_47 Modeling a “competitive” fault: result of fault depends on logic family being used

23. fig_02_48 Feedback bridging faults: Number of inversions is important Circuit ACircuit B In A there are an odd number of inversions on the path; this can cause oscillation; can sometimes be modeled as competing signals In B there are an even number of inversions; this can often be modeled as a stuck-at fault

24. fig_02_49fig_02_50 Functional faults: Example: hazards, race conditions Two possible methods: A: consider devices to be delay-free, add spike generator B: add delay elements on paths Method AMethod B As frequencies increase, eliminating hazards through good design is even more important

25. Finite State Machines and Sequential Logic (Memory faults: we will not discuss these here)

26. fig_03_08 Finite state machine (FSM): High-level view Moore machine: output is a function of the present state only Mealy machine: output is a function of the present stare and the inputs

27. fig_03_23,3_24 “Dividers”: slow clock down, e.g. Simple divide-by-2 example

28. fig_03_25, 03_26, 03_27 Example: Asynchronous divide- by-4 counter [asynchronous 2-bit binary upcounter; ripple counter] Note: asynchronous because flip-flops are changed by different signals Note: if 1 st stage output appears at time t0 + m, nth stage output appears at time t0 + nm; so this configuration is good for dividing the signal but using it as a ripple counter is prone to static and dynamic hazards Both outputs change:

29. fig_03_28, 03_29 Synchronous dividers and counters (preferred): Example: 2-bit binary upcounter Inputs: D A = not A D B = A xor B

30. fig_03_30, 03_31, 03_32, 03_33 Johnson counter (2-bit): shift register + feedback input; often used in embedded applications; states for a Gray code; thus states can be decoded using combinational logic; there will not be any race conditions or hazards

31. fig_03_34 3-stage Johnson counter: --Output is Gray sequence—no decoding spikes --not all 2 3 (2 n ) states are legal—period is 2n (here 2*3=6) --unused states are illegal; must prevent circuit from ever going into these states

32. Making actual working circuits: Must consider --timing in latches and flip-flops --clock distribution --how to test sequential circuits (with n flip- flops, there are potentially 2 n states, a large number; access to individual flipflops for testing must also be carefully planned)

33. fig_03_36, 03_37 Timing in latches and flip-flops: Setup time: how long must inputs be present and stable before gate or clock changes state? Hold time: how long must input remain stable after the gate or clock has changed state? Metastable oscillations can occur if timing is not correct Setup and hold times for a gated latch enabled by a logical 1 on the gate

34. fig_03_38 Example: positive edge triggered FF; 50% point of each signal

35. fig_03_39, 03-40 Propagation delay: minimum, typical, maximum values--with respect to causative edge of clock: Latch: must also specify delay when gate is enabled:

36. fig_03_41, 03_42 Timing margins: example: increasing frequency for 2-stage Johnson counter –output from either FF is 00110011…. assume t PDLH = 5-16ns t PDLH =7-18ns t su = 16ns

37. Case 1: L to H transition of Q A Clock period = t PDLH + t su + slack 0  t PDLH + t su If t PDLH is max, Frequency F max = 1/ [5 + 16)* 10 -9 ]sec = 48MHz If it is min, F max = 31.3 MHz Case 2: H to L transition: Similar calculations give F max = 43.5 MHz or 29.4 MHz Conclusion: F max cannot be larger than 29.4 MHz to get correct behavior

38. Clocks and clock distribution: --frequency and frequency range --rise times and fall times --stability --precision

39. fig_03_43 Clocks and clock distribution: Lower frequency than input; can use divider circuit above Higher frequncy: can use phase locked loop:

40. fig_03_44 Selecting portion of clock: rate multiplier

41. fig_03_46 Note: delays can accumulate

42. fig_03_47 Clock design and distribution: Need precision Need to decide on number of phases Distribution: need to be careful about delays Example: H-tree / buffers