55:035 Computer Architecture and Organization

Name: 55:035 Computer Architecture and Organization
Uploaded: 2017-08-24T11:12:38+00:00
Duration: PTM53S41
Channel: Meagan Evans
Description: 55:035 Computer Architecture and Organization

55:035 Computer Architecture and Organization
Lecture 3

Outline RISC and CISC Comparison Instruction Set Examples ARM Freescale 68K Intel IA-32 55:035 Computer Architecture and Organization

RISC and CISC Reduced Instruction Set Computer Fixed length instructions Simpler Instructions Fewer cycles per instruction Load/Store memory access Register operands only Probably doesn’t have microcode RISC is a misnomer – may have many instructions Complex Instruction Set Computer Variable length instructions More complex Instructions More cycles per instruction May have “orthogonal” instruction set Memory and register operands May have microcode 55:035 Computer Architecture and Organization

ARM “Advanced RISC Machines” Over 90 ARM processors are shipped every second – more than any other 32-bit processor IP supplier ARM licenses its technology to more than 200 semiconductor companies. Eight product families 55:035 Computer Architecture and Organization

ARM Example ARM CortexTM-A8 processor Intellectual Property (IP) Core licensed by other companies to create “System On a Chip” (SOC) Dual, symmetric, in-order issue, 13-stage pipelines Integrated L2 cache 55:035 Computer Architecture and Organization

ARM Register Structure
15 General Purpose Registers R14 also link register By convention R12 frame pointer R13 stack pointer Current Program Status Register 15 banked registers copied/restored when going to/from User/Supervisor 31 29 7 Program counter R0 R1 R14 Status 28 R15 (PC) 30 6 4 CPSR N - Negative Z - Zero C - Carry V- Overflow Condition code flags Processor mode bits register Interrupt disable bits General purpose registers 15 55:035 Computer Architecture and Organization

ARM Instruction Format
Condition 31 OP code 28 27 20 19 16 15 12 11 4 3 R n d Other info m Load/store architecture (RISC) Conditional execution of instructions One or two operands (register) Destination register See appendix B 55:035 Computer Architecture and Organization

ARM Addressing Modes Name Assembler syntax Addressing function W ith immediate of fset: Pre-inde x ed [R n , #of fset] EA = ] + fset with writeback fset]! fset; R Post-indexed ], ]; magnitude in m : shift] shifted shift]! shifted; shift Relati v e Location (Pre-inde [PC] fset)   where: EA = effective address offset = a signed number contained in the instruction shift = direction #integer, where direction is LSL for left shift or LSR for right shift, and integer is a 5-bit unsigned number specifying the shift amount +/- Rm = the offset magnitude in register Rm can be added to or subtracted from the contents of base register Rn 55:035 Computer Architecture and Organization

ARM Relative Addressing Mode
LDR R1,ITEM Pre-indexed mode with immediate offset PC is base register Calculated offset = 52 PC will be at 1008 when executed 52 = offset 1000 word (4 bytes) ITEM = 1060 Operand Memory address updated [PC] = 1008 * LDR R1, ITEM 1004 1008 - 55:035 Computer Architecture and Organization

ARM Pre-indexed Mode STR R3,[R5,R6] Pre-indexed mode base register = R5 offset register = R6 1000 200 = offset 1200 Base register 200 Offset register * STR R3, [R5, R6] R5 R6 Operand 55:035 Computer Architecture and Organization

ARM Post-indexed Mode w/ WB
LDR R1,[R2],R10,LSL #2 Use in loop LSL #2 is logical shift left by 2 bits => x4 1st pass: R1 <- [R2] 2nd pass: R1 <- [[R2] + [R10] x 4] R2 <- [R2] + [R10] x 4 3rd pass: R1 <- [[R2] + [R10] x 4] and so on 100 = 25 x 4 1000 word (4 bytes) 25 Base register * 6 1100 R2 -17 321 1200 Offset register R10 Memory address Load instruction: LDR R1,[R2],R10,LSL #2 55:035 Computer Architecture and Organization

ARM Pre-indexed Mode w/ WB
STR R0,[R5, #-4]! Push instruction R5 is SP Immediate offset of -4 is added to [R5] TOS = 2008 2008 2012 Base register (Stack pointer) R0 R5 27 - after execution of Push instruction Push instruction: STR R0,[R5,#-4]! 55:035 Computer Architecture and Organization

ARM Instructions All instructions can be executed conditionally b31-28 of instruction Most instructions have shift and rotate operations directly implemented in them barrel shifter Load/store multiple instructions LDMIA R10!,{R0,R1,R6,R7} R0 <- [R10], R1 <- [R10]+4, R6 <- [R10]+8, R7 <- [R10]+12 R10 <- [R10] + 16 Condition code set by “S” suffix 55:035 Computer Architecture and Organization

ARM Instructions Arithmetic Opcode Rd,Rn,Rm ADD R0,R2,R4 => R0 <- [R2] + [R4] ADD R0,R3,#17 => R0 <- [R3] + 17 immediate value in b7-0 SUB R0,R6, R5 => R0 <- [R6] – [R5] ADD R0,R1,R5,LSL #4 => R0 <- R1+[R5]x16 MUL R0,R1,R2 => R0 <- [R1] X [R2] MLA R0,R1,R2,R3 => R0 <- [R1]X[R2]+[R3] ADDS R0,R1,R2 => R0 <- [R1] + [R2] Sets condition codes NCZV 55:035 Computer Architecture and Organization

ARM Instructions Logic Opcode Rd,Rn,Rm AND R0,R2,R4 => R0 <- [R2] ^ [R4] BIC R0,R0,R1 => R0 <- [R0] ^ ~[R1] MVN R0,R3 => R0 <- ~[R3] BCD Pack Program LDR R0,POINTER Load address LOC in to R0. LDRB R1,[R0] ASCI I c haracters R2,[R0,#1] R1 and R2. AND R2,R2,#&F Clear high-order 28 bits of ORR R2,R2,R1,LSL #4 Or [R1] shifted left [R2]. STRB R2,PACKED Store pac k ed BCD digits P A CKED. 55:035 Computer Architecture and Organization

ARM Instructions Branch Contain 2’s complement 24-bit offset Condition to be tested is in b31-28 BEQ LOCATION BGT LOOP Condition 31 OP code 28 27 Offset 24 23 (a) Instruction format 1000 LOCATION = 1100 BEQ LOCATION Branch target instruction 1004 updated [PC] = 1008 Offset = 92 55:035 Computer Architecture and Organization

ARM Assembly Language Memory Addressing address or data lab el Operation information AREA CODE ENTR Y Statements that LDR R1,N generate R2,POINTER mac hine MOV R0,#0 instructions LOOP R3,[R2],#4 ADD R0,R0,R3 SUBS R1,R1,#1 BGT STR R0,SUM Assembler directives D ATA SUM DCD N 5 POINTER NUM1 3, 17,27, 12,322  Assembler directives 55:035 Computer Architecture and Organization

ARM Subroutines Example 1 Parameters passed through registers Branch and Link instruction (BL) Calling program LDR R1,N R2,POINTER BL LIST ADD STR R0,SUM . Subroutine STMFD R13!, { R3,R14 } Sa v e R3 and return address in R14 on stac k, using R13 as the k p oin ter. MO V R0,#0 LOOP R3,[R2],#4 R0,R0,R3 SUBS R1,R1,#1 BGT LDMFD R3,R15 Restore load to PC (R15). 55:035 Computer Architecture and Organization

ARM Subroutines Example 2 Parameters passed on stack (Assume top of stack is at level 1 b elo w.) Calling program LDR R0,POINTER Push NUM1 STR R0,[R13,# 4]! on stack. R0,N n BL LIST ADD R0,[R13,#4] Mo v e the sum in to R0,SUM memory lo cation SUM. R13,R13,#8 Remo parameters from . Subroutine STMFD R13!, { R0 R3,R14 } Sa registers. R1,[R13,#20] Load R2,[R13,#24] MO V R0,#0 LOOP R3,[R2],#4 R0,R0,R3 SUBS R1,R1,#1 BGT R0,[R13,#24] Place LDMFD R3,R15 Restore registers and return. – [R0] [R1] [R2] [R3] Return Address n NUM1 Lev el 3 2 1  55:035 Computer Architecture and Organization

ARM Program Example Byte sorting program C program Assembly program for (j = n 1; j > 0; 1) { ( k 1 ) if (LIST[ ] LIST[ ] ) TEMP ]; TEMP; } – ADR R4,LIST Load list p oin ter register R4, LDR R10,N and initialize outer lo op base ADD R2,R4,R10 R2 to LIST + n . R5,R4,#1 1 in R5. OUTER LDRB R0,[R2,# 1]! LIST( j ) R0. MO V R3,R2 Initialize inner R3 1. INNER R1,[R3,# k R1. CMP R1,R0 Compare ). STR GTB R1,[R2] If > ), swap R0,[R3] ), GT R0,R1 mo v e (new) R3,R4 0, rep eat BNE op. R2,R5 1, – 55:035 Computer Architecture and Organization

Freescale 68K Freescale Semiconductor formerly Motorola Semiconductor There are more than 17 billion Freescale semiconductors at work all over the planet. Automobiles, computer networks, communications infrastructure, office buildings, factories, industrial equipment, tools, mobile phones, home appliances and consumer products About 20 microprocessor families 55:035 Computer Architecture and Organization

68K 68K Family 68000: Introduced in 1979, 16 bit word length and 8/16/32 bit arithmetic, 24 bit address space (16 MB) 68008: 8 bit version of the with 20 bit address space 68010: Version of the supporting virtual memory and virtual machine concepts 68020: Extended addressing capabilities, 32-bit, i-cache 68030: Data cache in addition to the instruction cache, on-chip memory management unit 68040: Floating-point arithmetic, pipelining, . . . “ColdFire” family added in 1994 V1 through V5 cores 55:035 Computer Architecture and Organization

68K Example ColdFire V5 Core 55:035 Computer Architecture and Organization

68K Register Structure Word Byte Supervisor stack pointer Long word User stack pointer PC 31 15 7 8 16 Program counter pointers Stack registers Data Address D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 8 32-bit Data Registers 8 32-bit Address Registers A7 is Stack Pointer Separate Supervisor and User pointers Users cannot execute privileged instructions Status Register 15 13 10 8 4 SR Status register Carry Overflow Zero Negative Extend Trace mode select Supervisor mode select Interrupt mask - T S I X Z N V C 55:035 Computer Architecture and Organization

68K Instruction Format src 1 dst OP code size 5 8 11 12 15 9 7 6 Three operand sizes: Byte, Word, Long Word All addressing modes supported (CISC) One or two operands See appendix C 55:035 Computer Architecture and Organization

68K Addressing Modes Name Assem bler syn tax Addressing function Immediate #V alue Op erand = V Absolute Short EA Sign Extended WV Long Register Rn R n that is, [R ] Indirect (An) [A Autoincremen t (An)+ ]; Incremen A Auto decrement Decremen ; Indexed basic alue(An) + full BV alue(An,Rk.S) +[R k Relativ e alue(PC) [PC] or Lab el alue(PC,Rk.S) (Rk) – where: EA = effective address Value = a number given either explicitly or represented by a label BValue = an 8-bit Value WValue = a 16-bit Value An = an address register Rn = an address or a data register S = a size indicator 55:035 Computer Architecture and Organization

68K Instructions Format – see appendix C Opcode src,dst Opcode src Arithmetic examples ABCD, ADD, ADDA, ADDI, ADDQ, ADDX DIVS, DIVU, MULS, MULU SBCD, SUB, SUBA, SUBI, SUBQ, Logic examples AND, ANDI, EOR, EORI NBCD, NEG, NEGX, NOP, NOT, OR, ORI, SWAP 55:035 Computer Architecture and Organization

68K Instructions Shift examples ASL, ASR, BCHG, EXT, LSL, LSR ROL, ROR, ROXL, Bit test and compare BCLR, BSET, BTST, TAS, TST CMP, CMPA, CMPI, CMPMEXG Branch examples JMP, JSR, RESET, RTE, RTR, RTS, STOP, TRAP, TRAPV Memory load and store examples LEA, PEA, LINK, UNLINK MOVE, MOVEA, MOVEM, MOVEP, MOVEQ 55:035 Computer Architecture and Organization

68K Assembly Language R0 Clear R0,SUM R1 (R2)+,R0 Initialization Move LOOP Add Decrement #NUM1,R2 N,R1 Branch>0 MO VE.L N,D1 Put n 1 in to the SUBQ.L #1,D1 counter register D1 VEA.L #NUM1,A2 CLR.L D0 LOOP ADD.W (A2)+,D0 DBRA D1,LOOP Loopback until [D1]= –1. D0,SUM – 55:035 Computer Architecture and Organization

68K Subroutines Calling program MO VE.L #NUM1, (A7) Push parameters onto stack. N, BSR LIST ADD 4(A7),SUM Save result. ADDI.L #8,A7 Restore top of stack. . Subroutine VEM.L D0 D1/A2, Save registers D0, D1, and A2. 16(A7),D1 Initialize coun ter to n SUBQ.L #1,D1 Adjust count use DBRA. VEA.L 20(A7),A2 Initialize pointer the list. CLR.L sum 0. LOOP ADD.W (A2)+,D0 Add entry from DBRA D1,LOOP D0,20(A7) Put result on stac k. (A7)+,D0 D1/A2 registers. R TS – [D0] [D1] [A2] Return address n NUM1 Level 3 Lev el 2 1  55:035 Computer Architecture and Organization

68K Program Example Byte sorting program C program Assembly program for (j = n 1; j > 0; 1) { ( k 1 ) if (LIST[ ] LIST[ ] ) TEMP ]; TEMP; } – MO VEA.L #LIST,A1 P ointer to the start of list. VE N,D1 Initialize outer lo op SUBQ #1,D1 index j in D1. OUTER D1,D2 inner #1,D2 k D2. VE.B (A1,D1),D3 Current maximum value in D3. INNER CMP .B D3,(A1,D2) If LIST( ) [D3], BLE NEXT do not exchange. (A1,D2),(A1,D1) In terchange LIST(k) and load new maxim um D3. DBRA D2,INNER Decrement counters k and j branch back BGT if finished.  55:035 Computer Architecture and Organization

IA-32 Intel Corporation developer.intel.com Microprocessor used in PCs and Apple computers Processor Families Desktop processors Server and workstation processors Internet device processors Notebook processors Embedded and communications processors 55:035 Computer Architecture and Organization

IA-32 Intel microprocessor history 55:035 Computer Architecture and Organization

IA-32 Example P6 Microarchitecture 55:035 Computer Architecture and Organization

IA-32 Example The centerpiece of the P6 processor microarchitecture is an out-of-order execution mechanism called dynamic execution. Dynamic execution incorporates three data processing concepts: Deep branch prediction allows the processor to decode instructions beyond branches to keep the instruction pipeline full. Dynamic data flow analysis requires real-time analysis of the flow of data through the processor to determine dependencies and to detect opportunities for out-of-order instruction execution. Speculative execution refers to the processor’s ability to execute instructions that lie beyond a conditional branch that has not yet been resolved, and ultimately to commit the results in the order of the original instruction stream. 55:035 Computer Architecture and Organization

IA-32 Register Structure
8 32-bit Data Registers 8 64-bit Floating Point Registers 6 Segment Registers R0 R1 31 R7 FP0 FP1 FP7 63 CS 16 SS ES FS GS DS Code Segment Stack Segment Data Segments General purpose registers 8 Floating-point Segment 6 55:035 Computer Architecture and Organization

IA-32 Register Structure
32-bit Instruction pointer Status register Privilege level Condition codes 31 13 11 9 7 Instruction pointer CF - Carry ZF - Zero SF - Sign TF - Trap IOPL - Input/Output OF - Overflow IF - Interrupt enable Status register 12 8 6 privilege level 55:035 Computer Architecture and Organization

IA-32 Instruction Format
Prefix 1 to 4 OP code ModR/M SIB Displacement Immediate bytes 1 or 2 1 byte 1 or 4 Addressing mode Variable instruction length (CISC) See appendix D 55:035 Computer Architecture and Organization

IA-32 Addressing Modes Name Assembler syntax Addressing function Immediate V alue Op erand = Direct Lo cation EA Register Reg that is, [Reg] indirect Base with [Reg + Disp] Disp displacement Index S index [Reg1 Reg2 * S] [Reg1] [Reg2] Reg2 * S + Disp] and *  where: Value = an 8- or 32-bit signed number Location = a 32-bit address Reg, Reg1, Reg2 = one of the general purpose registers EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI, with the exception that ESP cannot be used as an index register Disp = an 8- or 32-bit signed number, except that in the Index with displacement mode it can only be 32 bits S = scale factor of 1, 2, 4, or 8 55:035 Computer Architecture and Organization

IA-32 Instructions Arithmetic examples ADC, ADD, CMC, DEC, DIV, IDIV, IMUL, MUL SBB, SUB Logic examples AND, CLC, STC NEG, NOP, NOT, OR, XOR 55:035 Computer Architecture and Organization

IA-32 Instructions Shift examples RCL, RCR, ROL, ROR, SAL, SAR, SHL, SHR Bit test and compare BT, BTC, BTR, BTS, CMP, TEST Branch examples CALL, RET, CLI, STI, HLT, INT, IRET LOOP, LOOPE, Memory/IO load and store examples LEA, MOV, MOVSX, MOVZX IN, OUT, POP, POPAD, PUSH, PUSHAD XCHG 55:035 Computer Architecture and Organization

IA-32 Assembly Language Assembler directives .data NUM1 DD 17 , 3 51 242 113 N 5 SUM .code Statements that generate machine instructions MAIN : LEA EBX SUB 4 MO V ECX EAX STARTADD : ADD [EBX +ECX 4] LOOP ST AR T END *  55:035 Computer Architecture and Organization

IA-32 Subroutines Calling program PUSH OFFSET NUM1 Push parameters on to the stack. N CALL LIST ADD Branc h subroutine. ESP ,4 Remo v e n from POP SUM P op sum in SUM. . Subroutine ADD: EDI Sa and use MO V EDI,0 as index register. EAX EAX,0 accummulator register. EBX load EBX,[ESP+20] address NUM1. ECX ECX,[ESP+20] count ST AR T EAX,[EBX+EDI 4] Add next umber. INC Incremen t index. DEC Decremen coun ter. JG bac k if not done. [ESP+24],EAX Ov erwrite stac with sum. Restore registers. RET Return. * [ECX] [EBX] [EAX] [EDI] Return Address n NUM1 Lev el 3 2 1  55:035 Computer Architecture and Organization

IA-32 Program Example Byte sorting program C program Assembly program for (j = n 1; j > 0; 1) { ( k 1 ) if (LIST[ ] LIST[ ] ) TEMP ]; TEMP; } – LEA EAX,LIST Load list p oin ter base MO V EDI,N register (EAX), and initialize DEC EDI outer lo op index (EDI) to j = n 1. OUTER: ECX,EDI Initialize inner ECX (ECX) k DL,[EAX + EDI] LIST(j) in DL. INNER: CMP [EAX ECX],DL Compare LIST(k) LIST(j). JLE NEXT If LIST(j), go next w er entry; X CHG Otherwise, interchange LIST(k) leaving EDI],DL new NEXT: Decrement inner loop index k. JGE INNER Repeat or terminate inner loop. Decrement outer loop index j. JG OUTER Repeat or terminate outer loop. –  55:035 Computer Architecture and Organization

55:035 Computer Architecture and Organization

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