1. Register-Transfer (RT) Synthesis Greg Stitt ECE Department University of Florida

2. Introduction Register-transfer (RT) synthesis Definition: Synthesis from register transfer level (RTL) descriptions VHDL, Verilog typically describe circuits as connections of RTL components What are register-transfer level components? Muxes, ALUs, registers, multipliers, etc. One abstraction level above gates Basically, components you use in most structural descriptions What are other levels? Transistor level Gate level Register transfer level High level System level Etc.

3. RT Synthesis Main Steps Lex/Parsing Analyzes HDL, converts into intermediate representation Resource Allocation Maps intermediate representation into RT components Optimizations Logic minimization State minimization State encoding Etc. Technology Mapping Placement + Routing

4. Technology Mapping Converts circuit from one technology (e.g. gates) onto technology used by physical device (e.g. LUTs, CLBs, etc) CLB

5. Placement Input: Technology-mapped circuit For simplicity, just consider CLBs Technology-mapped circuit consists of “virtual” CLBs and “virtual” connections FPGA fabric consists of physical CLBs Simplified Placement Definition: Map “virtual” CLBs onto physical CLBs I.e. Decide on a location in the FPGA for each virtual CLB 1234 6 5 CLB 1234 5 6 Technology Mapped Circuit FPGA Fabric Possible Placement

6. Routing Input: A set of placed components, and a list of “virtual” connections Simplified Routing Definition: Determine how to configure routing resources to implement “virtual” connections 1234CLB 5 6 1234 6 5 Physical CLBs not connected – must configure routing resources to implement these connections:

7. Placement+Routing (PAR) Placement and routing highly dependent Placement affects how well circuit can be routed Example: 1234 6 5 1234CLB 5 6 63 1 4 2 5 Placement 1Placement 2 Clearly, placement 1 is easier to route

8. Placement+Routing (PAR) Goals: 1) Make sure circuit can be implemented on fabric Trivial for placement, difficult for routing Bad placement may make circuit unroutable 2) Minimize delay of critical path Critical path is the longest register to register delay Important - Determines clock speed of circuit Why is placement and routing important? Bad PAR = slow circuit Even worse, BAD PAR = no circuit 1234CLB 5 6 63 1 4 2 5 Even if routing is possible, placement 2 likely to have longer wires – slower clock Placement 2 Placement 1

9. Placement Problem: Find a placement for each CLB, such that routing can maximize clock speed Challenges: 1) Huge solution space! Tiny Example: Fabric = 100 physical CLBs, Circuit = 10 “virtual” CLBs Possibilities = 100! / 90! = 6.2 * 10 19 And, that is for a tiny fabric and tiny circuit!!!!!!!!!!! Guess what … placement is NP-Complete 2) How to know how good the routing will be? One (im)possibility - perform routing for each possible placement Tiny example, cont. - assume same number of routing possibilities as placement possibilities 6.2 * 10 19 * 6.2 * 10 19 = A BIG NUMBER! Routing is also NP-complete Cleary, placement needs to estimate quality of routing Estimate known as a cost function

10. Cost Function Examples Example: average wire length Motivation: short wires faster than long wires Not perfect - many short wires not on critical path may lead to inaccuracy i.e. critical path may still be long despite short average wire length How to determine wire length? Without routing, don’t know length Possibilities: 1) Euclidian distance - measure straight line distance between CLBs Ignores how wire would be routed (can’t route diagonals) 2) Manhattan distance - shortest “zig-zag” distance Includes bends between CLBs CLB Euclidian Distance Manhattan Distance

11. Placement Techniques Placement is an NP-complete optimization problem Many possible placements, we want the best one What does this suggest for a solution? Remember last lecture! 1) Branch and bound Likely not feasible 2) Map to other NP-complete problem - use heuristic for that problem 3) Use general optimization heuristics Simulated annealing Hill climbing Very common (notice the temperature numbers in Xilinx ISE) How to use general optimization heuristics? Cost function represents quality of placement Neighboring solution – try new location for a “virtual” CLB, swap 2 CLBs, etc.

12. Placement Techniques Also common to map placement to other NP- complete problems Example: Min-cut problem Background: Given a graph, a cut is a set of edges that divides the graph into two (or more) groups Min-cut problem definition: Find the minimum cut size for a given graph Similar to graph bipartitioning problem Cutsize = 5 Cutsize = 3

13. Placement Techniques How can graph bipartitioning/min-cut be used for placement? Graph: Nodes are CLBs, Edges are wires Partition divides FPGA into sections Goal: minimize communication between sections Bipartitioning attempts to reduce routing “congestion” i.e. Cost function is cut size We can use common heuristic for graph bipartitioning Kernighan-Lin (KL) Heuristic

14. Placement Techniques KLFM Heuristic (Kernighan-Lin Fiduccia-Mattheyses) Basic Idea: Start with initial partition Iteratively improves cutsize Cutsize is number of edges between partitions Moves one node at a time Node that gives greatest reduction or least degradation Lock node after moving Continue moving nodes until all locked or size constraints are violated Find best partitioning, unlock all nodes Repeat until no improvement found

15. KLFM Algorithm Initial Partition Cutsize = 5 Size = 3 Maximum Size = 4

16. KLFM Algorithm Cutsize = 3 Size = 4Size = 2 Maximum Size = 4

17. KLFM Algorithm Cutsize = 2 Size = 3 Maximum Size = 4

18. KLFM Algorithm Cutsize = 2 Size = 2Size = 4 Maximum Size = 4

19. KLFM Algorithm Cutsize = 4 Size = 3 Maximum Size = 4

20. KLFM Algorithm Cutsize = 4 Size = 2Size = 4 Maximum Size = 4

21. KLFM Algorithm Cutsize = 5 Size = 3 Maximum Size = 4

22. KLFM Algorithm Cutsize = 2 Size = 3 Backtrack to minimum cut size, unlock nodes, and repeat

23. Circuit Partitioning How does a partition help us place CLBs? Apply bipartitioning hierarchically – circuit partitioning Basic idea 1) Initially divide FPGA into 2 sections Execute bipartitioning to determine which section “virtual” CLBs get mapped into 2) Divide each section into 2 subsections Execute bipartitioning to determine which subsection “virtual” CLBs get mapped into 3) Divided each subsection into 2 subsubsections And so on